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* ArmPkg: Introduce support for PcdFfaEnableSughosh Ganu2021-02-231-0/+7
| | | | | | | | | | | | The Secure Partition(SP) can request services from the Secure Partition Manager Core(SPMC) either through FF-A calls or through the existing SVC calls. Add a feature flag Pcd for enabling the FF-A method -- when this is set to FALSE, the SP uses the existing SVC calls for making the requests. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg: Add SMBIOS PCDs to ArmPkg.decRebecca Cran2021-02-081-0/+17
| | | | | | | | Platforms are expected to override these PCDs to provide relevant information to SMBIOS. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmSmcPsciResetSystemLib: remove EnterS3WithImmediateWake ()Ard Biesheuvel2020-01-141-4/+0
| | | | | | | | | | | | EnterS3WithImmediateWake () no longer has any callers, so remove it from ResetSystemLib. Note that this means the hack to support warm reboot by jumping to the SEC entry point with the MMU and caches off is also no longer used, and can be removed as well, along with the PCD PcdArmReenterPeiForCapsuleWarmReboot that was introduced for this purpose. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmScmiDxe: Add clock enable functionJeff Brasen2018-12-211-0/+1
| | | | | | | | | | | | | | | | Add function to allow enabling and disabling of the clock using the SCMI interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that support new API from those that just have the older protocol. SCMI_CLOCK2_PROTOCOL also adds a version parameter to allow for future changes. It is placed after the functions that are present in the existing protocol to allow SCMI_CLOCK2_PROTOCOL to be cast to SCMI_CLOCK_PROTOCOL so that only a single implementation of those function are needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: drop ArmBds remnant Pcds from .decLeif Lindholm2018-12-191-20/+0
| | | | | | | | | | | | | | | | The following Pcds - gArmTokenSpaceGuid.PcdArmLinuxSpinTable - gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset - gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset - gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment remained defined, without actual users. So get rid of them. One reference to be deleted separately from edk2-platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib: Add MMU Library suitable for use in S-EL0.Achin Gupta2018-11-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | The Standalone MM environment runs in S-EL0 in AArch64 on ARM Standard Platforms. Privileged firmware e.g. ARM Trusted Firmware sets up its architectural context including the initial translation tables for the S-EL1/EL0 translation regime. The MM environment will still request ARM TF to change the memory attributes of memory regions during initialization. The Standalone MM image is a FV that encapsulates the MM foundation and drivers. These are PE-COFF images with data and text segments. To initialise the MM environment, Arm Trusted Firmware has to create translation tables with sane default attributes for the memory occupied by the FV. This library sends SVCs to ARM Trusted Firmware to request memory permissions change for data and text segments. This patch adds a simple MMU library suitable for execution in S-EL0 and requesting memory permissions change operations from Arm Trusted Firmware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add PCDs needed for MM communication driver.Achin Gupta2018-11-271-0/+3
| | | | | | | | | | This patch defines PCDs to describe the base address and size of communication buffer between normal world (uefi) and standalone MM environment in the secure world. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add initial OpteeLib implementationSumit Garg2018-08-011-0/+1
| | | | | | | | | | | This is initial version of OP-TEE library that provides api's to communicate with OP-TEE OS (Trusted OS based on ARM TrustZone) via secure monitor calls. Currently it provides basic api to detect OP-TEE presence via UID matching. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm rebootArd Biesheuvel2018-06-151-0/+4
| | | | | | | | | | | | | | Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Introduce SCMI protocolGirish Pathak2018-04-231-0/+13
| | | | | | | | | | | | | | | | | | | This change introduces a new SCMI protocol driver for Arm systems. The driver currently supports only clock and performance management protocols. Other protocols will be added as and when needed. Clock management protocol is used to configure various clocks available on the platform e.g. HDLCD clock on the Juno platforms. Whereas performance management protocol allows adjustment of various performance domains. Currently this is used to evaluate performance of the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: MTL Library interface and Null library implementationGirish Pathak2018-04-231-1/+2
| | | | | | | | | | | | | Upcoming new component ArmPkg/Drivers/ArmScmiDxe is dependent on platform specific ArmMtlLib library implementation, however in order to be able to build the ArmScmiDxe component outside of the context of a particular platform, this change adds Null implementation of the ArmMtlLib along with ARM MTL library header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: order CpuDxe after ArmGicDxe via protocol depexLaszlo Ersek2018-04-121-2/+0
| | | | | | | | | | | | | | | | | | | | | | Commit 61a7b0ec634f ("ArmPkg/Gic: force GIC driver to run before CPU arch protocol driver", 2018-02-06) explains why CpuDxe should be dispatched after ArmGicDxe. To implement the ordering, we should use a regular protocol depex rather than the less flexible AFTER opcode. ArmGicDxe installs gHardwareInterruptProtocolGuid and gHardwareInterrupt2ProtocolGuid as one of the last actions on its entry point stack; either of those is OK for CpuDxe to wait for. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Gic: force GIC driver to run before CPU arch protocol driverArd Biesheuvel2018-02-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Currently, the GIC driver has a static dependency on the CPU arch protocol driver, so it can register its IRQ handler at init time. This means there is a window between dispatch of the CPU driver and dispatch of the GIC driver where any unexpected GIC state may trigger an interrupt which we are not set up to handle yet. Note that this is even the case if we enter UEFI with interrupts disabled at the CPU, given that any TPL manipulation involving TPL_HIGH_LEVEL will unconditionally enable IRQs at the CPU side regardless of whether they were enabled to begin with (but only as soon as the CPU arch protocol is actually installed) So let's reorder the GIC driver with the CPU driver, and let it run its initialization that puts the GIC into a known state before enabling interrupts. Move its installation of its IRQ handler to a protocol notify callback on the CPU arch protocol so that it runs as soon as it becomes available. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com>
* ArmPkg: remove BdsLib and remaining ARM BDS related PCDsArd Biesheuvel2017-11-261-8/+0
| | | | | | | | | With the last user FdtPlatformDxe removed, we can finally get rid of the last bit of ARM BDS related cruft. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove unused ArmGicSecLib library implementationArd Biesheuvel2017-11-261-2/+2
| | | | | | | | | | | This module is not used anywhere under edk2 or edk2-platforms, so let's remove it. This removes the only dependency on ArmPlatformLib from ArmPkg. While at it, remove a mention of ArmPlatformPkg from a comment in the .dec file as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Include: Add ArmSvcLib header file.Supreeth Venkatesh2017-10-061-0/+1
| | | | | | | | | | ArmSvcLib header file to specify the SVC arguments structure and function prototype to trigger an SVC call. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove UncachedMemoryAllocationLibArd Biesheuvel2017-08-311-4/+0
| | | | | | | | | | | | | | Now that ArmDmaLib can take care of its own memory allocation needs, let's get rid of UncachedMemoryAllocationLib entirely. This forces platforms to declare the required semantics (non-cache coherent DMA, whichever way it is implemented), rather than using uncached memory allocations directly, which may not always be the right choice, and prevents sharing of drivers between platforms if one is cache coherent and the other is not. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove unused PcdArmUncachedMemoryMask PCDArd Biesheuvel2017-02-271-1/+0
| | | | | | | | | | | | This removes the PCD PcdArmUncachedMemoryMask from ArmPkg, along with any remaining references to it in various platform .DSC files. It is no longer used now that we removed the virtual uncached pages protocol and the associated DebugUncachedMemoryAllocationLib library instance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: remove VirtualUncachedPages protocol and implementationArd Biesheuvel2017-02-231-3/+0
| | | | | | | | | | Virtual uncached pages are simply pages that are aliased using mismatched attributes, which is not allowed by the ARM architecture. So remove the protocol and its implementation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/GenericWatchdogDxe: Declare MMIO PCDs as UINT64Alexei2017-02-071-3/+3
| | | | | | | | | | | | | | PcdGenericWatchdogControlBase & PcdGenericWatchdogRefreshBase are declared as UINT32 values in ArmPkg.dec, but for platforms with addresses in the memory range above 4GB this causes build error F000: Too large PCD value for datum type [UINT32] of PCD gArmTokenSpaceGuid.PcdGenericWatchdogControlBase Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=361 Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmDmaLib: add support for fixed host-to-device DMA offsetArd Biesheuvel2016-11-301-0/+8
| | | | | | | | | | | | Some devices, such as the Raspberry Pi3, have a fixed offset between memory addresses as seen by the host and as seen by the other bus masters. So add a new PCD that allows this fixed offset to be recorded, and to be used when returning device addresses from the DmaLib mapping routines. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen2016-09-081-3/+3
| | | | | | | | | | | According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: introduce ArmMmuLib library classArd Biesheuvel2016-07-071-0/+1
| | | | | | | | | Introduce the library class ArmMmuLib, which encapsulates the functionality to set up and modify page table entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: move PCI related PCD definitions to ArmPkgArd Biesheuvel2016-04-291-0/+62
| | | | | | | | | | | | | | The PCI related PCDs are not platform specific, and architectural protocols such as CpuIo2 are based on PCI provided MMIO to IO translation, so these PCDs belong in ArmPkg not ArmPlatformPkg. NOTE: this *WILL* break some out-of-tree platforms, the fix is changing all consumers of gArmPlatformTokenSpaceGuid.PcdPci* to gArmTokenSpaceGuid.PcdPci* Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg|EmbeddedPkg: make PcdCpuVectorBaseAddress 64 bits wideLeendert van Doorn2016-03-251-2/+2
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmV7Mmu: introduce feature PCD to map normal memory non-shareableArd Biesheuvel2015-11-181-0/+6
| | | | | | | | | | | | | | | Even though mapping normal memory (inner) shareable is usually the correct choice on coherent systems, it may be desirable in some cases to use non-shareable mappings for normal memory, e.g., when hardware managed coherency is not required and the memory system is not fully configured yet. So introduce a PCD PcdNormalMemoryNonshareableOverride that makes cacheable mappings of normal memory non-shareable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18897 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: split off ArmGicArchLib from ArmGicLibArd Biesheuvel2015-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | The current implementation of ArmGicGetSupportedArchRevision () that is used by all ARM platforms is entirely stateless (in order to support being executed from flash) so it needs to interrogate the hardware for the supported GIC revision upon each invocation. However, this statelessness is only needed for SEC type modules; in all other cases, we could easily determine the GIC revision once, and store the result in a global variable. In preparation of having separate early and normal versions, this patch introduces the ArmGicArchLib library class and default implementation, and moves the existing ArmGicGetSupportedArchRevision () into it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Remove PCD declarations linked to the ARM BDS Linux LoaderOlivier Martin2015-07-141-1/+0
| | | | | | | | | | | | | The Linux Loader has been removed from ARM BDS. These PCDs are not needed anymore. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <Olivier.Martin@arm.com> Reviewed-by: Ronald Cron <Ronald.Cron@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17973 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: remove cache maintenance by VA operation range size thresholdArd Biesheuvel2015-04-141-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This removes the range size threshold for virtual address based cache maintenance instructions that operate on VA ranges to be 'promoted' to use set/way instructions. Doing so is unsafe: set/way operations are fundamentally different from VA operations, and really only suitable for cleaning or invalidating a cache when turning it on or off. To quote the ARM ARM (DDI0487A_d G3.4): """ Since the set/way instructions are performed only locally, there is no guarantee of the atomicity of cache maintenance between different PEs, even if those different PEs are each performing the same cache maintenance instructions at the same time. Since any cacheable line can be allocated into the cache at any time, it is possible for [a] cache line to migrate from an entry in the cache of one PE to the cache of a different PE in a manner that the cache line avoids being affected by set/way based cache maintenance. Therefore, ARM strongly discourages the use of set/way instructions to manage coherency in coherent systems. """ Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Olivier Martin <Olivier.Martin@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17176 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: allow patchable PCDs for memory, FD and FV addressesArd Biesheuvel2015-02-281-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to allow a runtime self relocating PrePi instance, change the allowable PCD types for the following PCDs: gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdFdBaseAddress gArmTokenSpaceGuid.PcdFvBaseAddress to include PcdsPatchableInModule. This makes the build system correctly distinguish fixed PCDs from PCDs whose value may be different from the assigned value at compile time. Note that this only affects platforms that explicitly mark these PCDs as PatchableInModule in the DSC. All existing platforms that use FixedPcd will not be affected by this change. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16954 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native modeArd Biesheuvel2015-02-161-0/+3
| | | | | | | | | | | | | | | | | | | | | The GICv3 driver must use native mode to drive a GICv3 due to the fact that v2 compatibility is optional in the v3 spec. However, if v2 compatibility is implemented, it is the default and needs to be disabled first by setting the Affinity Routing Enable (ARE) bit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> [added PCD that allows forcing the GICv3 driver to drive the GIC in v2 mode] Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16875 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Added GICv3 specific definitionsOlivier Martin2015-02-161-1/+3
| | | | | | | | | | | | | | | | | | ARM GICv3 specification introduces some new components and registers. This patch adds their definitions. The most important GICv3 component is the GIC Redistributor. It supports LPIs (Locality-specific peripheral Interrupt), 8+ CPU configuration. Some GIC distributor registers have moved to the GIC redistributor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16872 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg: Move the watchdog generic driver to ArmPkg/DriversRonald Cron2014-12-121-0/+8
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16512 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.Leif Lindholm2014-11-111-4/+4
| | | | | | | | | | | | | | Some AArch64 platforms have RAM and flash devices >4GB. Update some additional Pcd entries to 64-bit, and change the corresponding PcdGet32 calls to PcdGet64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/UncachedMemoryAllocationLib: Track uncached memory allocationsOlivier Martin2014-10-101-0/+3
| | | | | | | | | | | | | Keeping track of uncached memory allocations prevents doing expensive cache operations (eg: clean & invalidate) on newly allocated regions by reusing regions where possible Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16205 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPsciResetSystemLib: Made the library only using SMCOlivier Martin2014-10-101-8/+0
| | | | | | | | | | | | Only ArmVirtualizationPkg based platforms are expected to use the dynamic method to choose between SMC and HVC to invoke PSCI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16204 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Introduced ArmPsciResetSystemLibArd Biesheuvel2014-09-101-0/+8
| | | | | | | | | | | | | | This implementation of EfiResetSystemLib uses ARM PSCI calls to perform reboot and poweroff, using either HVC or SMC calls. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16089 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg,ArmPlatformPkg: Allow dynamic PCDs for memory base and sizeArd Biesheuvel2014-09-091-6/+6
| | | | | | | | | | | | | | | | | | | | | This changes the definition and a bunch of references to gArmTokenSpaceGuid.PcdSystemMemoryBase and gArmTokenSpaceGuid.PcdSystemMemorySize so they can be declared as dynamic PCDs by the platform. Also, move the non-SEC call to ArmPlatformInitializeSystemMemory() earlier, so a platform has a chance to set these PCDs before they are first referenced. The purpose is allowing dynamically instantiated virtual machines to declare the system memory by passing a device tree. Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16079 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: allow dynamic GIC base addressesArd Biesheuvel2014-09-091-7/+11
| | | | | | | | | | | | | | | | | | Allow the PCDs gArmTokenSpaceGuid.PcdGicDistributorBase and gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase to be redeclared as PcdsDynamic by the platform, so virtual machines can set these properties during boot. As the PcdGet32() calls now call into the PCD database, cache the values that are required during the handling of interrupts. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16072 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: allow dynamically discovered timer interruptsArd Biesheuvel2014-09-091-10/+13
| | | | | | | | | | | | | | | To support booting on virtual machines whose interrupt routing is discovered from the device tree, allow the interrupt numbers to be redeclared as PcdsDynamic by the platform .dsc Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16071 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPkg.dec: Added the interrupt numbers for the Hypervisor and ↵Olivier Martin2014-07-291-1/+4
| | | | | | | | | | | | | | | Virtual Timers These numbers are mainly to reduce hardcoded numbers into the ACPI GTDT table. And also to match with the use of PcdArmArchTimerSecIntrNum and PcdArmArchTimerIntrNum into the GTDT ACPI Table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15707 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Removed PSCI discoverability from the Linux loaderOlivier Martin2014-07-151-2/+3
| | | | | | | | | | | | | | | Some platforms might decide to not support PSCI in their FDT-aware Linux system even if their firmware supports it. It is the responsibility of the platform engineer to provide the appropriate FDT. The PCD gArmTokenSpaceGuid.PcdArmPsciSupport is not required anymore. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15658 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Added support for TFTP servers without 'tsize' extensionOlivier Martin2014-05-191-0/+2
| | | | | | | | | | | | | Some TFTP servers do not have 'tsize' extension. This change allows to download files from TFTP servers that do not have this extension by trying to download the file into a pre-allocated buffer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15539 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Fix typo in comment and trailing spacesOlivier Martin2014-03-241-15/+15
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15378 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64Olivier Martin2014-01-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The System Memory region might be out of the 32-bit memory space. This change has been validated on the FVP AArch64 model using 4GB of DRAM at 0x8_0000_0000: - # System Memory (2GB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + # System Memory (4GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 EFI Shell and Linux kernel boot successfully. Note: This change has not been validated on AArch32. I expect some early assembly code to not work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Renamed PL390Gic driver into ArmGic driverOlivier Martin2013-10-291-1/+1
| | | | | | | | | | | | The aim is to make this driver follows the ARM GIC specifications and be implementation independent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3Olivier Martin2013-08-211-18/+40
| | | | | | | | | | | This is already taken care by Sec when PcdTrustzoneSupport = TRUE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
* ARM: Remove NSACR from the common codeOlivier Martin2013-08-061-9/+9
| | | | | | | | | | | NSACR (Non-Secure Access Control Register) is AArch32 specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Added Aarch64 support for booting LinuxHarry Liebel2013-07-181-0/+6
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14487 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 21:29:07 +0000