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* ArmPkg/ArmGicLib: Fix GICR_IPRIORITYR address wrong issueMing Huang2021-03-011-1/+4
| | | | | | | | | | | | | The register address of GICR_IPRIORITYR is in SGI_base frame. Add IPRIORITY_ADDRESS macro for getting GICR_IPRIORITYR address. Otherwise GIC RAS error(Uncorrected software error) may report in ArmGicDxe. This resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3236 Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Tested-by: Ard Biesheuvel <ardb@kernel.org> # QEMU/kvm guest on ThunderX2 Tested-by: Quan Nguyen <quan@os.amperecomputing.com>
* ArmPkg/ArmGicLib: Fix two macros issue for offset parameterMing Huang2021-03-011-2/+2
| | | | | | | | Modify two macros to put "offset" in parentheses and remove parentheses from "4 * offset". Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmGicLib: Add ArmGicSetInterruptPriority() helper functionQuan Nguyen2020-12-181-0/+44
| | | | | | | | | | | | | | | | According to ARM IHI 0069F, section 11.9.18 GICD_IPRIORITYR<n>, Interrupt Priority Registers, n = 0 - 254, when affinity routing is enabled for the Security state of an interrupt, GICR_IPRIORITYR<n> is used instead of GICD_IPRIORITYR<n> where n = 0 to 7 (that is, for SGIs and PPIs). As setting interrupt priority for SGIs and PPIs are handled using difference registers depends on the mode, this patch instroduces ArmGicSetInterruptPriority() helper function to handle the discrepancy. Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Reviewed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add support for GICv4Sami Mujawar2018-10-121-14/+26
| | | | | | | | | | | | | | | | | | | | Updated Redistributor base calculation to allow for the fact that GICv4 has 2 additional 64KB frames (for VLPI and a reserved frame). The code now tests the VLPIS bit in the GIC Redistributor Type Register (GICR_TYPER) and calculates the Redistributor granularity accordingly. The code changes are: GICR_TYPER register fields, etc, added to the header. Loop updated to pay attention to GICR_TYPER.Last. Derive frame "stride" size from GICR_TYPER.VLPIS. Note: The assumption is that the redistributors are adjacent for all CPUs. However this may not be the case for NUMA systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Tidy GIC code before changes.Evan Lloyd2017-10-051-16/+57
| | | | | | | | | | | | | | | | | | | This change is purely cosmetic, to tidy some code before change. Mods involve: Re-order #includes Reformat comments. Use ns consistently (always "100ns" not sometimes "100 nS") Split overlength code lines. Make protocol functions STATIC. Remove "Horor vacui" comments. Rationalize GIC register address calculations Replace explicit test and assert with ASSERT_EFI_ERROR. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicLib: use correct loop variableArd Biesheuvel2016-09-091-1/+1
| | | | | | | | | | | The ArmGicLib API function GicGetCpuRedistributorBase () declares GicCpuRedistributorBase to iterate over the redistributors of all CPUs, but then inadvertently advances GicRedistributorBase instead. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributorArd Biesheuvel2016-07-131-3/+22
| | | | | | | | | | | | Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon <ndhillonv2@gmail.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: merge ArmGicV[23]Lib.h into ArmGicLib.hArd Biesheuvel2015-07-281-3/+0
| | | | | | | | | | | | | | | | | | | Before splitting off ArmGicArchLib and moving it out of ArmPkg/Drivers/ArmGic into ArmPkg/Library, make sure that the GIC specific declarations it depends on are not hidden away in local headers "GicV2/GicV2Lib.h" and "GicV3/GicV3Lib.h". So merge them with <Library/ArmGicLib.h>. This is entirely appropriate, since this is not a header that declares a public interface into ArmGicLib, but defines implementation internals. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18097 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native modeArd Biesheuvel2015-02-161-3/+3
| | | | | | | | | | | | | | | | | | | | | The GICv3 driver must use native mode to drive a GICv3 due to the fact that v2 compatibility is optional in the v3 spec. However, if v2 compatibility is implemented, it is the default and needs to be disabled first by setting the Affinity Routing Enable (ARE) bit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> [added PCD that allows forcing the GICv3 driver to drive the GIC in v2 mode] Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16875 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3Olivier Martin2015-02-161-11/+57
| | | | | | | | | | | | | | | GICv3 controller with no GICv2 legacy support must use the GIC Redistributor registers instead of the GIC Distributor registers for some operations (eg: enable/disable interrupts). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16874 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Function to locate the current CPU GIC redistributorOlivier Martin2015-02-161-1/+55
| | | | | | | | | | | | | | | | | | CPU GIC Registributors are located next to each other in the GIC Redistributor space. The CPU GIC Redistributor is identified by its CPU affinity Aff3.Aff2.Aff1.Aff0. This function returns the base address of the GIC Redistributor of the calling CPU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16873 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Added GicV3 support to ArmGicLibOlivier Martin2014-10-271-0/+9
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16233 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Added GicV3 detectionOlivier Martin2014-10-271-9/+0
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16232 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Introduced ArmGicGetSupportedArchRevision()Olivier Martin2014-10-271-12/+49
| | | | | | | | | | | | | | This function returns the revision of the GIC Architecture. Some GICv3 controllers can work in GICv2 mode. Switching to an older GIC revision is driven by the higher level exception level. This function allows code to support any GIC revision at runtime. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16231 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Corrected non-DOS line endingsRonald Cron2014-08-191-1/+1
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15832 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Returned the InterruptId in ArmGicAcknowledgeInterrupt()Olivier Martin2014-07-041-2/+29
| | | | | | | | | | | | | | | | The InterruptId has a different width for GicV2 and GicV3 (respectively 10bit and 24bit). The function prototype has been changed to return this value to make the caller GIC architecture version independent. Otherwise, we would have need to expose a different mask to allow the caller to retrieve this value from the read register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15628 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicLibOlivier Martin2014-07-041-3/+22
| | | | | | | | | | | | The support for GIcV2 was already existing. This change separate the GicV2 specific functions from the common Gic code (in preparation for GicV3 support). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15626 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Moved ArmGicDisableDistributor() to ArmGicLib.cOlivier Martin2014-07-041-3/+12
| | | | | | | | | | | | The implementation is the same when we run in Secure or Non-Secure world. This change makes this function available for ArmGicSec.inf and ArmGicNonSec.inf. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15625 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLib (cont)Olivier Martin2014-07-041-0/+122
... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. The renaming did not work well with SVN. Files were missing from the initial commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15622 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 06:53:43 +0000