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* ArmPkg/CompilerIntrinsicsLib: Add lasr ARM assembly source for GCCPete Batard2019-05-132-0/+31
| | | | | | | | | The new source is a port of the RVCT version. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: Add memcmp, memmove intrinsics for MSFTPete Batard2019-05-133-0/+67
| | | | | | | | | | We could have reused memmove.asm for ARM, but we would still need to add an implemention for ARM64, so we use the same source for both archs. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: Remove unused sources and clean up .infPete Batard2019-05-1319-1633/+37
| | | | | | | | | | | None of the .c/.h in Arm/ are used any more => remove them. Also merge the CC flags for MSFT ARM and ARM64, since these are the only archs we support for this package. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSmcPsciResetSystemLib: Add a new API ResetSystemZhichao Gao2019-04-281-0/+44
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460 Add a new API ResetSystem to this ResetSystemLib instance. It only adds the basic functions from ResetSystemRuntimeDxe. Lacking of this interface may cause link error, if some drivers use this new API and link to this library instance. Notes: This library API only provide a basic function of reset. Full function should use the instance in the MdeModulePkg and make sure the depex driver is dispatched. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-09186-1290/+186
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/SemiHostingDebugLib: Add new APIsBret Barkelew2019-04-021-5/+101
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidationArd Biesheuvel2019-01-293-20/+20
| | | | | | | | | | | | | | | | | | | Currently, we always invalidate the TLBs entirely after making any modification to the page tables. Now that we have introduced strict memory permissions in quite a number of places, such modifications occur much more often, and it is better for performance to flush only those TLB entries that are actually affected by the changes. At the same time, relax some system wide data synchronization barriers to non-shared. When running in UEFI, we don't share virtual address translations with other masters, unless we are running under virt, but in that case, the host will upgrade them as appropriate (by setting an override at EL2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: trim high memory regions instead of rejecting themArd Biesheuvel2019-01-281-1/+2
| | | | | | | | | | | | | | | ArmSetMemoryAttributes() still chokes in some cases, i.e., when the length of the region exceeds 4 GB, the subtraction overflows, which results in the region being misidentified as being 32-bit addressable. Let's update the logic to trim the length to what we can address with 32 bits. This fixes the issue, and also deals with the issue where an entire region is disregarded if part of it exceeds beyond what we can map with 32 bits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: add missing UefiLib includeArd Biesheuvel2019-01-171-0/+1
| | | | | | | | | | | | Commit 31f5388006fc ("ArmPkg/DefaultExceptionHandlerLib: use console if available") added calls to AsciiPrint() to the default exception handler code, but the ARM version did not include UefiLib.h yet (even though the .INF declares it unconditionally), resulting in build breakage. So add the missing include. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: use console if availableArd Biesheuvel2019-01-163-3/+16
| | | | | | | | | | | | Print the minimal 'exception occurred' message to the console as well as to the serial port if the console is available. This makes such messages visible on systems where the console is graphical and the serial is not connected. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/DefaultExceptionHandlerLib: drop BASE variantArd Biesheuvel2019-01-162-80/+0
| | | | | | | | | | Drop the redundant BASE variant, which is no longer used anywhere now that DebugAgentSymbolsBaseLib no longer incorporates a vector table and exception handling. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: declare the permitted usage contextArd Biesheuvel2019-01-161-2/+2
| | | | | | | | | | | Declare that this library is only usable in the context of DXE core or a DXE driver. Set the MODULE_TYPE to BASE: this only affects the prototype of the constructor (if present) but doesn't actually restrict the usage context otherwise. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DebugAgentSymbolsBaseLib: remove exception handlingArd Biesheuvel2019-01-165-662/+0
| | | | | | | | | | | | | | | | | | | | | DebugAgentSymbolsBaseLib is an optional library that is in charge of extracting debug headers from SEC and PEI_CORE images in memory so the filename and the offset in memory can be reported via the UART, allowing a developer to load debugging symbols into his debugger. Interestingly enough, DebugAgentSymbolsBaseLib is also in charge of exception handling before this duty is taken over by either the PEI core, or the CPU DXE driver when running under PrePi. Since exceptions are not actually handled at all on AArch64, and simply routed to the DefaultExceptionHandlerLib (for which a special version has been created to be usable this early), let's get rid of this dubious functionality altogether. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib AARCH64: fix out of bounds accessArd Biesheuvel2019-01-141-1/+1
| | | | | | | | | | Take care not to dereference BlockEntry if it may be pointing past the end of the page table we are manipulating. It is only a read, and thus harmless, but HeapGuard triggers on it so let's fix it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: disregard high memory when setting permissionsArd Biesheuvel2019-01-141-0/+4
| | | | | | | | | | | Ignore calls to ArmSetMemoryAttributes () when the region described is outside of the 32-bit addressable range. This memory is not mapped in the first place, and the current code does not deal with the high bits correctly, resulting in hangs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: fix thinko in second level page table handlingArd Biesheuvel2019-01-131-2/+2
| | | | | | | | | | | | | | | | | PopulateLevel2PageTable () is invoked for [parts of] mappings that start or end on a non-1 MB aligned address (or both). The size of the mapping depends on both the start address modulo 1 MB and the length of the mapping, but the logic that calculates this size is flawed: subtracting 'start address modulo 1 MB' could result in a negative value for the remaining length, which is obviously wrong. So instead, take either RemainLength, or the rest of the 1 MB block, whichever is smaller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmMmuLib ARM: add missing support for non-shareable cached mappingsArd Biesheuvel2019-01-131-0/+13
| | | | | | | | | | | Commit 829633e3a82 ("ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHAREABLE") introduced support for non-shareable cached mappings to the AArch64 version of ArmMmuLib, but the ARM version was left behind, so fix that. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSoftFloatLib: drop build flags specific to GCC46/GCC47Laszlo Ersek2019-01-081-2/+0
| | | | | | | | | | | | | | | | | | | We've removed BaseTools support for GCC44..GCC47. Drop ArmPkg/ArmSoftFloatLib build flags that are specific to any of those gcc versions. (See also commit 01627dba0911, "ArmPkg/ArmSoftfloatLib: restrict -fno-tree-vrp option to GCC46 and GCC47", 2015-12-15). No GCC44..GCC47 references remain under ArmPkg after this patch. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1377 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmPkg/ArmMmuLib: take MAX_ALLOC_ADDRESS into accountArd Biesheuvel2018-12-201-1/+1
| | | | | | | | | | | | | When creating the page tables for the 1:1 mapping, ensure that we don't attempt to map more than what is architecturally permitted when running with 4 KB pages, which is 48 bits of VA. This will be reflected in the value of MAX_ALLOC_ADDRESS once we override it for AArch64, so use that macro instead of MAX_ADDRESS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib ARM: avoid endless loop in RELEASE buildsArd Biesheuvel2018-12-191-0/+2
| | | | | | | | | | | | | Ensure that we prevent the CPU from proceeding after having taken an unhandled exception on a RELEASE build, which does not contain the ASSERT() which ensures this on DEBUG and NOOPT builds. Retain the code following the deadloop so that we can keep going when running in a debugger. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/OpteeLib: Add dummy RPC handlerSumit Garg2018-12-062-7/+30
| | | | | | | | | Add dummy RPC handler for RPCs that are not implemented as control should be returned back to OP-TEE in case any RPC is invoked. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: handle unmapped sections when updating permissionsArd Biesheuvel2018-12-031-2/+6
| | | | | | | | | | | | | The ARM ArmMmuLib code currently does not take into account that setting permissions on a region should take into account that a region may not be mapped yet to begin with. So when updating a section descriptor whose old value is zero, pass in the address explicitly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: take the CPU supported maximum PA space into accountArd Biesheuvel2018-11-293-8/+9
| | | | | | | | | | | | In preparation of dropping PcdPrePiCpuMemorySize entirely, base the maximum size of the identity map on the capabilities of the CPU. Since that may exceed what is architecturally permitted when using 4 KB pages, take MAX_ADDRESS into account as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: add support for reading the max physical address space sizeArd Biesheuvel2018-11-293-0/+33
| | | | | | | | | | | Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: fix StandaloneMmMmuLib subdirectory caseLeif Lindholm2018-11-272-1/+1
| | | | | | | | | While this isn't the only Aarch64 directory in the tree, let's keep from adding more of them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib: Add MMU Library suitable for use in S-EL0.Achin Gupta2018-11-272-0/+221
| | | | | | | | | | | | | | | | | | | | | | | The Standalone MM environment runs in S-EL0 in AArch64 on ARM Standard Platforms. Privileged firmware e.g. ARM Trusted Firmware sets up its architectural context including the initial translation tables for the S-EL1/EL0 translation regime. The MM environment will still request ARM TF to change the memory attributes of memory regions during initialization. The Standalone MM image is a FV that encapsulates the MM foundation and drivers. These are PE-COFF images with data and text segments. To initialise the MM environment, Arm Trusted Firmware has to create translation tables with sane default attributes for the memory occupied by the FV. This library sends SVCs to ARM Trusted Firmware to request memory permissions change for data and text segments. This patch adds a simple MMU library suitable for execution in S-EL0 and requesting memory permissions change operations from Arm Trusted Firmware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmSmcPsciResetSystemLib: add missing call to ExitBootServices()Ard Biesheuvel2018-11-216-6/+187
| | | | | | | | | | | | | | | | | | | | Our poor man's implementation of EnterS3WithImmediateWake () currently sets a high TPL level to disable interrupts, and simply calls the PEI entrypoint again after disabling the MMU. Unfortunately, this is not sufficient: DMA capable devices such as network controllers or USB controllers may still be enabled and writing to memory, e.g., in response to incoming network packets. So instead, do the full ExitBootServices() dance: allocate space and get the memory map, call ExitBootServices(), and in case it fails, get the memory map again and call ExitBootServices() again. This ensures that all cleanup related to DMA capable devices is performed before doing the warm reset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/OpteeLib: Fix compilation issues for ARM (32-bit)Sumit Garg2018-11-051-7/+7
| | | | | | | | | | Correct usage of EFI_PHYSICAL_ADDRESS (always 64-bit) vs. pointers (depending on architecture). Reported-by: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add APIs to communicate with OP-TEESumit Garg2018-10-303-0/+447
| | | | | | | | | | | | | | | Add following APIs to communicate with OP-TEE pseudo/early TAs: 1. OpteeInit 2. OpteeOpenSession 3. OpteeCloseSession 4. OpteeInvokeFunc Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: fix hotkey of boot optionHaojian Zhuang2018-08-231-1/+1
| | | | | | | | | Fix the parameter in EfiBootManagerAddKeyOptionVariable (). Otherwise, the hotkey of boot option won't be registered correctly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg: Add initial OpteeLib implementationSumit Garg2018-08-012-0/+79
| | | | | | | | | | | This is initial version of OP-TEE library that provides api's to communicate with OP-TEE OS (Trusted OS based on ARM TrustZone) via secure monitor calls. Currently it provides basic api to detect OP-TEE presence via UID matching. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBDS: Implement PlatformBootManagerUnableToBootRuiyu Ni2018-07-271-1/+17
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Removing ipf which is no longer supported from edk2.chenc22018-06-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: fix Mva to use idx instead of table baseChris Co2018-06-211-1/+1
| | | | | | | | | | | | | Mva address calculation should use the left-shifted current section index instead of the left-shifted table base address. Using the table base address here has the side-effect of potentially causing an access violation depending on the base address value. Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Christopher Co <christopher.co@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memoryArd Biesheuvel2018-06-212-13/+3
| | | | | | | | | | | | Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contentsArd Biesheuvel2018-06-211-12/+0
| | | | | | | | | | | | | | | | | | | Peculiarly enough, the current page table manipulation code takes it upon itself to write back and invalidate the memory contents covered by page and section mappings when their memory attributes change. It is not generally the case that data must be written back when such a change occurs, even when switching from cacheable to non-cacheable attributes, and in some cases, it is actually causing problems. (The cache maintenance is also performed on the PCIe MMIO regions as they get mapped by the PCI bus driver, and under virtualization, each cache maintenance operation on an emulated MMIO region triggers a round trip to the host and back) So let's just drop this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm rebootArd Biesheuvel2018-06-152-2/+28
| | | | | | | | | | | | | | Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: call ProcessCapsules() only onceArd Biesheuvel2018-06-152-27/+60
| | | | | | | | | | | | | ARM platforms have no restriction on when a system firmware update capsule can be applied, and so it is not necessary to call ProcessCapsules() twice. So let's drop the first invocation that occurs before EndOfDxe, and rewrite the second call so that all capsule updates will be applied when the console is up and able to provide progress feedback. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: fix GCC8 warning for __aeabi_memcpy aliasesMichael Zimmermann2018-06-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | This was the warning (shown for __aeabi_memcpy, __aeabi_memcpy4 and __aeabi_memcpy8): ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c:42:6: error: '__aeabi_memcpy8' alias between functions of incompatible types 'void(void*, const void *, size_t)' {aka 'void(void *, const void *, unsigned int)'} and 'void *(void *, const void *, size_t)' {aka 'void *(void *, const void *, unsigned int)'} [-Werror=attribute-alias] void __aeabi_memcpy8(void *dest, const void *src, size_t n); ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c:19:7: note: aliased declaration here void *__memcpy(void *dest, const void *src, size_t n) The problem is the different return type (void vs void*). So reshuffle the code so the prototypes match between the aliases. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> [ardb: change prototype of internal __memcpy() and drop extra wrapper] Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmDisassemblerLib: fix check for MSR instructionMichael Zimmermann2018-06-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | GCC8 reported it with the following warning: ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c: In function 'DisassembleArmInstruction': ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c:397:30: error: bitwise comparison always evaluates to false [-Werror=tautological-compare] if ((OpCode & 0x0db00000) == 0x03200000) { This condition tries to be true for both the immediate and the register version of the MSR instruction. They get identified inside the if-block using the variable I, which contains the value of bit 25. The problem with the comparison reported by GCC is that the bitmask excludes bit 25, while the value requires it to be set to one: 0x0db00000: 0000 11011 0 11 00 00 0000 000000000000 0x03200000: 0000 00110 0 10 00 00 0000 000000000000 ^ So the solution is to just don't require that bit to be set, because it gets checked later using 'I', which results in the following value: 0x01200000: 0000 00010 0 10 00 00 0000 000000000000 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBootManagerLib: load platform boot optionsHaojian Zhuang2018-06-052-0/+105
| | | | | | | | | | | | | Make platform driver to create predefined boot options and related hot keys. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: add reenable hook to ArmGenericTimerCounterLibArd Biesheuvel2018-04-262-0/+16
| | | | | | | | | | | | | | In preparation of selectively reinstating the timer enable quirk for Xen that we removed in commit 411a373ed642 ("ArmPkg/TimerDxe: remove workaround for KVM timer handling"), add a ArmGenericTimerReenableTimer() library function to ArmGenericTimerCounterLib that we will populate for Xen only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Julien Grall <julien.grall@arm.com> Acked-by: Julien Grall <julien.grall@arm.com>
* ArmPkg: MTL Library interface and Null library implementationGirish Pathak2018-04-232-0/+134
| | | | | | | | | | | | | Upcoming new component ArmPkg/Drivers/ArmScmiDxe is dependent on platform specific ArmMtlLib library implementation, however in order to be able to build the ArmScmiDxe component outside of the context of a particular platform, this change adds Null implementation of the ArmMtlLib along with ARM MTL library header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/TimerDxe: remove workaround for KVM timer handlingArd Biesheuvel2018-04-191-10/+0
| | | | | | | | | | | | | | | | When we first ported EDK2 to KVM/arm, we implemented a workaround for the quirky timer handling on the KVM side. This has been fixed in Linux commit f120cd6533d2 ("KVM: arm/arm64: timer: Allow the timer to control the active state") dated 23 June 2014, which was incorporated into Linux release 4.3. So almost 4 years later, it should be safe to drop this workaround on the EDK2 side. This reverts commit b1a633434ddc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Library/CompilerIntrinsicsLib: Enable VS2017/ARM buildsPete Batard2018-02-077-32/+185
| | | | | | | | | | | | | | | Introduce CRT assembly replacements for __rt_sdiv, __rt_udiv, __rt_udiv64, __rt_sdiv64, __rt_srsh (by reusing the RVCT code) as well as memcpy and memset. For MSFT compatibility, some of the code needs to be explicitly forced to ARM, and the /oldit assembly flag needs to be added. Also, while RVCT_ASM_EXPORT macro invocations have been removed, the replacement code is designed to be as close as possible to the one that would have been generated if using the macros. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Library/ArmLib: add ArmWriteSctlrMichael Zimmermann2018-01-153-0/+16
| | | | | | | | | | This currently isn't needed by anything in the edk2 tree but it's useful for externally maintained platforms which have to set this register e.g. to disable alignment aborts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: fix page size granularity in initial MMU settingMichael Zimmermann2017-12-201-17/+23
| | | | | | | | | | | | | | | | | From what I can see this bug dates back to the commit from 2011 where support for this was added: 2cf4b60895f8a The first problem is that PopulateLevel2PageTable overflows the translation table buffer because it doesn't verify that the size actually fits within one level 2 page table. The second problem is that the loop in FillTranslationTable doesn't care about the PhysicalBase or the RemainLength and always substracts one section size from RemainLength. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBootManagerLib: add missing newlineArd Biesheuvel2017-12-111-1/+1
| | | | | | | | | Add a missing newline to the version string output that is displayed on the serial console, or the next line will be appended to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: print firmware version to consoleArd Biesheuvel2017-12-082-0/+26
| | | | | | | | | | | | If gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString is set to a non-empty string, print it to the console at boot. Note that this is independent of DEBUG/RELEASE or graphical vs serial console, although we do attempt to stay clear of the logo and progress bar in graphical mode, by printing it top center. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmExceptionLib: Add implementation of new APIJian J Wang2017-12-081-0/+33
| | | | | | | | | | | | | | | | | | | | | | | This patch add implementation of following new API introduced into CpuExceptionHandlerLib. Since this lib hasn't support Stack Guard and stack switch, the new method just calls original InitializeCpuExceptionHandlers. EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitDataEx OPTIONAL ); Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-21 20:07:42 +0000