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* ArmPkg/ArmDmaLib: add missing DxeServicesTableLib dependencyArd Biesheuvel2016-10-261-0/+1
| | | | | | | | | This missing dependency has gone unnoticed until now, but it is breaking the Omap35xxPkg.dsc build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: replace AsciiStrCat() with AsciiStrCatS()Laszlo Ersek2016-10-251-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | AsciiStrCat() is deprecated / disabled under the DISABLE_NEW_DEPRECATED_INTERFACES feature test macro. The caller of CpsrString() is required to pass in "ReturnStr" with 32 CHAR8 elements. (DefaultExceptionHandler() complies with this.) "Str" is used to build "ReturnStr" gradually. Just before calling AsciiStrCat(), "Str" points to the then-terminating NUL character in "ReturnStr". The difference (Str - ReturnStr) gives the number of non-NUL characters we've written thus far, hence (32 - (Str - ReturnStr)) yields the number of remaining bytes in ReturnStr, including the ultimately terminating NUL character. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael Zimmermann <sigmaepsilon92@gmail.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=164 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=165 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* ArmPkg/ArmDisassemblerLib: replace AsciiStrCat() with AsciiStrCatS()Laszlo Ersek2016-10-252-23/+19
| | | | | | | | | | | | | | | | | | | | AsciiStrCat() is deprecated / disabled under the DISABLE_NEW_DEPRECATED_INTERFACES feature test macro. The "Str" variable serves no particular purpose in the MRegList() and ThumbMRegList() functions; replace it with the pointed-to "mMregListStr" / "mThumbMregListStr" global variable (as appropriate), so that the new AsciiStrCatS() calls are as clear as possible. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael Zimmermann <sigmaepsilon92@gmail.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=164 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=165 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* ArmPkg: remove BaseMemoryLibStmArd Biesheuvel2016-10-2425-2440/+0
| | | | | | | | | All users have moved to the generic or accelerated versions in MdePkg, so remove the obsolete BaseMemoryLibStm. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Fix typos in commentsGary Lin2016-10-193-4/+4
| | | | | | | | | | | | | - differnt -> different - Libary -> Library - intialized -> initialized Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/LinuxLoader: Reference Shell protocols in MdePkgRuiyu Ni2016-10-191-2/+2
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/CpuDxe: Fix MMU initialization problemKurt Kennett2016-09-261-0/+5
| | | | | | | | | | | | | During Mmu initialization in the CpuDxe, for a page table any bits set in the 'NextSectionAttributes' are garbage and were set from bits that are actually part of the pagetable address. We clear it out to zero so that the SyncCacheConfigPage will use the page attributes instead of trying to convert the (bogus) section attributes into page attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kurt Kennett <kurt.kennett@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/AsmMacroIoLib: force word alignment for functionsArd Biesheuvel2016-09-211-0/+1
| | | | | | | | | Without an explicit .align directive, the Clang assembler defaults to no alignment, which may result in instructions appearing misaligned in the final executable. So use word alignment in all cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: improve formatting of backtraceArd Biesheuvel2016-09-141-19/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the backtrace formattting suggested by Andrew, i.e., IRQ Exception at 0x000000005BE182B0 PC 0x00005BE182B0 (0x00005BE14000+0x000042B0) [ 0] ArmCpuDxe.dll PC 0x00005BE15770 (0x00005BE14000+0x00001770) [ 0] ArmCpuDxe.dll PC 0x00005EF08CC8 (0x00005EEEB000+0x0001DCC8) [ 1] DxeCore.dll PC 0x00005EF09008 (0x00005EEEB000+0x0001E008) [ 1] DxeCore.dll PC 0x00005EEF6ACC (0x00005EEEB000+0x0000BACC) [ 1] DxeCore.dll PC 0x00005EF0963C (0x00005EEEB000+0x0001E63C) [ 1] DxeCore.dll PC 0x00005EF09A38 (0x00005EEEB000+0x0001EA38) [ 1] DxeCore.dll PC 0x00005EF01560 (0x00005EEEB000+0x00016560) [ 1] DxeCore.dll PC 0x00005EF02FB4 (0x00005EEEB000+0x00017FB4) [ 1] DxeCore.dll PC 0x00005EF03098 (0x00005EEEB000+0x00018098) [ 1] DxeCore.dll PC 0x00005EF0460C (0x00005EEEB000+0x0001960C) [ 1] DxeCore.dll PC 0x00005EF005C4 (0x00005EEEB000+0x000155C4) [ 1] DxeCore.dll PC 0x00005EF00360 (0x00005EEEB000+0x00015360) [ 1] DxeCore.dll PC 0x00005EF003C8 (0x00005EEEB000+0x000153C8) [ 1] DxeCore.dll PC 0x00005EF128D0 (0x00005EEEB000+0x000278D0) [ 1] DxeCore.dll PC 0x00005EF12930 (0x00005EEEB000+0x00027930) [ 1] DxeCore.dll PC 0x00005EEEF594 (0x00005EEEB000+0x00004594) [ 1] DxeCore.dll PC 0x00005EF0CF18 (0x00005EEEB000+0x00021F18) [ 1] DxeCore.dll PC 0x00005EF1A310 (0x00005EEEB000+0x0002F310) [ 1] DxeCore.dll PC 0x00005EEF1808 (0x00005EEEB000+0x00006808) [ 1] DxeCore.dll PC 0x00005EEF1E48 (0x00005EEEB000+0x00006E48) [ 1] DxeCore.dll PC 0x00005EF0A838 (0x00005EEEB000+0x0001F838) [ 1] DxeCore.dll PC 0x00005EEED70C (0x00005EEEB000+0x0000270C) [ 1] DxeCore.dll PC 0x00005EEEC93C (0x00005EEEB000+0x0000193C) [ 1] DxeCore.dll PC 0x00005EEEC024 (0x00005EEEB000+0x00001024) [ 1] DxeCore.dll [ 0] /home/ard/build/edk2/Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/AARCH64/ArmPkg/Drivers/CpuDxe/CpuDxe/DEBUG/ArmCpuDxe.dll [ 1] /home/ard/build/edk2/Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/AARCH64/MdeModulePkg/Core/Dxe/DxeMain/DEBUG/DxeCore.dll Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: base page table VA size on GCD memory map sizeArd Biesheuvel2016-09-133-12/+10
| | | | | | | | | | | | | | | | As reported by Eugene, the practice of sizing the address space in the virtual memory system based on the maximum address in the table passed to ArmConfigureMmu() is problematic, since it fails to take into account the fact that the GCD memory space may be extended at a later time, both for memory and for MMIO. So instead, choose the VA size identical to the GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM systems. Reported-by: Eugene Cohen <eugene@hp.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: use a pool allocation for the root tableArd Biesheuvel2016-09-131-5/+22
| | | | | | | | | | | | | | | | | Currently, we allocate a full page for the root translation table, even if the configured translation only requires two entries (16 bytes) for the root level, which happens to be the case for a 40 bit VA. Likewise, for a 36-bit VA space, the root table only needs 16 entries of 8 bytes each, adding up to 128 bytes. So switch to a pool allocation for the root table if we can, but take into account that the architecture requires it to be naturally aligned to its size, i.e., a 64 byte table requires 64 byte alignment, whereas pool allocations in general are only guaranteed to be aligned to 8 bytes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: remove bogus alignment of page allocationsArd Biesheuvel2016-09-131-6/+4
| | | | | | | | | | | | | | | In commit 7d189f99d81c ("ArmPkg/Mmu: Fix bug of aligning new allocated page table"), we fixed a flaw in the logic regarding alignment of newly allocated translation table pages. However, we all failed to spot that aligning page based allocations to page size is rather pointless to begin with, so simply allocate a single page each time we add new pages to the translation tables. Also, drop the unnecessary cast. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: deobfuscate GetRootTranslationTableInfo ()Ard Biesheuvel2016-09-131-31/+4
| | | | | | | | | | | | | | | | The relations between T0SZ, the number of translation levels and the size/alignment of the root table can be expressed in simple arithmetic expressions, so get rid of the lookup table. Note that this disregards the fact that the maximum value of T0SZ is 39 not 42 (as one would expect for the smallest VA size using 2 levels) but since this corresponds to a VA size of 32 MB and 4 MB, respectively, neither of which are sufficient to run UEFI, we can safely ignore the distinction. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicLib: use correct loop variableArd Biesheuvel2016-09-091-1/+1
| | | | | | | | | | | The ArmGicLib API function GicGetCpuRedistributorBase () declares GicCpuRedistributorBase to iterate over the redistributors of all CPUs, but then inadvertently advances GicRedistributorBase instead. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: trim module name in backtrace outputArd Biesheuvel2016-09-091-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Vishal, the new backtrace output would be more useful if it did not contain the full absolute path of each module in the list. So strip off everything up to the last forward slash or backslash in the string. Example output: IRQ Exception at 0x000000005EF110E0 DxeCore.dll loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EF121F0) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EF1289C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFB6B4) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFAA44) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFB450) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF938C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF8D04) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFA8E8) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF3C14) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF3E48) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EF0C838) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEEF70C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEEE93C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEEE024) loaded at 0x000000005EEED000 Suggested-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmBaseLib: clean up directory structureArd Biesheuvel2016-09-0815-12/+12
| | | | | | | | | | | | | | | | | | | | For historical reasons, the files under ArmLib are split up into 'common' files under Common/, containing common C files as well as AArch64 and Arm specific asm files, and ArmV7 and AArch64 files under ArmV7/ and AArch64/, respectively. This presumably dates back to the time when ArmLib supported different revisions of the 32-bit architecture (i.e., pre-V7) Since the PI spec requires V7 or later, we can simplify this to Arm/ and AArch64, which aligns ArmLib with the majority of other modules that carry ARM or AArch64 specific code. So move the files around so that shared files live at the same level as ArmBaseLib.inf, and ARM/AArch64 specific files live in Arm/ or AArch64/, respectively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmBaseLib: remove MemoryAllocationLib.h includesArd Biesheuvel2016-09-082-2/+0
| | | | | | | | | The ArmBaseLib timer code does not depend on MemoryAllocationLib at all, so remove the #includes referring to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: remove all ArmLib flavors except ArmBaseLibArd Biesheuvel2016-09-089-405/+0
| | | | | | | | | | | | | | | | | | | | This removes the following ArmLib implementation, which were, apart from the fact that they targeted either ARM or AARCH64, fully identical: ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf Only ArmBaseLib remains, which can fulfil the dependencies upon each of the listed flavors. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: introduce ArmBaseLibArd Biesheuvel2016-09-082-0/+60
| | | | | | | | | Introduce a new ArmLib version ArmBaseLib, which encapsulates the ARM version ArmV7Lib and the AArch64 version AArch64Lib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: remove NullArmLibArd Biesheuvel2016-09-083-159/+0
| | | | | | | | | Remove the NULL instance of ArmLib: it is not currently used, and its usefulness its dubious. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen2016-09-084-8/+8
| | | | | | | | | | | According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib AARCH64: add minimal backtrace to crash dumpArd Biesheuvel2016-09-071-0/+21
| | | | | | | | | | | | | When dumping the CPU state after an unhandled fault, walk the stack frames and decode the return addresses so we can show a minimal backtrace. Unfortunately, we do not have sufficient information to show the function names, but at least we can see the modules and the return addresses inside the modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: use Clang-compatible 'weak' attributeArd Biesheuvel2016-09-061-6/+3
| | | | | | | | | Clang does not like separate definitions for the __alias__ and the __weak__ attributes, so merge the definitions into one. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib ARM: make memset() weak againArd Biesheuvel2016-09-051-0/+9
| | | | | | | | | | | | | | After the recent update of CompilerIntrinsicsLib, our memset() is no longer emitted as a weak symbol. On ARM, this may cause problems when combining this library with another library that supplies memset() [e.g., CryptoPkg/IntrinsicLib], due to the fact that the object also supplies the __aeabi_memXXX entry points, which can only be satisfied by this object. So make our memset() weak again, to let the other implementation take precedence. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/BaseMemoryLibStm: implement new IsZeroBuffer() API functionArd Biesheuvel2016-09-024-0/+101
| | | | | | | | | | BaseMemoryLib has recently been extended with an API function IsZeroBuffer(), so copy the default implementation into BaseMemoryLibStm as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/BaseMemoryLibStm: implement new IsZeroGuid() API functionArd Biesheuvel2016-09-021-0/+29
| | | | | | | | | | BaseMemoryLib has recently been extended with an API function IsZeroGuid(), so copy the default implementation into BaseMemoryLibStm as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove BaseMemoryLibVstm implementation of BaseMemoryLibArd Biesheuvel2016-09-0122-1960/+0
| | | | | | | | | | The BaseMemoryLibVstm implementation of BaseMemoryLib is ARM only, uses the NEON register file despite the fact that the UEFI spec does not allow it, and is currently not used anywhere. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: replace memcpy and memset with C codeArd Biesheuvel2016-09-0110-395/+103
| | | | | | | | | | | | | | | | | | | | | | This replaces the various implementations of memset and memcpy, including the ARM RTABI ones (__aeabi_mem[set|clr]_[|4|8]) with a single C implementation for each. The ones we have are either not very sophisticated (ARM), or they are too sophisticated (memcpy() on AARCH64, which may perform unaligned accesses) or already coded in C (memset on AArch64). The Tianocore codebase mandates the explicit use of its SetMem() and CopyMem() equivalents, of which various implementations exist for use in different contexts (PEI, DXE). Few compiler generated references to these functions should remain, and so our implementations in this BASE library should be small and usable with the MMU off. So replace them with a simple C implementation that builds correctly on GCC/AARCH64, CLANG/AARCH64, GCC/ARM, CLANG/ARM and RVCT/ARM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/SemihostLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-11/+4
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-1125-113/+56
| | | | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Note that in some cases, various entry points refer to different parts of the same routine, so in those cases, the files have been left untouched. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/BaseMemoryLibVstm: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-11/+6
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/BaseMemoryLibSm: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-9/+6
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSmcLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-10/+5
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-111-3/+1
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-119-424/+205
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmHvcLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-12/+7
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicV3: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-40/+16
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmCpuLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-15/+3
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSmcLibNull: move to generic C implementationArd Biesheuvel2016-08-114-66/+24
| | | | | | | | | | The C language is powerful enough to implement a function that does absolutely nothing, so there is no need to resort to implementations in assembler for various toolchains/architectures. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: introduce ASM_FUNC, MOV32/MOV64 and ADRL/LDRL macrosArd Biesheuvel2016-08-112-1/+42
| | | | | | | | | | | | | | | | This introduces the ASM_FUNC() macro to annotate function entry points in assembler files. This allows us to add additional metadata that marks a function entry point as a function, and allows us to emit a .section directive for each function, which makes it possible for the linker to drop unreferenced code. In addition, introduce a couple of utility macros that we can use to clean up the code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AsmMacroIoLib: remove unused obsolete MMIO and other asm macrosArd Biesheuvel2016-08-112-267/+0
| | | | | | | | | | | | | | This removes the various Mmio ASM macros that are not used anywhere in the code, and removes some variants of LoadConstant... () that are not used anywhere either. Note that these MmioXxx() implementations are unrelated to the C versions defined in MdePkg. These are strictly intended for use in assembler, and no such uses remain. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: add missing ArmMmuLib resolution to ArmPkg.dscArd Biesheuvel2016-08-111-0/+4
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmLib: remove ArmReplaceLiveTranslationEntry() implementationArd Biesheuvel2016-08-112-60/+4
| | | | | | | | | | | | | | | The function ArmReplaceLiveTranslationEntry() has been moved to ArmMmuLib, so remove the old implementation from ArmLib. Note that the new implementation was not exported from the object file, and so references to it were satisfied by the old version residing in ArmLib. Since we are removing that one, we need to export the new one at the same time to prevent the linker from bailing with undefined reference errors. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe: Fix double GIC EIOR write per interruptAlexei Fedorov2016-08-082-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes a bug in the GIC v2 and v3 drivers where the GICC_EOIR (End Of Interrupt Register) is written twice for a single interrupt. GicV(2|3)IrqInterruptHandler() calls the Interrupt Handler and then GicV(2|3)EndOfInterrupt() on exit: InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt]; if (InterruptHandler != NULL) { // Call the registered interrupt handler. InterruptHandler (GicInterrupt, SystemContext); } else { DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); } GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt); although gInterrupt->EndOfInterrupt() can be expected to have already been called by InterruptHandler() [which is the case for the primary in-tree handler in TimerDxe] The fix moves the EndOfInterrupt() call inside the else case for unregistered/spurious interrupts. This removes a potential race condition that might have lost interrupts. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: make the default memset() weakArd Biesheuvel2016-08-051-0/+8
| | | | | | | | | | | | | The ARM compiler intrinsics library defines __aeabi_memset() and memset() in the same object, which means that both will be pulled in if either is referenced. The IntrinsicLib in CryptoPkg defines its own, preferred memset(), which may clash with our memset(). So make our version weak. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSoftFloatLib: disable LTO build for GCCArd Biesheuvel2016-08-051-1/+1
| | | | | | | | | | | | | | | | Building ArmSoftFloatLib with LTO results in errors like .../bin/ld: softfloat.obj: plugin needed to handle lto object .../bin/ld: __aeabi_dcmpge.obj: plugin needed to handle lto object .../bin/ld: __aeabi_dcmplt.obj: plugin needed to handle lto object .../bin/ld: internal error ../../ld/ldlang.c 6299 This library is only linked by OpensslLib at the moment, and only marginally used at runtime, so just disable LTO for it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: add prebuilt glue binaries for GCC5 LTO supportArd Biesheuvel2016-08-024-0/+88
| | | | | | | | | | | | | | | | | | | | | | | GCC in LTO mode interoperates poorly with non-standard libraries that provide implementations of compiler intrinsics such as memcpy/memset or the stack protector entry points. Such libraries need to be built in non-LTO mode, and then referenced explicitly on the linker command line using a -plugin-opt=-pass-through=-lxxx linker option. However, if these intrinsics are also referenced directly, the LTO version of the code will be pulled in, and will happily satisfy all other references to the same symbol. So add a pair of glue libraries, for ARM and AARCH64, that reference the known intrinsics. Since the binaries live under ArmPkg directly, we can reference them in tools_def.txt. Under LD garbage collection, the object itself will be pruned, and so will the intrinsics that end up unused by the module. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Library: Add ArmReadSctlr for AArch64Supreeth Venkatesh2016-08-011-1/+11
| | | | | | | | | | | ArmLib defines a prototype for the ArmReadSctlr() function, but the AArch64 implementation is missing. So add it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: John Powell <john.powell@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> [ardb: update commit log] Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add Cortex-A72 CPU typeJeremy Linton2016-07-281-0/+1
| | | | | | | | Add the Cortex-A72 CPU type which is used in JunoR2. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributorArd Biesheuvel2016-07-131-3/+22
| | | | | | | | | | | | Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon <ndhillonv2@gmail.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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