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* ArmPkg: update InvalidateInstructionCacheRange to flush only to PoUEugene Cohen2015-12-085-2/+25
| | | | | | | | | | | | | | | | | | | | This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to flush the data cache only to the point of unification (PoU). This improves performance and also allows invalidation in scenarios where it would be inappropriate to flush to the point of coherency (like when executing code from L2 configured as cache-as-ram). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Added AARCH64 and ARM/GCC implementations of the above. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Send RemainingDevicePath to PXE Load File protocolHeyi Guo2015-12-071-2/+2
| | | | | | | | | | | | Load File protocol requires remaining device path rather than whole device path. For PXE, it actually requires end node device path only, or else invalid parameter will be returned directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19148 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macroEugene Cohen2015-12-0327-277/+156
| | | | | | | | | | | This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg RVCT: add asm macro combining EXPORT, AREA and label definitionEugene Cohen2015-12-021-0/+29
| | | | | | | | | | | | | | In response to Leif's request earlier, this adds a new RVCT assembler macro to centralize the exporting of assembly functions including the EXPORT directive (so the linker can see it), the AREA directive (so it's in its own section for code size reasons) and the function label itself. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19098 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Convert whole-cache InvalidateInstructionCache to just ASSERTEugene Cohen2015-12-011-1/+1
| | | | | | | | | | | | | | | | | | In SVN 18756 ("disallow whole D-cache maintenance operations") InvalidateInstructionCache was modified to remove the full data cache clean but left the full instruction cache invalidate. The change was made to address issues in the set/way clean methodology but the resulting code could lead someone to a painful debug. If a component called this function, the proper code would not be flushed to the PoU, since the intent of this function is not only to invalidate the I-cache but to provide coherency after code loading / modification. This change simply places an ASSERT(FALSE) in this function to avoid this hazard. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19084 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmSoftFloatLib: add support for RVCTArd Biesheuvel2015-11-3015-17/+1
| | | | | | | | | | | | | | The ARM softfloat library in ArmSoftfloatLib currently does not build under RVCT, simply because the code includes system header files that RVCT does not provide. However, nothing exported by those include files is actually used by the library when built in SOFTFLOAT_FOR_GCC mode, so we can just drop all of them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19031 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: factor out softfloat support from StdLib/LibC/SoftFloatArd Biesheuvel2015-11-3020-0/+4771
| | | | | | | | | | | | In order to support software floating point in the context of DXE drivers etc, this factors out the core ARM softfloat support into a separate library. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19030 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: remove SetPrimaryStack and InitializePrimaryStack macrosArd Biesheuvel2015-11-273-109/+0
| | | | | | | | | | | | The SetPrimaryStack and InitializePrimaryStack macros are no longer used now that we removed support for ArmPlatformGlobalVariableLib. So remove the various versions of them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19004 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: drop bogus gArmGlobalVariableGuid dependencyArd Biesheuvel2015-11-271-1/+0
| | | | | | | | | | | The BdsLib implementation under ArmPkg never references gArmGlobalVariableGuid so it should not list it as a dependency. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18997 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: remove ArmPlatformGlobalVariableLib resolution from ArmPkg.dscArd Biesheuvel2015-11-271-3/+0
| | | | | | | | | | | ArmPkg does not depend on ArmPlatformGlobalVariableLib, and this library is about to be removed, so remove all mention of it from ArmPkg.dsc. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18983 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/PeiServicesTablePointerLib: add missing MigratePeiServicesTablePointer()Eugene Cohen2015-11-251-0/+23
| | | | | | | | | | | | | | | | | As of SVN 15115, the PEI core needs a MigratePeiServicesTablePointer function. Background: The ArmPkg variant of the PeiServicesTablePointerLib implements the standard PEI Services table retrieval mechanism as defined in the PI Specification Volume 1 section 5.4.4 using the TPIDRURW registers. No special action is required on ARM to migrate the PEI Services table pointer after main memory initialization but a function must be implemented nonetheless. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18953 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/UncachedMemoryAllocationLib: fix warning about uninitialized local varEugene Cohen2015-11-251-0/+1
| | | | | | | | | | | RVCT (the proprietary 32-bit ARM compiler) warns about Node potentially being used uninitialized, so initialize it to NULL explicitly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18952 6f19259b-4bc3-4df7-8a09-765794883524
* ArmLib/ArmV7Mmu: use 64-bit type for mapping region sizeArd Biesheuvel2015-11-241-1/+1
| | | | | | | | | | | | | | | | | The way the v7 MMU code is invoked by the Xen port is somewhat of a pathological case, since it describes its physical memory space using a single cacheable region that covers the entire addressable range. When clipping this region to the part that is 1:1 addressable, we end up with a region of exactly 4 GB in size, which just exceeds the range of the UINT32 variable we use in FillTranslationTable() to track our progress while populating the page tables. So promote it to UINT64 instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18930 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Invalidate cache after allocating UC memoryHeyi Guo2015-11-232-0/+4
| | | | | | | | | | | | It is implied that the memory returned from UncachedMemoryAllocationLib should have cache invalidated. So we invalidate memory range after changing memory attribute to uncached. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18920 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () aliasLeif Lindholm2015-11-206-20/+8
| | | | | | | | | | | | | | | | | | In ArmLib, there exists an alias for ArmDataSynchronizationBarrier, named after one of several names for the pre-ARMv6 cp15 operation that was formalised into the Data Synchronization Barrier in ARMv6. This alias is also the one called from within ArmLib, in preference of the correct name. Through the power of code reuse, this name slipped into the AArch64 variant as well. Expunge it from the codebase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18915 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPlatformPkg: position vectors relative to baseMark Rutland2015-11-193-39/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: correct TTBR1_EL1 settings in TCR_EL1Mark Rutland2015-11-192-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since reset. Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU may make page table walks via TTBR1_EL1 at any time, potentially using UNKNOWN values. This can result in a number of potential problems (e.g. the CPU may load from MMIO registers as part of a page table walk). Additionally, in the presence of Cortex-A57 erratum #822227, we must program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a hypervisor which makes use of PAR_EL1. This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any CPU capable of running EDK2 must support this granule, and given TCR_EL1.EPD1, programming the field is not detrimental in the absence of the erratum. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18903 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu: handle memory regions over 4 GB correctlyArd Biesheuvel2015-11-181-2/+9
| | | | | | | | | | | | | The ARM_MEMORY_REGION_DESCRIPTOR array provided by the platform may contain entries that extend beyond the 4 GB boundary, above which we can't map anything on 32-bit ARM. If this is the case, map only the 1:1 addressable part. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18900 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Lib: take MP extensions into account when programming TTBRArd Biesheuvel2015-11-182-7/+12
| | | | | | | | | | | | | Bits 0 and 6 of the TTBRx system registers have different meanings depending on whether a system implements the Multiprocessing Extensions. So use separate memory attribute definitions for MP and non-MP. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18899 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Lib: fix definition of TTBR_NON_INNER_CACHEABLEArd Biesheuvel2015-11-181-1/+1
| | | | | | | | | | | | The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not bit 0 set. Furthermore, the name is inconsistent with the other definitions so rename it to TTBR_INNER_NON_CACHEABLE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18898 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu: introduce feature PCD to map normal memory non-shareableArd Biesheuvel2015-11-184-9/+33
| | | | | | | | | | | | | | | Even though mapping normal memory (inner) shareable is usually the correct choice on coherent systems, it may be desirable in some cases to use non-shareable mappings for normal memory, e.g., when hardware managed coherency is not required and the memory system is not fully configured yet. So introduce a PCD PcdNormalMemoryNonshareableOverride that makes cacheable mappings of normal memory non-shareable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18897 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu: make cached translation table accesses shareableArd Biesheuvel2015-11-182-3/+16
| | | | | | | | | | | To align with the way normal cacheable memory is mapped, set the shareable bit for cached accesses performed by the page table walker. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Lib: add function to test for presence of MP extensionsArd Biesheuvel2015-11-183-0/+20
| | | | | | | | | | | Some MMU manipulation is dependent on the presence of the multiprocessing extensions. So add a function that returns this information. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18895 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Lib: add support for reading the ID_MMFR0 system registerArd Biesheuvel2015-11-183-0/+16
| | | | | | | | | | | | | Implement an accessor function for the ID_MMFR0 system register, which contains information about the VMSA implementation. We will need this to access the number of shareability levels and the nature of their implementations. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18894 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu: fix write-through translation table accessesArd Biesheuvel2015-11-182-2/+2
| | | | | | | | | | | | | | | | The definition TTBR_WRITE_THROUGH_NO_ALLOC makes little sense, since a) its meaning is unclear in the context of TTBRx, since write through always implies Read-Allocate and no Write-Allocate b) its definition equals the definition of TTBR_WRITE_BACK_ALLOC So instead, rename it to TTBR_WRITE_THROUGH and update the definition to reflect the name. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18893 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Mmu: set required XN attributes for device mappingsArd Biesheuvel2015-11-183-2/+7
| | | | | | | | | | | | | | | | | | | To prevent speculative intruction fetches from MMIO ranges that may have side effects on reads, the architecture requires device mappings to be created with the XN or UXN/PXN bits set (for the ARM/EL2 and EL1&0 translation regimes, respectively.) Note that, in the ARM case, this involves moving all accesses to a client domain since permission attributes like XN are ignored from a manager domain. The use of a client domain is actually mandated explicitly by the UEFI spec. Reported-by: Heyi Guo <heyi.guo@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18891 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AArch64Mmu: remove unused GcdAttributeToArmAttribute()Ard Biesheuvel2015-11-182-47/+0
| | | | | | | | | | | | | The function GcdAttributeToArmAttribute() is not used anywhere in the code base, and is only defined for AARCH64 and not for ARM. It also fails to set the bits for shareability and non-executability that we require for correct operation. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18888 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: ensure DebugAgentVectorTable is 2K-alignedMark Rutland2015-11-171-1/+1
| | | | | | | | | | | | | | | | We force alignment to 2K after generating the DebugAgentVectorTable symbol, and hence DebugAgentVectorTable itself may not be 2K-aligned, and table entries may not be at the correct offset from the DebugAgentVectorTable base address. Fix this by forcing alignment before generating the DebugAgentVectorTable symbol. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18865 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: mark all cached mappings as (inner) shareableArd Biesheuvel2015-11-123-15/+19
| | | | | | | | | | | | | | | | | Mark all cached memory mappings as shareable (or inner shareable on AArch64) so that our view of memory is kept coherent by the hardware. This is relevant for things like coherent DMA and virtualization (where a guest may migrate to another core) but in general, since UEFI on ARM is mostly used in a context where the secure firmware and possibly a secure OS are already up and running, it is best to refrain from using any non-shareable mappings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18778 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmDmaLib: use the cache writeback granularity for alignmentArd Biesheuvel2015-11-091-1/+1
| | | | | | | | | | | | | | | | When allocating memory to perform non-coherent DMA, use the cache writeback granule rather than the data cache linesize for alignment. This prevents the explicit cache maintenance from corrupting unrelated adjacent data if the cache writeback granule exceeds the cache linesize. Reported-by: Mark Rutland <mark.rutland@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18759 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: add accessor function for Cache Writeback GranuleArd Biesheuvel2015-11-092-0/+23
| | | | | | | | | | | | | Add a function to ArmLib that provides access to the Cache Writeback Granule (CWG) field in CTR_EL0. This information is required when performing non-coherent DMA. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18758 6f19259b-4bc3-4df7-8a09-765794883524
* ArmCacheMaintenanceLib: disallow whole D-cache maintenance operationsArd Biesheuvel2015-11-091-4/+4
| | | | | | | | | | | | | | | | | The ARM architecture provides no reliable way to clean or invalidate the entire data cache at runtime. The reason is that such maintenance requires the use of set/way maintenance operations, which are suitable only for the kind of maintenance that is carried out when the cache is taken offline entirely. So ASSERT () when any of the CacheMaintenanceLib whole data cache routines are invoked rather than pretending we can do anything meaningful here. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18756 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: move cache maintenance sync barriers out of loopArd Biesheuvel2015-11-094-36/+1
| | | | | | | | | | | | | | | | | | | There is no need to issue a full data synchronization barrier and an instruction synchronization barrier after each and every set/way or MVA cache maintenance operation. For the set/way case, we can simply remove them, since the set/way outer loop already issues the required barriers after completing its traversal over all the cache levels. For the MVA case, move the data synchronization barrier out of the loop, and add the instruction synchronization barrier to the I-cache invalidation by MVA routine. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18755 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: retrieve cache line length from CTR not CCSIDRArd Biesheuvel2015-11-093-52/+18
| | | | | | | | | | | | | | | | | The stride used by the cache maintenance by MVA instructions should be retrieved from CTR_EL0.DminLine and CTR_EL0.IminLine, whose values reflect the actual geometry of the caches. Using CCSIDR for this purpose violates the architecture. Also, move the line length accessors to common code, since there is no need to keep them separate between ARMv7 and AArch64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18754 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: remove CCSIDR based cache info routinesArd Biesheuvel2015-11-096-488/+0
| | | | | | | | | | | | | | The ARM architecture does not allow the actual geometries of the caches to be inferred from the CCSIDR cache info system register, since the geometry it reports is intended for performing cache maintenance by set/way and nothing else. Since the ArmLib cache info routines are based solely on CCSIDR contents, they should not be used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18753 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: remove unused ArmCleanDataCacheToPoU()Ard Biesheuvel2015-11-098-192/+0
| | | | | | | | | | | | | | The function ArmCleanDataCacheToPoU() has no users, and its purpose is unclear, since it uses cache maintenance by set/way to perform the clean to PoU, which is a dubious practice to begin with. So remove the declaration and all definitions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18752 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg BeagleBoardPkg Omap35xxPkg: fix typo 'ArmDataSyncronizationBarrier'Ard Biesheuvel2015-11-094-7/+7
| | | | | | | | | | | | Replace all instances of ArmDataSyncronizationBarrier with ArmDataSynchronizationBarrier. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18751 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: remove unused ARM9 supportArd Biesheuvel2015-11-097-762/+0
| | | | | | | | | | | | The ARM9 ArmLib implementation is not referenced anywhere in the tree, and unlikely to be useful going forward, considering that ARM9 outdates even ARMv6. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18750 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: fix barriers in AArch64 ArmEnableMmuMark Rutland2015-11-091-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | The ARM architecture requires a DSB to complete TLB maintenance, with a subsequent ISB being required to synchronize subsequent items in the current instruction stream against the completed TLB maintenance. The ArmEnableMmu function is currently missing the DSB, and hence the TLB maintenance is not guaranteed to have completed at the point the MMU is enabled. This may result in unpredictable behaviour. The DSB subsequent to the write to SCTLR_EL1 is unnecessary; the ISB alone is sufficient to complete all prior instructions and to synchronise the new context with any subsequent instructions. This patch adds missing DSBs to complete TLB maintenance, and removes the unnecessary trailing DSB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18749 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Increase fallback tftp buffer sizeAshutosh Singh2015-11-091-2/+2
| | | | | | | | | | | | | When performing a tftp download from a server which does not support rfc2349 transfer size option (such as netkit-tftpd), the existing code falls back to allocating an 8MB buffer. Since this is insufficient for an uncompressed AArch64 Linux kernel image, double the size to 16MB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ashutosh Singh <ashutosh.singh@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18748 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Purge unused/unneeded CPU-specific header filesLeif Lindholm2015-11-065-175/+4
| | | | | | | | | | | | | | | | | | In ArmPkg/Include/Chipset, several CPU-specific header files reside. Most of these provide no actual, or very little, use. ARM1176JZ-S.h is not used at all (and unusable since SVN r18237). ArmAemV8.h simply includes AArch64.h. ArmCortexA15.h defines one processor-specific configuration bit and then includes ArmV7.h. Delete these include files, and update their sole users to function without them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18736 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib MMU: add functions to set/clear RO and XN bits on regionsArd Biesheuvel2015-10-083-0/+150
| | | | | | | | | | | | | | Use the refactored UpdateRegionMapping () to traverse the translation tables, splitting block entries along the way if required, and apply a mask + or on each to set or clear the PXN/UXN/XN or RO bits. For now, the 32-bit ARM versions remain unimplemented. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18587 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AArch64Mmu: move page table traversal code to separate functionArd Biesheuvel2015-10-081-19/+31
| | | | | | | | | | | | | | Move the page table traversal and splitting logic to a separate function UpdateRegionMapping() and refactor it slightly so we can reuse it later to implement non-executable regions, for the stack. This primarly involves adding a value/mask pair to the function prototype that allows us to flip arbitrary bits on each block entry as the page tables are traversed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18586 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AArch64Mmu: use architecturally correct definitions for XN/UXNArd Biesheuvel2015-10-082-3/+6
| | | | | | | | | | | | | | | The non-privileged execute never (UXN) page table bit defined for the EL1&0 translation regime and the execute never (XN) bit defined for the EL2 and EL3 translation regimes happen to share the same bit position, but they are in fact defined distinctly by the architecture. So define both bits explicitly, and add comments in places where we take advantage of the fact that they share the same bit position. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18585 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AArch64Mmu: remove cache maintenance for page tablesArd Biesheuvel2015-10-061-6/+0
| | | | | | | | | | | | | | | All our page tables are allocated from memory whose cacheability attributes are inherited by the cacheability bits in the MMU control register, so there is no need for explicit cache maintenance after updating the page tables. And even if there were, Set/Way operations are not appropriate anyway for ensuring that these changes make it to main memory. So just remove the explicit cache maintenance completely. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18570 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Mmu: do not configure block translations at level 0Ard Biesheuvel2015-10-021-2/+3
| | | | | | | | | | | | | | | | | | | | | Now that the AArch64 MMU code correctly identifies and handles naturally aligned regions of more than 2 MB in size, it will happily try to use block mappings at level 0 to map huge memory regions, such as the single cacheable 1:1 mapping we use for Xen domU to map the entire PA space. However, block mappings are not supported at level 0 so the resulting translation tables will be incorrect, causing execution to fail as soon as the MMU is enabled. So use level 1 as the minimum level at which to perform block translations. Reported-by: Julien Grall <julien.grall@citrix.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18568 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Disable interrupt before restoring contextHeyi Guo2015-09-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | Interrupt must be disabled before we storing ELR and other system registers, or else ELR will be overridden by interrupt reentrance. This bug is critical as we may get occasional exception or dead loop when interrupt reentrance occurs: After increasing SP ... Before popping out registers Or After restoring ELR The 1st circumstance could also be resolved by optimizing SP operation (Pop out registers before adding SP back), but the 2nd could not be resolved by disabling interrupt. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18538 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Mmu: Fix potential page table memory leakHeyi Guo2015-09-091-0/+7
| | | | | | | | | | | | | | | | | | | | During page entry attribute update, if there are table entries between starting BlockEntry and LastBlockEntry, table entries will be set as block entries and the allocated memory of the tables will be leaked. So instead, we break the inner loop when we find a table entry and run outer loop again to step into the table by the same logic. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> [ardb: move termination condition check inside the loop] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18425 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Mmu: Increase PageLevel when table found at the targeted levelHeyi Guo2015-09-091-30/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Below code has bug since *BlockEntrySize and *TableLevel are not updated accordingly: if (IndexLevel == PageLevel) { // And get the appropriate BlockEntry at the next level BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, \ IndexLevel + 1, RegionStart); // Set the last block for this new table *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, \ TT_ENTRY_COUNT); } Also it doesn't check recursively to get the last level, e.g. the initial PageLevel is 1 and we already have level 2 and 3 tables at this address. What's more, *LastBlockEntry was not updated when we get a table and IndexLevel != PageLevel. So we reorganize the sequence, only updating TranslationTable, PageLevel and BlockEntry in the loop, and setting the other output parameters with the final PageLevel before returning. And LastBlockEntry is only an OUT parameter. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18424 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Mmu: Fix literal number left shift bugHeyi Guo2015-09-091-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a hidden bug for below code: (1 << BaseAddressAlignment) & *BlockEntrySize From disassembly code, we can see the literal number 1 will be treated as INT32 by compiler by default, and we'll get 0xFFFFFFFF80000000 when BaseAddressAlignment is equal to 31. So we will always get 31 when alignment is larger than 31. if ((1 << BaseAddressAlignment) & *BlockEntrySize) { 5224: f9404be0 ldr x0, [sp,#144] 5228: 2a0003e1 mov w1, w0 522c: 52800020 mov w0, #0x1 // #1 5230: 1ac12000 lsl w0, w0, w1 5234: 93407c01 sxtw x1, w0 The bug can be replayed on QEMU AARCH64; by adding some debug print, we can see lots of level 1 tables created (for block of 1GB) even when the region is large enough to use 512GB block size. Use LowBitSet64() in BaseLib instead to fix the bug. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18423 6f19259b-4bc3-4df7-8a09-765794883524
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