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* edk2: Move TianoCore Contribution Agreement to rootMichael D Kinney2017-08-031-218/+0
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=629 Move Contributions.txt that contains the TianoCore Contribution Agreement 1.0 to the root of the edk2 repository and remove the duplicate Contributions.txt files from all packages. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Move IS_DEVICE_PATH_NODE for sharingJun Nie2017-08-012-3/+3
| | | | | | | | Move IS_DEVICE_PATH_NODE into header to share it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: implement ResetSystemLib using PSCI 0.2 callsArd Biesheuvel2017-07-032-0/+150
| | | | | | | | | | | | | | | This adds an implementation of the ResetSystemLib library class as defined in MdeModulePkg. It is used as the platform glue by the generic ResetSystemRuntimeDxe which lives in the same package. This implementation is intended to replace the EfiResetSystemLib based implementation that is deprecated now that we have decided that there is no longer a reason to keep a different ResetSystem() implementation under EmbeddedPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add CNTHCTL_EL2 support functionsSami Mujawar2017-05-222-1/+21
| | | | | | | | | | Added helper functions for reading and writing the CNTHCTL_EL2 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: copy/paste fixes in ARM ArmHvcLib/ArmSmcLibLeif Lindholm2017-04-132-2/+2
| | | | | | | | | | | | | ARM ArmHvcLib looks like it was created from copy of ArmSmcLib which looks like it was created from a copy of the AArch64 version. Both of these files include AsmMacroIoLibV8.h instead of AsmMacroIoLib.h, although since they only use macros that are identical between the two, there was no functional issue caused by this. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove ArmCpuLib header and implementationsArd Biesheuvel2017-04-0615-592/+0
| | | | | | | | Remove ArmCpuLib entirely. It is no longer used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/ArmExceptionLib: use EL0 stack for synchronous exceptionsArd Biesheuvel2017-03-273-38/+82
| | | | | | | | | | | In order to be able to produce meaningful diagnostic output when taking synchronous exceptions that have been caused by corruption of the stack pointer, prepare the EL0 stack pointer and switch to it when handling the 'Sync exception using SPx' exception class. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: walk call stack unconditionallyArd Biesheuvel2017-03-221-25/+31
| | | | | | | | | | | | Currently, we only attempt to walk the call stack and print a backtrace if the program counter refers to a location covered by a PE/COFF image. However, regardless of the value of PC, the frame pointer may still have a meaningful value, and so we can still produce the remainder of the backtrace. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: add missing GUID to .infArd Biesheuvel2017-03-222-0/+6
| | | | | | | | | Add the gEfiDebugImageInfoTableGuid, which is referenced in the code, to both .INF files describing this module. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: move to BootLogoLib for boot splash supportArd Biesheuvel2017-03-223-689/+28
| | | | | | | | | | Replace the duplicated and outdated code in QuietBoot.c with a reference to BootLogoLib, which provides the same functionality. This also allows us to drop all references to IntelFrameworkModulePkg in this module. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: refer to Shell FILE_GUID directlyArd Biesheuvel2017-03-222-4/+4
| | | | | | | | | | | Instead of indirecting the reference to the Shell binary via a PCD that is defined in IntelFrameworkModulePkg, and which invariably gets set to the same value by all users of this library, refer to the UEFI Shell application by its declared symbolic GUID. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/UncachedMemoryAllocationLib: set XP bit via CPU arch protocolArd Biesheuvel2017-03-152-8/+42
| | | | | | | | | | | | | | | | | | | | | Commit e7b24ec9785d ("ArmPkg/UncachedMemoryAllocationLib: map uncached allocations non-executable") adds code that manipulates the GCD memory space attributes of a newly allocated uncached region without checking whether this region expose these attributes in its capabilities mask. Given that the intent is to remove executable permissions from the region, this is a fairly pointless exercise to begin with, regardless of whether it is correct or not. The reason is that RO/XP memory attributes in the GCD memory space map or the UEFI memory map are completely disconnected from the actual mapping permissions used in the page tables. So instead, invoke the CPU arch protocol directly, and add the non-exec attributes in the page tables directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPkg: Fix modsi3.S compilation across toolchains.Marvin Häuser2017-03-141-1/+1
| | | | | | | | | modsi3.S references the symbol '__divsi3' by '___divsi3' which assumes the prefix is always required and supported. Use ASM_PFX() instead to support all compilers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
* ArmPkg/CpuDxe: handle implied attributes in EfiAttributeToArmAttributeArd Biesheuvel2017-03-081-3/+7
| | | | | | | | | | | | | | | | Some memory attributes are implied by the memory type, e.g., device memory is always mapped non-executable and cached memory should have the inner shareable attribute. In order to prevent unnecessary memory attribute updates of mappings created early on, make EfiAttributeToArmAttribute() return these implied attributes in the same way as ArmMmuLib does already. This avoids false positives when looking for differences between current and desired mapping attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/UncachedMemoryAllocationLib: map uncached allocations non-executableArd Biesheuvel2017-03-081-1/+2
| | | | | | | | | | | | | The primary use case for UncachedMemoryAllocationLib is non-coherent DMA, which implies that such regions are not used to fetch instructions from. So let's map them as non-executable, to avoid creating a security hole when the rest of the platform may be enforcing strict memory permissions on ordinary allocations. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/UncachedMemoryAllocationLib: use CWG value to align pool allocationsArd Biesheuvel2017-03-081-1/+1
| | | | | | | | | | | | | | | Uncached pool allocations are aligned to the data cache line length under the assumption that this is sufficient to prevent cache maintenance from corrupting adjacent allocations. However, the value to use in such cases is architecturally called the Cache Writeback Granule (CWG), which is essentially the maximum Dcache line length rather than the minimum. Note that this is mostly a cosmetical fix, given that the pool allocation is turned into a page allocation later, and rounded up accordingly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/UncachedMemoryAllocationLib: restore mapping attributes after freeArd Biesheuvel2017-03-081-9/+7
| | | | | | | | | | In order to play nice with platforms that use strict memory permission policies, restore the original mapping attributes when freeing uncached allocations. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: implement memory permission control routinesArd Biesheuvel2017-03-071-4/+6
| | | | | | | | | | | | | | | | | Now that we have the prerequisite functionality available in ArmMmuLib, wire it up into ArmSetMemoryRegionNoExec, ArmClearMemoryRegionNoExec, ArmSetMemoryRegionReadOnly and ArmClearMemoryRegionReadOnly. This is used by the non-executable stack feature that is configured by DxeIpl. NOTE: The current implementation will not combine RO and XP attributes, i.e., setting/clearing a region no-exec will unconditionally clear the read-only attribute, and vice versa. Currently, we only use ArmSetMemoryRegionNoExec(), so for now, we should be able to live with this. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: remove VirtualMask arg from ArmSetMemoryAttributesArd Biesheuvel2017-03-074-22/+7
| | | | | | | | | | | | | We no longer make use of the ArmMmuLib 'feature' to create aliased memory ranges with mismatched attributes, and in fact, it was only wired up in the ARM version to begin with. So remove the VirtualMask argument from ArmSetMemoryAttributes()'s prototype, and remove the dead code that referred to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: move ARM version of SetMemoryAttributes to ArmMmuLibArd Biesheuvel2017-03-077-425/+414
| | | | | | | | | | | | | | | ... where it belongs, since AARCH64 already keeps it there, and non DXE users of ArmMmuLib (such as DxeIpl, for the non-executable stack) may need its functionality as well. While at it, rename SetMemoryAttributes to ArmSetMemoryAttributes, and make any functions that are not exported STATIC. Also, replace an explicit gBS->AllocatePages() call [which is DXE specific] with MemoryAllocationLib::AllocatePages(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: use correct return type for exported functionsArd Biesheuvel2017-03-072-34/+35
| | | | | | | | | | | | | | The routines ArmConfigureMmu(), SetMemoryAttributes() [*] and the various set/clear read-only/no-exec routines are declared as returning EFI_STATUS in the respective header files, so align the definitions with that. * SetMemoryAttributes() is declared in the wrong header (and defined in ArmMmuLib for AARCH64 and in CpuDxe for ARM) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe ARM: honour RO/XP attributes in SetMemoryAttributes()Ard Biesheuvel2017-03-071-92/+86
| | | | | | | | | | | | | | Enable the use of strict memory permissions on ARM by processing the EFI_MEMORY_RO and EFI_MEMORY_XP rather than ignoring them. As before, calls to CpuArchProtocol::SetMemoryAttributes that only set RO/XP bits will preserve the cacheability attributes. Permissions attributes are not preserved when setting the memory type only: the way the memory permission attributes are defined does not allows for that, and so this situation does not deviate from other architectures. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe ARM: avoid unnecessary cache/TLB maintenanceArd Biesheuvel2017-03-071-26/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Page and section entries in the page tables are updated using the helper ArmUpdateTranslationTableEntry(), which cleans the page table entry to the PoC, and invalidates the TLB entry covering the page described by the entry being updated. Since we may be updating section entries, we might be leaving stale TLB entries at this point (for all pages in the section except the first one), which will be invalidated wholesale at the end of SetMemoryAttributes(). At that point, all caches are cleaned *and* invalidated as well. This cache maintenance is costly and unnecessary. The TLB maintenance is only necessary if we updated any section entries, since any page by page entries that have been updated will have been invalidated individually by ArmUpdateTranslationTableEntry(). So drop the clean/invalidate of the caches, and only perform the full TLB flush if UpdateSectionEntries() was called, or if sections were split by UpdatePageEntries(). Finally, make the cache maintenance on the remapped regions themselves conditional on whether any memory type attributes were modified. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe ARM: avoid splitting page table sections unnecessarilyArd Biesheuvel2017-03-071-8/+43
| | | | | | | | | | | | | | | | | | Currently, any range passed to CpuArchProtocol::SetMemoryAttributes is fully broken down into page mappings if the start or the size of the region happens to be misaliged relative to the section size of 1 MB. This is going to result in memory being wasted on second level page tables when we enable strict memory permissions, given that we remap the entire RAM space non-executable (modulo the code bits) when the CpuArchProtocol is installed. So refactor the code to iterate over the range in a way that ensures that all naturally aligned section sized subregions are not broken up. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig()Ard Biesheuvel2017-02-283-0/+8
| | | | | | | | | | | | | | | To prevent the initial MMU->GCD memory space map synchronization from stripping permissions attributes [which we cannot use in the GCD memory space map, unfortunately], implement the same approach as x86, and ignore SetMemoryAttributes() calls during the time SyncCacheConfig() is in progress. This is a horrible hack, but is currently the only way we can implement strict permissions on arbitrary memory regions [as opposed to PE/COFF text/data sections only] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove unused PcdArmUncachedMemoryMask PCDArd Biesheuvel2017-02-271-1/+0
| | | | | | | | | | | | This removes the PCD PcdArmUncachedMemoryMask from ArmPkg, along with any remaining references to it in various platform .DSC files. It is no longer used now that we removed the virtual uncached pages protocol and the associated DebugUncachedMemoryAllocationLib library instance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: remove VirtualUncachedPages protocol and implementationArd Biesheuvel2017-02-236-138/+0
| | | | | | | | | | Virtual uncached pages are simply pages that are aliased using mismatched attributes, which is not allowed by the ARM architecture. So remove the protocol and its implementation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove DebugUncachedMemoryAllocationLibArd Biesheuvel2017-02-233-704/+0
| | | | | | | | | | | | | | | | | | | | | The debug implementation of the UncachedMemoryAllocationLib library class relies on the creation of an uncached alias of a memory range, while keeping the original cached mapping, but with read-only attributes to trap inadvertent write accesses. This is not a terribly good idea, given that the ARM architecture does not allow mismatched attributes, and so creating them deliberately is not something we should encourage by doing it in reference code. So remove the library, and replace all references to it with a reference to the non-debug version (unless the platform does not require a resolution for it in the first place, in which case all UncachedMemoryAllocationLib references can be removed altogether). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: AARCH64: enable stack alignment checkingArd Biesheuvel2017-02-221-0/+1
| | | | | | | | | | Enable the hardware stack alignment check, as mandated by the UEFI spec. This ensures that the stack pointer is 16 byte aligned at each instance where it is used as the base address in a load/store operation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managedArd Biesheuvel2017-02-222-0/+46
| | | | | | | | | In preparation of enabling stack alignment checking, which is mandated by the UEFI spec for AARCH64, add the code to manage this bit to ArmLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: AARCH64: set frame pointer in cache maintenance routineArd Biesheuvel2017-02-221-2/+3
| | | | | | | | | Stack and unstack the frame pointer according to the AAPCS in AArch64AllDataCachesOperation (). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissionsArd Biesheuvel2017-02-213-36/+67
| | | | | | | | | | | | | | Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between CpuDxe and ArmMmuLib so we don't have to introduce yet another definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissionsArd Biesheuvel2017-02-211-0/+7
| | | | | | | | | | | Currently, we have not implemented support on 32-bit ARM for managing permission bits in the page tables. Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, let's simply ignore those for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttributeArd Biesheuvel2017-02-212-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The single user of EfiAttributeToArmAttribute () is the protocol method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the return value to compare against the ARM attributes of an existing mapping, to infer whether it is actually necessary to change anything, or whether the requested update is redundant. This saves some cache and TLB maintenance on 32-bit ARM systems that use uncached translation tables. However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with only permission bits set, in which case the implied requested action is to update the permissions of the region without modifying the cacheability attributes. This is currently not possible, because EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments that lack a cacheability bit. So let's simply return TT_ATTR_INDX_MASK (AArch64) or TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the appropriate permission bits). This way, the return value is equally suitable for checking whether the attributes need to be modified, but in a way that accommodates the use without a cacheability bit set. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usageJiewen Yao2017-02-214-12/+13
| | | | | | | | | | | Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, according to UEFI spec, we should use EFI_MEMORY_RO for write protection. The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/GenericWatchdogDxe: Declare MMIO PCDs as UINT64Alexei2017-02-072-8/+8
| | | | | | | | | | | | | | PcdGenericWatchdogControlBase & PcdGenericWatchdogRefreshBase are declared as UINT32 values in ArmPkg.dec, but for platforms with addresses in the memory range above 4GB this causes build error F000: Too large PCD value for datum type [UINT32] of PCD gArmTokenSpaceGuid.PcdGenericWatchdogControlBase Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=361 Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib: Revert "use a pool allocation for the root table"Ard Biesheuvel2017-01-201-23/+6
| | | | | | | | | | | | | | | | | | | This reverts commit d32702d2c2aa23e828363a7f88829b78ce36c3af. Using a pool allocation for the root translation table seemed like a good idea at the time, but as it turns out, such allocations are handled in a way that makes them unsuitable for this purpose: they are backed by HOBs that don't remain in the same place during the various PI phase changes, which means the address programmed into the TTBR register is no longer valid, and may refer to memory that is reported as available to the OS. So switch back to using a page based allocation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: remove indirection layer from timer register accessorsArd Biesheuvel2017-01-2011-589/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | The generic timer support libraries call the actual system register accessor function via a single pair of functions ArmArchTimerReadReg() and ArmArchTimerWriteReg(), which take an enum argument to identify the register, and return output values by pointer reference. Since these functions are never called with a non-immediate argument, we can simply replace each invocation with the underlying system register accessor instead. This is mostly functionally equivalent, with the exception of the bounds check for the enum (which is pointless given the fact that we never pass a variable), the check for the presence of the architected timer (which only makes sense for ARMv7, but is highly unlikely to vary between platforms that are similar enough to run the same firmware image), and a check for enum values that refer to the HYP view of the timer, which we never referred to anywhere in the code in the first place. So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib and ArmGenericTimerVirtCounterLib implementations to call the system register accessors directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPkg: fix compilation error in ArmDmaLibLeif Lindholm2016-12-011-1/+1
| | | | | | | | | | | | | Commit 0a99a65d2c8a ("fix incorrect device address of double buffer") retained an explicit cast on the variable "Buffer" which became incorrect with the other changes, leading to compilation failures with some toolchains. Drop the cast. Contributed-under: TianoCore Contribution Agreement 1.0 Reported-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmDmaLib: add support for fixed host-to-device DMA offsetArd Biesheuvel2016-11-303-2/+27
| | | | | | | | | | | | Some devices, such as the Raspberry Pi3, have a fixed offset between memory addresses as seen by the host and as seen by the other bus masters. So add a new PCD that allows this fixed offset to be recorded, and to be used when returning device addresses from the DmaLib mapping routines. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: clean up abuse of device addressArd Biesheuvel2016-11-301-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | In preparation of adding support to ArmDmalib for DMA bus masters whose view of memory is offset by a constant compared to the CPU's view, clean up some abuse of the device address. The device address is not defined in terms of the CPU's address space, and so it should not be used in CopyMem () or cache maintenance operations that require a valid mapping. This not only applies to the above use case, but also to the DebugUncachedMemoryAllocationLib that unmaps the primary, cached mapping of an allocation, and returns a host address which is an uncached alias offset by a constant. Since we should never access the device address from the CPU, there is no need to record it in the MAPINFO struct. Instead, record the buffer address in case of double buffering, since we do need to copy the contents (in case of a bus master write) and free the buffer (in all cases) when DmaUnmap() is called. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: fix incorrect device address of double bufferArd Biesheuvel2016-11-301-1/+1
| | | | | | | | | | | | | | | | | | | If double buffering is not required in DmaMap(), the returned device address is passed through ConvertToPhysicalAddress () to convert the host address (which in case of DebugUncachedMemoryAllocationLib is not 1:1 mapped) to a physical address, which is what a device would expect to be able to perform DMA. By the same reasoning, a double buffer allocated using DmaAllocateBuffer () should be converted in the same way, considering that the buffer is allocated using UncachedAllocatePages (), to which the above equally applies. So add the missing ConvertToPhysicalAddress () invocation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: use DMA buffer alignment from CPU arch protocolArd Biesheuvel2016-11-302-12/+8
| | | | | | | | | | | | | | | Instead of depending on ArmLib to retrieve the CWG directly, use the DMA buffer alignment exposed by the CPU arch protocol. This removes our dependency on ArmLib, which makes the library a bit more architecture independent. While we're in there, rename gCpu to mCpu to better reflect its local scope, and reflow some lines that we're modifying anyway. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: support page tables in cacheable memory onlyArd Biesheuvel2016-11-301-25/+24
| | | | | | | | | | | | | | | | | Translation table walks are always cache coherent on ARMv8-A, so cache maintenance on page tables is never needed. Since there is a risk of loss of coherency when using mismatched attributes, and given that memory is mapped cacheable except for extraordinary cases (such as non-coherent DMA), restrict the page table walker to performing cacheable accesses to the translation tables. For DEBUG builds, retain some of the logic so that we can double check that the memory holding the root translation table is indeed located in memory that is mapped cacheable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove the LinuxLoader applicationArd Biesheuvel2016-11-2514-2873/+0
| | | | | | | | | | | | | The LinuxLoader application boots Linux in a way that prevents the OS from accessing UEFI runtime services. Since we have better ways now of invoking the kernel (via GRUB, or directly via the kernel's UEFI stub), remove the obsolete LinuxLoader so that people will no longer mistake it for a suitable reference of how to invoke the OS from UEFI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPkg/Library/ArmDmaLib: Deallocate Map buffer in case of errorDaniil Egranov2016-11-151-5/+11
| | | | | | | | | | | | | The patch is fixing memory leak in case of errors. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov@arm.com> Tested-by; Ryan Harkin <ryan.harkin@linaro.org> Style fixes: use goto for error handling, whitespace fixes Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/CpuDxe: set DmaBufferAlignment according to CWGArd Biesheuvel2016-11-021-1/+12
| | | | | | | | | | The DmaBufferAlignment currently defaults to 4, which is dangerously small and may result in lost data on platforms that perform non-coherent DMA. So instead, take the CWG value from the cache info registers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove LoadConstantXxx() asm macrosArd Biesheuvel2016-10-283-73/+0
| | | | | | | | This is ancient cruft that is no longer used, so remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg RVCT: add ADRL/LDRL macro equivalentsArd Biesheuvel2016-10-281-0/+20
| | | | | | | | | | | | | | | The GCC ARM builds have access to ADRL/LDRL macros that emit relative symbol references, i.e., references that do not require fixing up at load time (or FV generation time for XIP modules) Implement equivalent functionality for RVCT: note that this does not use movw/movt pairs, but the more compatible add/add/add or add/add/ldr sequences (which Clang does not support, unfortunately, hence the use of movw/movt for the GCC toolchain family) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: enable -DDISABLE_NEW_DEPRECATED_INTERFACESArd Biesheuvel2016-10-281-0/+2
| | | | | | | | | | | | | Define DISABLE_NEW_DEPRECATED_INTERFACES on the compiler command line by default, to prevent deprecated interfaces from being used in core EDK2 code. Bug: https://bugzilla.tianocore.org/show_bug.cgi?id=164 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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