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* ArmPkg/ArmArchTimerLib: correct typosEvan Lloyd2016-04-011-8/+8
| | | | | | | | | | | Some minor typographical problems were noticed during previous commits. This change corrects those, and contains no functional modifications. The changes are in comments, and one diagnostic message. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmArchTimerLib: fix unused variable in RELEASE buildsSami Mujawar2016-04-011-3/+2
| | | | | | | | | | | | | | | | The TimerFreq variable in the TimerConstructor() is unused in RELEASE builds since ASSERTs are then disabled. The only use of the variable (in the ASSERT) is replaced by a direct invocation of the function previously used to set it. NOTE: The build tools suppress warnings of this using compiler options eg. -Wno-unused-but-set-variable for GCC toolchain or --diag_suppress=550 for RVCT toolchain. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmArchTimerLib: add GetTimeInNanoSecond() to ArmArchTimerLibSami Mujawar2016-04-011-1/+50
| | | | | | | | | | FirmwarePerformanceDxe.c utilizes the Timer Library function GetTimeInNanoSecond() which was not implemented by the ArmArchTimerLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArchArmTimerLib: refactor MultU64xN and TimerFreq definitionsSami Mujawar2016-04-011-18/+31
| | | | | | | | | | | | | | This refactors some timer code to define MultU64xN as a preprocessor symbol rather than a function pointer, and to factor out the code that obtains the timer frequency into GetPlatformTimerFreq (). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 [ard.biesheuvel: split off from 'add GetTimeInNanoSecond() to ArmArchTimerLib'] Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg|EmbeddedPkg: make PcdCpuVectorBaseAddress 64 bits wideLeendert van Doorn2016-03-252-4/+4
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: apply Cortex-A57 errataLeendert van Doorn2016-03-251-3/+6
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/AArch64Mmu: use correct AP[] bits in ArmClearMemoryRegionReadOnlyArd Biesheuvel2016-03-221-1/+1
| | | | | | | | | | | | | The function ArmClearMemoryRegionReadOnly() was supposed to undo the effect of ArmSetMemoryRegionReadOnly(), but instead, it sets the permissions to EL0-no access, EL1-read-only. Since the EL0 bit should be 1 to align with EL2/3 (where the bit is SBO), use TT_AP_RW_RW instead, which makes the entry read-write for EL0 when executing at EL1, and read-write for all other levels. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmExceptionLib: reimplement register stack/unstack routinesArd Biesheuvel2016-03-221-126/+109
| | | | | | | | | | | | | | | | This replaces the somewhat opaque preprocessor based stack/unstack macros with open coded ldp/stp sequences to preserve the interrupted context before handing over to the exception handler in C. This removes various arithmetic operations on the stack pointer, and reduces the exception return critical section to its minimum size (i.e., the bare minimum required to populate the ELR and SPSR registers and invoke the eret). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: avoid indirect call if using vector table in placeArd Biesheuvel2016-03-221-0/+4
| | | | | | | | | | | If we are using the vector table in place, there is no need to make an indirect call to the common handler routine from the vector table entries, so just use a straight branch instruction in that case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: make build time define visible to the compilerArd Biesheuvel2016-03-221-2/+4
| | | | | | | | | | | | | | The global gArmRelocateVectorTable is a build time constant, but due to its external linkage and lack of constness, the compiler does not see that. So turn it into a static boolean, and at the same time, make the function CopyExceptionHandlers() (which is only called if gArmRelocateVectorTable is set) static as well, so that the compiler can eliminate it completely if we are using the vector table in place. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: don't restore ESR and FAR upon exception returnArd Biesheuvel2016-03-221-6/+0
| | | | | | | | | | | ESR and FAR are populated by the hardware upon exception entry, and describe the exception, not the interrupted context. So there is no point in restoring their values before returning from the exception. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: stack FPSR on common pathArd Biesheuvel2016-03-221-8/+6
| | | | | | | | | | | We have three code paths to stack/unstack the exception context, one for each of EL3, EL2 and EL1. However, they all access the same copy of FPSR so move that access to the common path. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: fold exception handler prologue into vector tableArd Biesheuvel2016-03-221-73/+39
| | | | | | | | | | | | | | | | Unlike the AArch32 vector table, which has room for a single instruction for each exception type, the AArch64 exception table has 128 byte slots, which can easily hold the shared prologues that are emitted out of line. So refactor this code into a single macro, and expand it into each vector table slot. Since the address of the command handler entry point is no longer patched in by the C code, we can just emit the literal into each vector entry directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/AsmMacroIoLibV8: remove undocumented assumption from ELx macrosArd Biesheuvel2016-03-221-8/+8
| | | | | | | | | | | | | | | The macros EL1_OR_EL2() and EL1_OR_EL2_OR_EL3() allow conditional execution of assembly sequences based on the current exception level, by jumping to caller supplied labels 1f, 2f or 3f. However, the jump to 1f is actually a fallthrough, which means the EL1 code needs to follow right after the macro invocation, and the 1f label is ignored. So let's fix this by making all jumps explicit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg: update CpuDxe to use CpuExceptionHandlerLibCohen, Eugene2016-03-177-1402/+98
| | | | | | | | | | Use the new ARM/AArch64 implementation of the base CpuExceptionHandlerLib library from CpuDxe to centralize exception handling. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: ARM/AArch64 implementation of CpuExceptionHandlerLibCohen, Eugene2016-03-169-0/+1577
| | | | | | | | | | | | | | | | | | | | | | | Introduce ARM and AArch64 instances of the CpuExceptionHandlerLib which provides exception handling and registration of handlers regardless of execution phase. Two variants of the ArmExceptionLib are provided: one where exception handlers reside within the module (meeting appropriate architectural alignment requirements for the vector table) and another one that will relocate a copy of thee xception handlers to an address specified by PcdCpuVectorBaseAddress. The ArmRelocateExceptionLib is intended for use in cases where ArmExceptionLib is too large for the application (uncompressed XIP images) as driven by the vector table alignment padding. The AArch64 build of this library supports execution at EL1, EL2, and EL3 exception levels. Tested on ARM, and AArch64 with SEC, DXE Core, and CpuDxe modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCRCohen, Eugene2016-03-162-0/+11
| | | | | | | | | Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Configure TTBCR registerEvan Lloyd2016-03-034-4/+32
| | | | | | | | | | | | | Architecturally, the TTBCR register value is undefined at reset for Non-Secure. On some platforms the reset value for TTBCR is not zero and this causes a data abort exception once the MMU is enabled. This patch configures the TTBCR register to enable translation table walk using TTBR0. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
* ArmPkg: CpuDxe: don't track interrupt state in a global variableCohen, Eugene2016-02-231-5/+1
| | | | | | | | | | | Update the CpuDxe driver to remove an assumption that it is the only component modifying interrupt state since this can be done through BaseLib as well. Instead of using a global variable for last interrupt state we now check the current PSTATE value directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: CpuDxe: fix AArch64 interrupt read masksCohen, Eugene2016-02-232-25/+23
| | | | | | | | | | | | | | The AArch64 DAIF bits are different for reading (mrs) versus writing (msr). The bitmask definitions assumed they were the same causing incorrect results when trying to determine the current interrupt state through ArmGetInterruptState. The logic for interpreting the DAIF read data using the csel instruction was also incorrect and is fixed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: DefaultExceptionHandler fixes for use with DxeCoreCohen, Eugene2016-02-154-38/+12
| | | | | | | | | | | Modify the DefaultExceptionHandler (uefi-variant) so it can be used by DxeCore (via CpuExceptionHandlerLib) where the debug info table is not yet published at library constructor time. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add isb when setting SCREvan Lloyd2016-02-033-0/+3
| | | | | | | | | | | | Some updates to SCR can cause a problem which manifests as an undefined opcode exception. This may be when a speculative secure instruction fetch happens after the NS bit is set. An isb is required to make the register change take effect fully. Contributed-under: Tianocore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com> Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Rectify file modesEvan Lloyd2016-01-3056-0/+0
| | | | | | | | | | | | | | | Problems have been encountered because some of the source files have execute permission set. This can cause git to report them as changed when they are checked out onto a file system with inherited permissions. This has been seen using Cygwin, MinGW and PowerShell Git. This patch makes no change to source file content, and only aims to correct the file modes/permissions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19778 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: LinuxLoader: fix typo in help stringRyan Harkin2016-01-201-2/+2
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19698 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmSoftfloatLib: add missing entry points for RVCTArd Biesheuvel2015-12-174-1/+94
| | | | | | | | | | | | | | | | | | | | The RVCT compiler may emit calls to the various __aeabi_c?cmp?? functions, which return their results via the CPU condition flags C and Z. According to ARM doc IHI 0043D 'Run-time ABI for the ARM architecture': The 3-way comparison functions c*cmple, c*cmpeq and c*rcmple return their results in the CPSR Z and C flags. C is clear only if the operands are ordered and the first operand is less than the second. Z is set only when the operands are ordered and equal. Add implementations for the double and float variants of the above. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19327 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: rewrite vector table population macrosArd Biesheuvel2015-12-161-2/+5
| | | | | | | | | | | | | | | | | | | | | Unfortunately, Clang does not support the use of symbol references in .org directives, and bails with the following error message when it encounters them: <...>:error: expected assembly-time absolute expression .org DebugAgentVectorTable + 0x000 So replace the .org arguments with absolute values, and move the whole vector table into a subsection with the appropriate alignment, and starting at .org 0x0. This gives the same protection with respect to entries that exceed 128 bytes, in a way that Clang supports as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19303 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu: prefer non shareable memory on non-coherent hardwareArd Biesheuvel2015-12-152-3/+53
| | | | | | | | | | | | | | Commit SVN r18778 made all mappings of normal memory (inner) shareable, even on hardware that implements shareability as uncached accesses. The original concerns that prompted the change, regarding coherent DMA and virt guests migrating between CPUs, do not apply to such hardware, so revert to the original behavior in that case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19285 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmSoftfloatLib: restrict -fno-tree-vrp option to GCC46 and GCC47Ard Biesheuvel2015-12-151-1/+3
| | | | | | | | | | | | The -fno-tree-vrp option is not required for GCC 4.8 or later, and is not supported by CLANG. So restrict its use to GCC 4.6 and 4.7, which are the oldest versions we support for ARM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19283 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Lib: add CLANG alternative for FPEXC accessArd Biesheuvel2015-12-151-0/+4
| | | | | | | | | | | | | The open coded access to co-processor #10 to set FPEXC is not supported by the CLANG assembler, but the architecturally correct VMSR instruction is not supported by older binutils. So keep the former unless __clang__ is defined. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19282 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CompilerIntrinsicsLib: add GCC version of __aeabi_memset()Ard Biesheuvel2015-12-151-2/+17
| | | | | | | | | | | CLANG for ARM may emit calls to __aeabi_memset(), which is subtly different from the default memset() [arguments 2 and 3 are reversed] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19281 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: use unified asm syntax for CLANGArd Biesheuvel2015-12-159-21/+30
| | | | | | | | | | | | | | | The CLANG assembler does not support the legacy, non-unified assembler syntax, i.e., it does not support the reordering of the condition suffixes with the increment/decrement before/after or byte/word suffixes, and it does not recognize the 'empty descending' (ED) suffix at all. So move to the unified syntax, and replace 'empty descending' with 'decrement after' or 'increment before' as appropriate. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19280 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: fix bug in GICv3 distributor configurationArd Biesheuvel2015-12-151-2/+2
| | | | | | | | | | | | | | In the function ArmGicEnableDistributor (), the Affinity Routing Enable (ARE) bit, which essentially defines whether the GIC runs in v2 or v3 mode, is inadvertently cleared when enabling the GIC distributor if it is running in v3 mode. So fix that. Reported-by: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19274 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: drop ARMv4 exception handling codeArd Biesheuvel2015-12-157-357/+4
| | | | | | | | | | | | Since we do not support anything below ARMv7, let's promote the ARMv6 exception handling code in CpuDxe to the only version we provide for ARM. This means we can drop the unused ARMv4 version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19273 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Convert all .uni files to utf-8Jordan Justen2015-12-151-0/+0
| | | | | | | | | | | | | To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py ArmPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19248 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: update InvalidateInstructionCacheRange to flush only to PoUEugene Cohen2015-12-085-2/+25
| | | | | | | | | | | | | | | | | | | | This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to flush the data cache only to the point of unification (PoU). This improves performance and also allows invalidation in scenarios where it would be inappropriate to flush to the point of coherency (like when executing code from L2 configured as cache-as-ram). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Added AARCH64 and ARM/GCC implementations of the above. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Send RemainingDevicePath to PXE Load File protocolHeyi Guo2015-12-071-2/+2
| | | | | | | | | | | | Load File protocol requires remaining device path rather than whole device path. For PXE, it actually requires end node device path only, or else invalid parameter will be returned directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19148 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macroEugene Cohen2015-12-0327-277/+156
| | | | | | | | | | | This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg RVCT: add asm macro combining EXPORT, AREA and label definitionEugene Cohen2015-12-021-0/+29
| | | | | | | | | | | | | | In response to Leif's request earlier, this adds a new RVCT assembler macro to centralize the exporting of assembly functions including the EXPORT directive (so the linker can see it), the AREA directive (so it's in its own section for code size reasons) and the function label itself. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19098 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Convert whole-cache InvalidateInstructionCache to just ASSERTEugene Cohen2015-12-011-1/+1
| | | | | | | | | | | | | | | | | | In SVN 18756 ("disallow whole D-cache maintenance operations") InvalidateInstructionCache was modified to remove the full data cache clean but left the full instruction cache invalidate. The change was made to address issues in the set/way clean methodology but the resulting code could lead someone to a painful debug. If a component called this function, the proper code would not be flushed to the PoU, since the intent of this function is not only to invalidate the I-cache but to provide coherency after code loading / modification. This change simply places an ASSERT(FALSE) in this function to avoid this hazard. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19084 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmSoftFloatLib: add support for RVCTArd Biesheuvel2015-11-3015-17/+1
| | | | | | | | | | | | | | The ARM softfloat library in ArmSoftfloatLib currently does not build under RVCT, simply because the code includes system header files that RVCT does not provide. However, nothing exported by those include files is actually used by the library when built in SOFTFLOAT_FOR_GCC mode, so we can just drop all of them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19031 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: factor out softfloat support from StdLib/LibC/SoftFloatArd Biesheuvel2015-11-3020-0/+4771
| | | | | | | | | | | | In order to support software floating point in the context of DXE drivers etc, this factors out the core ARM softfloat support into a separate library. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19030 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: remove SetPrimaryStack and InitializePrimaryStack macrosArd Biesheuvel2015-11-273-109/+0
| | | | | | | | | | | | The SetPrimaryStack and InitializePrimaryStack macros are no longer used now that we removed support for ArmPlatformGlobalVariableLib. So remove the various versions of them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19004 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: drop bogus gArmGlobalVariableGuid dependencyArd Biesheuvel2015-11-271-1/+0
| | | | | | | | | | | The BdsLib implementation under ArmPkg never references gArmGlobalVariableGuid so it should not list it as a dependency. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18997 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: remove ArmPlatformGlobalVariableLib resolution from ArmPkg.dscArd Biesheuvel2015-11-271-3/+0
| | | | | | | | | | | ArmPkg does not depend on ArmPlatformGlobalVariableLib, and this library is about to be removed, so remove all mention of it from ArmPkg.dsc. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18983 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/PeiServicesTablePointerLib: add missing MigratePeiServicesTablePointer()Eugene Cohen2015-11-251-0/+23
| | | | | | | | | | | | | | | | | As of SVN 15115, the PEI core needs a MigratePeiServicesTablePointer function. Background: The ArmPkg variant of the PeiServicesTablePointerLib implements the standard PEI Services table retrieval mechanism as defined in the PI Specification Volume 1 section 5.4.4 using the TPIDRURW registers. No special action is required on ARM to migrate the PEI Services table pointer after main memory initialization but a function must be implemented nonetheless. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18953 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/UncachedMemoryAllocationLib: fix warning about uninitialized local varEugene Cohen2015-11-251-0/+1
| | | | | | | | | | | RVCT (the proprietary 32-bit ARM compiler) warns about Node potentially being used uninitialized, so initialize it to NULL explicitly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18952 6f19259b-4bc3-4df7-8a09-765794883524
* ArmLib/ArmV7Mmu: use 64-bit type for mapping region sizeArd Biesheuvel2015-11-241-1/+1
| | | | | | | | | | | | | | | | | The way the v7 MMU code is invoked by the Xen port is somewhat of a pathological case, since it describes its physical memory space using a single cacheable region that covers the entire addressable range. When clipping this region to the part that is 1:1 addressable, we end up with a region of exactly 4 GB in size, which just exceeds the range of the UINT32 variable we use in FillTranslationTable() to track our progress while populating the page tables. So promote it to UINT64 instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18930 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Invalidate cache after allocating UC memoryHeyi Guo2015-11-232-0/+4
| | | | | | | | | | | | It is implied that the memory returned from UncachedMemoryAllocationLib should have cache invalidated. So we invalidate memory range after changing memory attribute to uncached. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18920 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () aliasLeif Lindholm2015-11-206-20/+8
| | | | | | | | | | | | | | | | | | In ArmLib, there exists an alias for ArmDataSynchronizationBarrier, named after one of several names for the pre-ARMv6 cp15 operation that was formalised into the Data Synchronization Barrier in ARMv6. This alias is also the one called from within ArmLib, in preference of the correct name. Through the power of code reuse, this name slipped into the AArch64 variant as well. Expunge it from the codebase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18915 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPlatformPkg: position vectors relative to baseMark Rutland2015-11-193-39/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
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