summaryrefslogtreecommitdiffstats
path: root/ArmPkg
Commit message (Collapse)AuthorAgeFilesLines
...
* ArmPkg/CpuDxe: Implement EFI memory attributes protocolArd Biesheuvel2023-03-164-0/+326
| | | | | | | | Expose the protocol introduced in v2.10 that permits the caller to manage mapping permissions in the page tables. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/CpuDxe: Expose unified region-to-EFI attribute conversionArd Biesheuvel2023-03-163-0/+69
| | | | | | | | | | In preparation for introducing an implementation of the EFI memory attributes protocol that is shared between ARM and AArch64, unify the existing code that converts a page table descriptor into a EFI_MEMORY_xx bitfield, so it can be called from the generic code. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Avoid splitting block entries if possibleArd Biesheuvel2023-03-162-0/+21
| | | | | | | | | | | | | | | | | Currently, the ARM MMU page table logic will break down any block entry that overlaps with the region being mapped, even if the block entry in question is using the same attributes as the new region. This means that creating a non-executable mapping inside a region that is already mapped non-executable at a coarser granularity may trigger a call to AllocatePages (), which may recurse back into the page table code to update the attributes on the newly allocated page tables. Let's avoid this, by preserving the block entry if it already covers the region being mapped with the correct attributes. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Implement EFI_MEMORY_RP using access flagArd Biesheuvel2023-03-164-4/+144
| | | | | | | | | | | Implement support for read-protected memory by wiring it up to the access flag in the page table descriptor. The resulting mapping is implicitly non-writable and non-executable as well, but this is good enough for implementing this attribute, as we never rely on write or execute permissions without read permissions. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Clear individual permission bitsArd Biesheuvel2023-03-161-13/+81
| | | | | | | | | | | | | | | | | Currently, the MMU code that is supposed to clear the RO or XP attributes from a region just clears both unconditionally. This approximates the desired behavior to some extent, but it does mean that setting the RO bit first on a code region, and then clearing the XP bit results both RO and XP being cleared, and we end up with writable code, and avoiding that is the point of all these protections. Once we introduce RP support, this will only get worse, so let's fix this up, by reshuffling the attribute update code to take the entry mask from the caller, and use the mask to preserve other attributes when clearing RO or XP. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Isolate the access flag from AP maskArd Biesheuvel2023-03-165-40/+64
| | | | | | | | | | | Split the ARM permission fields in the short descriptors into an access flag and AP[2:1] as per the recommendation in the ARM ARM. This makes the access flag available separately, which allows us to implement EFI_MEMORY_RP memory analogous to how it will be implemented for AArch64. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/CpuDxe ARM: Fix page-to-section attribute conversionArd Biesheuvel2023-03-162-0/+5
| | | | | | | | | | | | | | | | The section-to-page attribute conversion takes the shareability and execute-never attributes into account, whereas the page-to-section counterpart does not. The result is that GetMemoryRegionPage () -which takes a section attribute argument (via *RegionAttributes) that is ostensibly based on the first page in the range, but differs from the actual page attributes when converted back- may return with a RegionLength of zero. This is incorrect, and confuses code that scans a region by calling GetMemoryRegion () in sequence. So fix the conversion, and ASSERT () on a non-zero region length. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Split off XN page descriptor bit from type fieldArd Biesheuvel2023-03-162-11/+9
| | | | | | | | | | | With large page support out of the picture, we can treat bits 1 and 0 of the page descriptor as individual valid and XN bits, instead of treating XN as a page type. Doing so aligns the handling of the attribute with the section descriptor layout, as well as the XN handling on AArch64, and this is beneficial for maintainability. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Remove half baked large page supportArd Biesheuvel2023-03-165-39/+20
| | | | | | | | | | | | | | | | | | Large page support on 32-bit ARM is essentially a glorified contiguous bit where 16 consecutive entries describing a contiguous range with the same attributes are presented in a way that permits the TLB to cache its translation with a single entry. This was never wired up completely, and does not add a lot of value in EFI, where the page granularity is 4k and we expect to be able to set RO and XP permissions on individual pages. Given that large page support complicates the handling of the XN bit at the page level (which is in a different place depending on whether the page is small or large), let's just rip it out. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/SemihostFs: replace SetMem with ZeroMemGerd Hoffmann2023-03-091-1/+1
| | | | | | | | | | | | | SetMem arguments 2+3 are in the wrong order, resulting in the call having no effect because Length is zero. Fix this by using ZeroMem instead. Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4205 Reported-by: Jeremy Boone <jeremy.boone@nccgroup.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg/ArmScmiDxe: Fix the calculation of RequiredArraySizeSudeep Holla2023-02-061-23/+16
| | | | | | | | | | | | | | | | | | | | | | As per the SCMI specification, section CLOCK_DESCRIBE_RATES mentions that the value of num_rates_flags[11:0] in the response must be 3 if the return format is the triplet. Due to the buggy firmware, this was not noticed for long time. The firmware is now fixed resulting in ClockDescribeRates() to fail with "Buffer Too Small" error as the RequiredArraySize gets miscalculated as 72 instead of 24. Fix the issue by reusing the logic for both the return format which must work if num_rates_flags has correct value as expected from the specification. Cc: Girish Pathak <girish.pathak@arm.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Tested-by: Pierre Gondois <pierre.gondois@arm.com> Reported-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Remove RealView Debugger supportRebecca Cran2023-01-304-188/+0
| | | | | | | | | | | | The RealView Debugger is related to RVCT, which is no longer supported. Given that, remove RvdPeCoffExtraActionLib and code from RvdPeCoffExtraActionLib which prints lines for use with the RealView Debugger. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Bob Feng <bob.c.feng@intel.com>
* ArmPkg: implement EFI_MP_SERVICES_PROTOCOL based on PSCI callsRebecca Cran2023-01-275-0/+2335
| | | | | | | | | | | | | | Add support for EFI_MP_SERVICES_PROTOCOL during the DXE phase under AArch64. PSCI_CPU_ON is called to power on the core, the supplied procedure is executed and PSCI_CPU_OFF is called to power off the core. Fixes contributed by Ard Biesheuvel. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
* ArmPkg: Add GET_MPIDR_AFFINITY_BITS and MPIDR_MT_BIT to ArmLib.hRebecca Cran2023-01-271-7/+9
| | | | | Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/ArmTrngLib: Remove ASSERTs in ArmTrngLibConstructor()Pierre Gondois2022-11-261-5/+0
| | | | | | | | Remove ASSERTs in ArmTrngLibConstructor() that prevent from booting on DEBUG builds. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/ArmTrngLib: Remove ASSERT in GetArmTrngVersion()Pierre Gondois2022-11-161-1/+0
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4150 GetArmTrngVersion() is used to check the presence of an Arm Trng. If not found, an ASSERT prevents from booting in DEBUG builds. Remove this ASSERT. Reported-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg/ArmTrngLib: Fix incorrect GUID reference in DEBUG() outputArd Biesheuvel2022-11-111-1/+1
| | | | | | | | | ArmTrngLib crashes when run in DEBUG mode due to the fact that it passed the [truncated] GUID value to a DEBUG() print statement instead of a pointer to the GUID which is what the %g conversion expects. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg/ArmTrngLib: Add Arm TRNG librarySami Mujawar2022-11-064-0/+468
| | | | | | | | | | | | | | | | | | | | Bugzilla: 3668 (https://bugzilla.tianocore.org/show_bug.cgi?id=3668) The Arm True Random Number Generator Firmware, Interface 1.0, Platform Design Document (https://developer.arm.com/documentation/den0098/latest/) defines an interface between an Operating System (OS) executing at EL1 and Firmware (FW) exposing a conditioned entropy source that is provided by a TRNG back end. The conditioned entropy, that is provided by the Arm TRNG interface, is commonly used to seed deterministic random number generators. This patch adds an ArmTrngLib library that implements the Arm TRNG interface. Acked-by: Leif Lindholm <quic_llindhol@quicinc.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* ArmPkg: Add FID definitions for Arm TRNGSami Mujawar2022-11-061-2/+107
| | | | | | | | | | | | | | | | | | Bugzilla: 3668 (https://bugzilla.tianocore.org/show_bug.cgi?id=3668) The Arm True Random Number Generator Firmware, Interface 1.0, Platform Design Document (https://developer.arm.com/documentation/den0098/latest/) defines an interface between an Operating System (OS) executing at EL1 and Firmware (FW) exposing a conditioned entropy source that is provided by a TRNG back end. New function IDs have been defined by the specification for accessing the TRNG services. Therefore, add these definitions to the Arm standard SMC header. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/ArmHvcLibNull: Add NULL instance of ArmHvcLibPierre Gondois2022-11-063-0/+52
| | | | | | | Add a Null instance of ArmHvcLib in case of library dependencies. Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
* ArmPkg: Sort HVC/SMC section alphbetically in ArmPkg.dscPierre Gondois2022-11-061-2/+2
| | | | | | | | Sort the section containing HVC/SMC libraries prior to adding new libraries in this specific section. Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
* ArmPkg/ArmMonitorLib: Add ArmMonitorLibPierre Gondois2022-11-063-0/+64
| | | | | | | | | | The ArmMonitorLib provides an abstract interface to issue an HyperVisor Call (HVC) or System Monitor Call (SMC) depending on the default conduit. The PcdMonitorConduitHvc PCD allows to select the default conduit. Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* ArmPkg/ArmMonitorLib: Definition for ArmMonitorLib library classPierre Gondois2022-11-062-0/+47
| | | | | | | | | | | | | The ArmMonitorLib provides an abstract interface to issue an HyperVisor Call (HVC) or System Monitor Call (SMC) depending on the default conduit. The PcdMonitorConduitHvc PCD allows to select the default conduit. The new library relies on the ArmHvcLib and ArmSmcLib libraries. A Null instance of these libraries can be used for the unused conduit. Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* ArmPkg: PCD to select conduit for monitor callsSami Mujawar2022-11-061-1/+6
| | | | | | | | | | | | Define a PCD 'PcdMonitorConduitHvc' to select the conduit to use for monitor calls. PcdMonitorConduitHvc is defined as FALSE by default, meaning the SMC conduit is enabled as default. Adding PcdMonitorConduitHvc allows selection of HVC conduit to be used by virtual firmware implementations. Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* ArmPkg/ArmMmuLib: Reuse XIP MMU routines when splitting entriesArd Biesheuvel2022-10-195-10/+44
| | | | | | | | | | | | | | In order to reduce the likelihood that we will need to rely on the logic that disables and re-enables the MMU for updating a page table entry safely, expose the XIP version of the helper routine via a HOB and use it instead of the one that is copied into DRAM. Since the XIP copy is already clean to the PoC, and will never end up getting unmapped during a block entry split, we can use it safely without any cache maintenance, and without running the risk of pulling the rug from under our feet when updating an entry by going through an invalid mapping. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: permit initial configuration with MMU enabledArd Biesheuvel2022-10-191-22/+26
| | | | | | | | | | | | | | Permit the use of this library with the MMU and caches already enabled. This removes the need for any cache maintenance for coherency, and is generally better for robustness and performance, especially when running under virtualization. Note that this means we have to defer assignment of TTBR0 until the page tables are ready to be used, and so UpdateRegionMapping() can no longer read back TTBR0 directly to discover the root table address. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Disable and re-enable MMU only when neededArd Biesheuvel2022-10-193-29/+123
| | | | | | | | | | | | | When updating a page table descriptor in a way that requires break before make, we temporarily disable the MMU to ensure that we don't unmap the memory region that the code itself is executing from. However, this is a condition we can check in a straight-forward manner, and if the regions are disjoint, we don't have to bother with the MMU controls, and we can just perform an ordinary break before make. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: don't replace table entries with block entriesArd Biesheuvel2022-10-191-18/+2
| | | | | | | | | | | | Drop the optimization that replaces table entries with block entries and frees the page tables in the subhierarchy that is being replaced. This rarely occurs in practice anyway, and will require more elaborate TLB maintenance once we switch to a different approach where we no longer disable the MMU and nuke the TLB entirely every time we update a descriptor in a way that requires break-before-make (BBM). Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/SmbiosMiscDxe: Get SMBIOS information from OemMiscLibMinh Nguyen2022-09-234-11/+66
| | | | | | | | | | | | In some scenarios, the information of Bios Version, Bios Release and Embedded Controller Firmware Release are fetched during UEFI booting. This patch supports updating those fields dynamically when the PCDs are empty. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/SmbiosMiscDxe: Remove redundant updates in SMBIOS Type 2Minh Nguyen2022-09-231-10/+0
| | | | | | | | | | | This patch removes redundant updates of "BoardManufacturerType02" and "SerialNumberType02". Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/SmbiosMiscDxe: Fix typo of "AssetTagType02"Minh Nguyen2022-09-232-2/+3
| | | | | | | | | | | This patch fixes typo from "AssertTagType02" to "AssetTagType02". Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/SmbiosMiscDxe: Support fetching System UUIDNhi Pham2022-09-234-1/+36
| | | | | | | | | | | This adds an API to OemMiscLib for fetching the system UUID according to the platform. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg: Correct return value of "SMCCC_ARCH_SOC_ID" Function ID callMinh Nguyen2022-09-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | According to "SMC Calling Convention" specification, section 7.4, return value of Arm Architecture Calls is stored at first argument of SMC aguments (ARM_SMC_ARGS). This value can be negative values indicating error or positive values (including zero) indicating success. Positive value would contain information of respective Function ID (Section 7.3.4 and 7.4.4). For that reason, "SMCCC_VERSION" and "SMCCC_ARCH_FEATURES" Function ID calls read return value from "SmcCallStatus" variable (Args.Arg0 - first argument of SMC call). But "SMCCC_ARCH_SOC_ID" Function ID call is reading return value from "SmcParam" variable (Args.Arg1 - second argument of SMC call) so it leads to unexpected results of "Jep106Code" and "SocRevision". This patch is to correct it. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ProcessorSubClassDxe: Get processor version from OemMiscLibMinh Nguyen2022-09-232-1/+9
| | | | | | | | | | | | | | In some scenarios, the processor version may be updated dynamically from pre-UEFI firmware during booting. But the processor version is fixed with PCD (PcdProcessorVersion), so it can not be updated it dynamically. This patch will support setting that value both statically and dynamically. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg, ArmVirtPkg: put SpellCheck in AuditOnly modeArd Biesheuvel2022-09-101-1/+1
| | | | | | | | | | Don't allow spelling errors to break the CI build and inadvertently reject pull requests - spelling is important but not that important. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Remove duplicated wordsPierre Gondois2022-09-052-3/+3
| | | | | | | | | In an effort to clean the documentation of the above package, remove duplicated words, and fix a typo while at it. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.muajwar@arm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg: Handle warm reboot request correctlyPranav Madhu2022-09-052-2/+21
| | | | | | | | | | The warm reboot requests from OSPM are mapped to cold reboot. To handle the warm reboot separately from a cold reboot, update ArmSmcPsciResetSystemLib and to invoke the PSCI call with parameters for warm reboot. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* UefiCpuPkg: Simplify InitializeSeparateExceptionStacksLiu, Zhiguang2022-08-091-6/+9
| | | | | | | | | | | | | | | | Hide the Exception implementation details in CpuExcetionHandlerLib and caller only need to provide buffer Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* ArmPkg/CpuDxe: drop ARM_PROCESSOR_TABLE pseudo-ACPI tableArd Biesheuvel2022-07-225-147/+0
| | | | | | | | | | | The ARM_PROCESSOR_TABLE pseudo-ACPI table (which carries a ACPI-table like header but is published as a EFI config table) is not described in any relevant spec, and is not known to be relied upon by any OS. Let's just get rid of it. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg/Drivers: ArmGicIsInterruptEnabled returns incorrect valueRobbie King2022-07-011-4/+3
| | | | | | | | | | | | | | | | The issue appears to have been introduced by: 41fb5d46 : ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3 The changes to ArmGicIsInterruptEnabled() introduced the error where the Boolean result is assigned to Interrupts, but then the bit position check is performed again (against the computed Boolean result instead of the interrupt mask) during the return statement. Fix removes erroneous test and relies on boolean test made at return. Signed-off-by: Robbie King <robbiek@xsightlabs.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/ArmExceptionLib: Follow new CpuExceptionHandlerLib APIsRay Ni2022-06-141-47/+11
| | | | | | | | | | | | | | | | | CpuExceptionHandlerLib has been refactored with following changes: 1. Removed InitializeCpuInterruptHandlers in 2a09527ebcb459b40 2. Removed InitializeCpuExceptionHandlersEx and added InitializeSeparateExceptionStacks in e7abb94d1fb8a0e7 The patch updates ARM version of CpuExceptionHandlerLib to follow the API changes. The functionality to ARM platforms should be none. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Remove RVCT supportRebecca Cran2022-05-1327-1552/+0
| | | | | | | | RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/ArmMmuLib AARCH64: avoid EL0 accessible mappingsArd Biesheuvel2022-02-012-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | We never run any code at EL0, and so it would seem that any access permissions set for EL0 (via the AP[1] attribute in the page tables) are irrelevant. We currently set EL0 and EL1 permissions to the same value arbitrarily. However, this causes problems on hardware like the Apple M1 running the MacOS hypervisor framework, which enters EL1 with SCTLR_EL1.SPAN enabled, causing the Privileged Access Never (PAN) feature to be enabled on any exception taken to EL1, including the IRQ exceptions that handle our timer interrupt. When PAN is enabled, EL1 has no access to any mappings that are also accessible to EL0, causing the firmware to crash if it attempts to access such a mapping. Even though it is debatable whether or not SCTLR_EL1.SPAN should be disabled at entry or whether the firmware should put all UNKNOWN bits in all system registers in a consistent state (which it should), using EL0 permissions serves no purpose whatsoever so let's fix that regardless. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Alexander Graf <agraf@csgraf.de> Acked-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Replace CoreId and ClusterId with Mpidr in ARM_CORE_INFO structRebecca Cran2022-01-302-2/+5
| | | | | | | | | | | Remove the ClusterId and CoreId fields in the ARM_CORE_INFO structure in favor of a new Mpidr field. Update code in ArmPlatformPkg/PrePeiCore/MainMPCore and ArmPlatformPkg/PrePi/MainMPCore.c to use the new field and call new macros GET_MPIDR_AFF0 and GET_MPIDR_AFF1 instead. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg: MmCommunicationDxe: Update MM communicate `MessageLength` checkKun Qin2022-01-271-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3751 Current MM communicate routine from ArmPkg would conduct few checks prior to proceeding with SMC calls. However, the inspection step is different from PI specification. This patch updated MM communicate input argument inspection routine to assure that "if the `MessageLength` is zero, or too large for the MM implementation to manage, the MM implementation must update the `MessageLength` to reflect the size of the `Data` buffer that it can tolerate", as described by `EFI_MM_COMMUNICATION_PROTOCOL.Communicate()` section in PI specification. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: MmCommunicationDxe: Update MM communicate `CommSize` checkKun Qin2022-01-271-7/+12
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3751 Current MM communicate routine from ArmPkg would conduct few checks prior to proceeding with SMC calls. However, the inspection step is different from PI specification. This patch updated MM communicate input argument inspection routine to assure `CommSize` represents "the size of the data buffer being passed in" instead of the size of the data being used from data buffer, as described by section `EFI_MM_COMMUNICATION2_PROTOCOL.Communicate()` in PI specification. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: MmCommunicationDxe: Update MM communicate `CommBuffer**` checksKun Qin2022-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3751 Current MM communicate routine from ArmPkg would conduct few checks prior to proceeding with SMC calls. However, the inspection step is different from PI specification. This patch updated MM communicate input argument inspection routine to assure that return code `EFI_INVALID_PARAMETER` represents "the `CommBuffer**` parameters do not refer to the same location in memory", as described by `EFI_MM_COMMUNICATION2_PROTOCOL.Communicate()` section in PI specification. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: MmCommunicationDxe: MM communicate function argument attributesKun Qin2022-01-271-6/+7
| | | | | | | | | | | | | | | | | | Current MM communicate2 function from ArmPkg described input arguments `CommBufferPhysical`, `CommBufferVirtual` and `CommSize` as input only, which mismatches with the "input and output type" as in PI specification. This change updated function descriptions of MM communite2 to match input argument types. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg/ProcessorSubClassDxe: Get serial and part number from OemMiscLibNhi Pham2021-12-162-2/+14
| | | | | | | | | | | Currently, the serial and part number of a processor are filled with fixed PCDs. However, they may be updated dynamically according to the information being passed from a the pre-UEFI firmware during booting. So, this patch is to support updating these string fields from OemMiscLib if the PCDs are empty. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg/SmbiosMiscDxe: Get full SMBIOS strings from OemMiscLibNhi Pham2021-12-163-0/+33
| | | | | | | | | | | Typically, the information of the SMBIOS type 1/2/3 is fetched from an FRU device during UEFI booting intead of fixed PCDs. Therefore, this patch is to add more HII string fields in the OemMiscLib and support updating these SMBIOS types with the strings provided by the OemMiscLib if the PCDs are empty. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-10 04:08:44 +0000