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* ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributorArd Biesheuvel2016-07-131-3/+22
| | | | | | | | | | | | Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon <ndhillonv2@gmail.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: avoid type promotion in TCR_EL1 assignmentArd Biesheuvel2016-07-131-78/+62
| | | | | | | | | | | | | | | | | | | | | | Commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1") introduced a symbolic constant TCR_TG1_4KB which resolves to (2 << 30), and ORs it into the value to be written into TCR_EL1 (if executing at EL1). Since the constant is implicitly typed as signed int, and has the sign bit set, the promotion that occurs when casting to UINT64 results in a TCR value that has bits [63:32] all set, which includes mostly RES0 bits but also the TBIn, AS and IPS fields. So explicitly redefine all TCR related constants as 'unsigned long' types, using the UL suffix. To avoid confusion in the future, the inappropriately named VTCR_EL23_xxx constants have the leading V removed, and the actual VTCR_EL2 related constants are dropped, given that we never configure stage 2 translation in UEFI. Reported-by: Vishal Oliyil Kunnil <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
* ArmPkg: Fix typos in commentsGiri P Mudusuru2016-07-111-1/+1
| | | | | | | | | | EFI_UNSUPPORTEDT to EFI_UNSUPPORTED Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib: add PEI specific version of ArmMmuLibArd Biesheuvel2016-07-072-0/+97
| | | | | | | | | | | | This introduces a special version of ArmMmuLib for PEIMs that takes care only to perform cache maintenance on the live entry replacement routine if the module is not executing in place. Not only is such cache maintenance unnecessary in that case, it may be actively harmful on some systems that fail to tolerate cache maintenance operations on NOR flash regions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLibArd Biesheuvel2016-07-0714-1282/+1
| | | | | | | | | | | | Switch all users of ArmLib that depend on the MMU routines to the new, separate ArmMmuLib. This needs to occur in one go, since the MMU routines are removed from ArmLib build at the same time, to prevent conflicting symbols. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* ArmPkg: introduce base ArmMmuLib implementationArd Biesheuvel2016-07-076-0/+1406
| | | | | | | | | | | This base library encapsulates the MMU manipulation routines that have been factored out of ArmLib. The functionality covers initial creation of the 1:1 mapping in the page tables, and remapping regions to change permissions or cacheability attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: introduce ArmMmuLib library classArd Biesheuvel2016-07-072-0/+66
| | | | | | | | | Introduce the library class ArmMmuLib, which encapsulates the functionality to set up and modify page table entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: unmask SErrors in DEBUG buildsArd Biesheuvel2016-07-011-0/+9
| | | | | | | | | | | | | | | | | | | SErrors (formerly called asynchronous aborts) are a distinct class of exceptions that are not closely tied to the currently executing instruction. Since execution may be able to proceed in such a condition, this class of exception is masked by default, and software needs to unmask it explicitly if it is prepared to handle such exceptions. On DEBUG builds, we are well equipped to report the CPU context to the user and it makes sense to report an SError as soon as it occurs rather than to wait for the OS to take it when it unmasks them, especially since the current arm64/Linux implementation simply panics in that case. So unmask them when ArmCpuDxe loads. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: put ASSERT (FALSE) lastArd Biesheuvel2016-07-011-1/+1
| | | | | | | | | | | Putting DEBUG () code after an ASSERT (FALSE) statement is not very useful, since the code will be unreachable on DEBUG builds and compiled out on RELEASE builds. So move the ASSERT () statement after it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1Ard Biesheuvel2016-06-232-2/+19
| | | | | | | | | | | | Reassign all interrupts to non-secure Group-1 if the GIC has its DS (Disable Security) bit set. In this case, it is safe to assume that we own the GIC, and that no other firmware has performed any configuration yet, which means it is up to us to reconfigure the interrupts so they can be taken by the non-secure firmware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: avoid cache maintenance in PEIMs when executing in placeArd Biesheuvel2016-06-155-1/+121
| | | | | | | | | | | | | | On some platforms, performing cache maintenance on regions that are backed by NOR flash result in SErrors. Since cache maintenance is unnecessary in that case, create a PEIM specific version that only performs said cache maintenance in its constructor if the module is shadowed in RAM. To avoid performing the cache maintenance if the MMU code is not used to begin with, check that explicitly in the constructor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: implement new generic versionArd Biesheuvel2016-05-124-0/+1379
| | | | | | | | | This implements the platform glue for the new generic BDS implementation. It is based on the ArmVirtQemu version, with the QEMU references removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: don't invalidate entire I-cache on range operationArd Biesheuvel2016-05-125-11/+43
| | | | | | | | | | | Instead of cleaning the data cache to the PoU by virtual address and subsequently invalidating the entire I-cache, invalidate only the range that we just cleaned. This way, we don't invalidate other cachelines unnecessarily. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AArch64Mmu: don't let table entries inherit XN permission bitsArd Biesheuvel2016-05-101-7/+0
| | | | | | | | | | | | | | | | | | When we split a block entry into a table entry, the UXN/PXN/XN permission attributes are inherited both by the new table entry and by the new block entries at the next level down. Unlike the NS bit, which only affects the next level of lookup, the XN table bits supersede the permissions of the final translation, and setting the permissions at multiple levels is not only redundant, it also prevents us from lifting XN restrictions on a subregion of the original block entry by simply clearing the appropriate bits at the lowest level. So drop the code that sets the UXN/PXN/XN bits on the table entries. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: assert that consistent mappings are uncachedArd Biesheuvel2016-05-101-0/+17
| | | | | | | | | | | | | | | | | DmaMap () only allows uncached mappings to be used for creating consistent mappings with operation type MapOperationBusMasterCommonBuffer. However, if the buffer passed to DmaMap () happens to be aligned to the CWG, there is no need for a bounce buffer, and we perform the cache maintenance directly without ever checking if the memory attributes of the buffer adhere to the API. So add some debug code that asserts that the operation type and the memory attributes are consistent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: do not remap arbitrary memory regions as uncachedArd Biesheuvel2016-05-101-6/+0
| | | | | | | | | | | | | | | | In the DmaMap () operation, if the region to be mapped happens to be aligned to the Cache Writeback Granule (CWG) (whose value is typically 64 or 128 bytes and 2 KB maximum), we remap the memory as uncached. Since remapping memory occurs at page granularity, while the buffer and the CWG may be much smaller, there is no telling what other memory we affect by doing this, especially since the operation is not reverted in DmaUnmap(). So remove the remapping call. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: reject consistent DMA mappings of cached memoryArd Biesheuvel2016-05-101-3/+23
| | | | | | | | | | | | | | | | | | | | DmaMap () operations of type MapOperationBusMasterCommonBuffer should return a mapping that is coherent between the CPU and the device. For this reason, the API only allows DmaMap () to be called with this operation type if the memory to be mapped was allocated by DmaAllocateBuffer (), which in this implementation guarantees the coherency by using uncached mappings on the CPU side. This means that, if we encounter a cached mapping in DmaMap () with this operation type, the code is either broken, or someone is violating the API, but simply proceeding with a double buffer makes no sense at all, and can only cause problems. So instead, actively reject this operation type for cached memory mappings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: interpret GCD attributes as a bit fieldArd Biesheuvel2016-05-101-3/+1
| | | | | | | | | | | | Comparing a GCD attribute field directly against EFI_MEMORY_UC and EFI_MEMORY_WT is incorrect, since it may have other bits set as well which are not related to the cacheability of the region. So instead, test explicitly against the flags EFI_MEMORY_WB and EFI_MEMORY_WT, which must be set if the region may be mapped with cacheable attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: consistently use 'gCacheAlignment - 1' as alignment maskArd Biesheuvel2016-05-101-1/+1
| | | | | | | | | | | We manage to use both an AND operation with 'gCacheAlignment - 1' and a modulo operation with 'gCacheAlignment' in the same compound if statement. Since gCacheAlignment is a global of which the compiler cannot guarantee that it is a power of two, simply use the AND version in both cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmDmaLib: deal with NULL return value of UncachedAllocatePages ()Ard Biesheuvel2016-05-101-2/+10
| | | | | | | | | | | The allocation function UncachedAllocatePages () may return NULL, in which case our implementation of DmaAllocateBuffer () should return EFI_OUT_OF_RESOURCES rather than silently ignoring the NULL value and returning EFI_SUCCESS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: fix typoArd Biesheuvel2016-05-091-1/+1
| | | | | | | Replace : with ; which was changes accidentally. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: add stack dump to exception handling codeArd Biesheuvel2016-05-091-0/+21
| | | | | | | | | | | This adds a partial stack dump (256 bytes at either side of the stack pointer) to the CPU state dumping routine that is invoked when taking an unexpected exception. Since dereferencing the stack pointer may itself fault, ensure that we don't enter the dumping routine recursively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: use deadloop rather than ASSERTArd Biesheuvel2016-05-091-1/+3
| | | | | | | | | | | | | | | | The default exception handler, which is essentially the one that is invoked for unexpected exceptions, ends with an ASSERT (FALSE), to ensure that execution halts after dumping the CPU state. However, ASSERTs are compiled out in RELEASE builds, and since we simply return to wherever the ELR is pointing, we will not make any progress in case of synchronous aborts, and the same exception will be taken again immediately, resulting in the string 'Exception at 0x....' to be printed over and over again. So use an explicit deadloop instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: implement CpuIo2 protocol driver specific for PCIArd Biesheuvel2016-04-292-0/+612
| | | | | | | | | | | | | | | | | The CpuIo2 protocol is required by the generic PciHostBridgeDxe driver, which relies on it to back its own I/O and MMIO operations. Since ARM has no native I/O port equivalent, such accesses can only originate from PCI drivers, and the PCI I/O space is translated to MMIO in this case. So we can implement this protocol using MMIO operations only, and take the PCI I/O translation offset into account when performing I/O port accesses. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: move PCI related PCD definitions to ArmPkgArd Biesheuvel2016-04-291-0/+62
| | | | | | | | | | | | | | The PCI related PCDs are not platform specific, and architectural protocols such as CpuIo2 are based on PCI provided MMIO to IO translation, so these PCDs belong in ArmPkg not ArmPlatformPkg. NOTE: this *WILL* break some out-of-tree platforms, the fix is changing all consumers of gArmPlatformTokenSpaceGuid.PcdPci* to gArmTokenSpaceGuid.PcdPci* Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Gic: Fix boundary checking bugHeyi Guo2016-04-253-9/+9
| | | | | | | | | mGicNumInterrupts is the total number of interrupts, so the interrupt ID equal to mGicNumInterrupts is also invalid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/AArch64Mmu: disable MMU during page table manipulationsArd Biesheuvel2016-04-145-2/+124
| | | | | | | | | | | | | | | | | | | | On ARM, manipulating live page tables is cumbersome since the architecture mandates the use of break-before-make, i.e., replacing a block entry with a table entry requires an intermediate step via an invalid entry, or TLB conflicts may occur. Since it is not generally feasible to decide in the page table manipulation routines whether such an invalid entry will result in those routines themselves to become unavailable, use a function that is callable with the MMU off (i.e., a leaf function that does not access the stack) to perform the change of a block entry into a table entry. Note that the opposite should never occur, i.e., table entries are never coalesced into block entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
* ArmPkg/AArch64Mmu: Fix XN attribute for device memoryHeyi Guo2016-04-141-2/+2
| | | | | | | | | | | | | Now XN attribute will be set automatically if the region is declared as device memory. However, the function ArmMemoryAttributeToPageAttribute is to get attribute for block and page descriptors, not for table descriptors, so attribute TT_TABLE_*XN does not really take effect. Need to use TT_*XN_MASK instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmArchTimerLib: correct typosEvan Lloyd2016-04-011-8/+8
| | | | | | | | | | | Some minor typographical problems were noticed during previous commits. This change corrects those, and contains no functional modifications. The changes are in comments, and one diagnostic message. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmArchTimerLib: fix unused variable in RELEASE buildsSami Mujawar2016-04-011-3/+2
| | | | | | | | | | | | | | | | The TimerFreq variable in the TimerConstructor() is unused in RELEASE builds since ASSERTs are then disabled. The only use of the variable (in the ASSERT) is replaced by a direct invocation of the function previously used to set it. NOTE: The build tools suppress warnings of this using compiler options eg. -Wno-unused-but-set-variable for GCC toolchain or --diag_suppress=550 for RVCT toolchain. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmArchTimerLib: add GetTimeInNanoSecond() to ArmArchTimerLibSami Mujawar2016-04-011-1/+50
| | | | | | | | | | FirmwarePerformanceDxe.c utilizes the Timer Library function GetTimeInNanoSecond() which was not implemented by the ArmArchTimerLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArchArmTimerLib: refactor MultU64xN and TimerFreq definitionsSami Mujawar2016-04-011-18/+31
| | | | | | | | | | | | | | This refactors some timer code to define MultU64xN as a preprocessor symbol rather than a function pointer, and to factor out the code that obtains the timer frequency into GetPlatformTimerFreq (). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 [ard.biesheuvel: split off from 'add GetTimeInNanoSecond() to ArmArchTimerLib'] Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg|EmbeddedPkg: make PcdCpuVectorBaseAddress 64 bits wideLeendert van Doorn2016-03-252-4/+4
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: apply Cortex-A57 errataLeendert van Doorn2016-03-251-3/+6
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/AArch64Mmu: use correct AP[] bits in ArmClearMemoryRegionReadOnlyArd Biesheuvel2016-03-221-1/+1
| | | | | | | | | | | | | The function ArmClearMemoryRegionReadOnly() was supposed to undo the effect of ArmSetMemoryRegionReadOnly(), but instead, it sets the permissions to EL0-no access, EL1-read-only. Since the EL0 bit should be 1 to align with EL2/3 (where the bit is SBO), use TT_AP_RW_RW instead, which makes the entry read-write for EL0 when executing at EL1, and read-write for all other levels. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmExceptionLib: reimplement register stack/unstack routinesArd Biesheuvel2016-03-221-126/+109
| | | | | | | | | | | | | | | | This replaces the somewhat opaque preprocessor based stack/unstack macros with open coded ldp/stp sequences to preserve the interrupted context before handing over to the exception handler in C. This removes various arithmetic operations on the stack pointer, and reduces the exception return critical section to its minimum size (i.e., the bare minimum required to populate the ELR and SPSR registers and invoke the eret). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: avoid indirect call if using vector table in placeArd Biesheuvel2016-03-221-0/+4
| | | | | | | | | | | If we are using the vector table in place, there is no need to make an indirect call to the common handler routine from the vector table entries, so just use a straight branch instruction in that case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: make build time define visible to the compilerArd Biesheuvel2016-03-221-2/+4
| | | | | | | | | | | | | | The global gArmRelocateVectorTable is a build time constant, but due to its external linkage and lack of constness, the compiler does not see that. So turn it into a static boolean, and at the same time, make the function CopyExceptionHandlers() (which is only called if gArmRelocateVectorTable is set) static as well, so that the compiler can eliminate it completely if we are using the vector table in place. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: don't restore ESR and FAR upon exception returnArd Biesheuvel2016-03-221-6/+0
| | | | | | | | | | | ESR and FAR are populated by the hardware upon exception entry, and describe the exception, not the interrupted context. So there is no point in restoring their values before returning from the exception. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: stack FPSR on common pathArd Biesheuvel2016-03-221-8/+6
| | | | | | | | | | | We have three code paths to stack/unstack the exception context, one for each of EL3, EL2 and EL1. However, they all access the same copy of FPSR so move that access to the common path. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmExceptionLib: fold exception handler prologue into vector tableArd Biesheuvel2016-03-221-73/+39
| | | | | | | | | | | | | | | | Unlike the AArch32 vector table, which has room for a single instruction for each exception type, the AArch64 exception table has 128 byte slots, which can easily hold the shared prologues that are emitted out of line. So refactor this code into a single macro, and expand it into each vector table slot. Since the address of the command handler entry point is no longer patched in by the C code, we can just emit the literal into each vector entry directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/AsmMacroIoLibV8: remove undocumented assumption from ELx macrosArd Biesheuvel2016-03-221-8/+8
| | | | | | | | | | | | | | | The macros EL1_OR_EL2() and EL1_OR_EL2_OR_EL3() allow conditional execution of assembly sequences based on the current exception level, by jumping to caller supplied labels 1f, 2f or 3f. However, the jump to 1f is actually a fallthrough, which means the EL1 code needs to follow right after the macro invocation, and the 1f label is ignored. So let's fix this by making all jumps explicit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg: update CpuDxe to use CpuExceptionHandlerLibCohen, Eugene2016-03-177-1402/+98
| | | | | | | | | | Use the new ARM/AArch64 implementation of the base CpuExceptionHandlerLib library from CpuDxe to centralize exception handling. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: ARM/AArch64 implementation of CpuExceptionHandlerLibCohen, Eugene2016-03-169-0/+1577
| | | | | | | | | | | | | | | | | | | | | | | Introduce ARM and AArch64 instances of the CpuExceptionHandlerLib which provides exception handling and registration of handlers regardless of execution phase. Two variants of the ArmExceptionLib are provided: one where exception handlers reside within the module (meeting appropriate architectural alignment requirements for the vector table) and another one that will relocate a copy of thee xception handlers to an address specified by PcdCpuVectorBaseAddress. The ArmRelocateExceptionLib is intended for use in cases where ArmExceptionLib is too large for the application (uncompressed XIP images) as driven by the vector table alignment padding. The AArch64 build of this library supports execution at EL1, EL2, and EL3 exception levels. Tested on ARM, and AArch64 with SEC, DXE Core, and CpuDxe modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCRCohen, Eugene2016-03-162-0/+11
| | | | | | | | | Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Configure TTBCR registerEvan Lloyd2016-03-034-4/+32
| | | | | | | | | | | | | Architecturally, the TTBCR register value is undefined at reset for Non-Secure. On some platforms the reset value for TTBCR is not zero and this causes a data abort exception once the MMU is enabled. This patch configures the TTBCR register to enable translation table walk using TTBR0. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
* ArmPkg: CpuDxe: don't track interrupt state in a global variableCohen, Eugene2016-02-231-5/+1
| | | | | | | | | | | Update the CpuDxe driver to remove an assumption that it is the only component modifying interrupt state since this can be done through BaseLib as well. Instead of using a global variable for last interrupt state we now check the current PSTATE value directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: CpuDxe: fix AArch64 interrupt read masksCohen, Eugene2016-02-232-25/+23
| | | | | | | | | | | | | | The AArch64 DAIF bits are different for reading (mrs) versus writing (msr). The bitmask definitions assumed they were the same causing incorrect results when trying to determine the current interrupt state through ArmGetInterruptState. The logic for interpreting the DAIF read data using the csel instruction was also incorrect and is fixed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: DefaultExceptionHandler fixes for use with DxeCoreCohen, Eugene2016-02-154-38/+12
| | | | | | | | | | | Modify the DefaultExceptionHandler (uefi-variant) so it can be used by DxeCore (via CpuExceptionHandlerLib) where the debug info table is not yet published at library constructor time. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add isb when setting SCREvan Lloyd2016-02-033-0/+3
| | | | | | | | | | | | Some updates to SCR can cause a problem which manifests as an undefined opcode exception. This may be when a speculative secure instruction fetch happens after the NS bit is set. An isb is required to make the register change take effect fully. Contributed-under: Tianocore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com> Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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