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* ArmPkg/ArmMmuLib: Explicitly cast function pointer argumentMichael Kubacki2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | | The function ArmReplaceLiveTranslationEntry () is passed as a VOID pointer to WriteBackDataCacheRange (). This produces the following warning on VS2019: warning C4152: nonstandard extension, function/data pointer conversion in expression This change explicitly casts the argument to the formal parameter type VOID*. This can be reproduced with the following build command: build -b DEBUG -a AARCH64 -t VS2019 -p ArmPkg/ArmPkg.dsc -m ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmMmuLib: Explicitly cast UINT32 data conversionsMichael Kubacki2020-10-222-4/+4
| | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2835 There's several occurrences of a UINT64 or an EFI_PHYSICAL_ADDRESS being assigned to a UINT32 value in ArmMmuLib. These result in warning C4244 in VS2019: warning C4244: '=': conversion from 'UINT64' to 'UINT32', possible loss of data warning C4244: '=': conversion from 'EFI_PHYSICAL_ADDRESS' to 'UINT32', possible loss of data This change explicitly casts the values to UINT32. These can be reproduced with the following build command: build -b DEBUG -a ARM -t VS2019 -p ArmPkg/ArmPkg.dsc -m ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmMmuLib: Fix implicit castPierre Gondois2020-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | While building with the following command line: build -b DEBUG -a AARCH64 -t VS2017 -p MdeModulePkg\MdeModulePkg.dsc A missing cast triggers the following warning, then triggering an error: ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c(652): warning C4152: nonstandard extension, function/data pointer conversion in expression This patch first casts the function pointer to (UINTN), then to (VOID *), followowing the C99 standard s6.3.2.3 "Pointer", paragraphs 5 and 6. This suppresses the warning. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Suggested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/PlatformBootManagerLib: regenerate boot options on boot failureArd Biesheuvel2020-06-171-0/+34
| | | | | | | | | | | | | | | | | | | | | | | One of the side effects of the recent changes to PlatformBootManagerLib changes to avoid connecting all devices on every boot is that we no longer default to network boot on a virgin boot, but end up in the UiApp menu. At this point, the UiApp will instantiate the autogenerated boot options that we used to rely on as before, but since we are already sitting idle in the root UiApp menu at that point, it does break the unattended boot case where devices are expected to attempt a network boot on the very first power on. Let's work around this by refreshing all boot options explicitly in the UnableToBoot() handler, and rebooting the system if doing so resulted in a change to the total number of configured boot options. This way, we ultimately end up in the UiApp as before if no boot options could be started, but only after all the autogenerated ones have been attempted as well. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
* ArmPkg/ArmExceptionLib: use static buffer for sp_el0Heyi Guo2020-06-101-8/+6
| | | | | | | | | | | | | The exception library is also used in DxeMain before memory services are available, and AllocatePages() will fail in this case and cause sp_el0 remains 0. Then if any exception occurs before CpuDxe driver is loaded, a recursive exception will be trigged by page translation fault for sp = 0 - 0x130. Use static buffer instead to fix this issue. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg: only attempt buildin MmCommunicationDxe for AArch64Leif Lindholm2020-06-071-1/+1
| | | | | | | | | | | Commit 045e4b84c18f ("ArmPkg/ArmPkg.dsc: Add missing components") adds some components to the ArmPkg.dsc build config, but it adds them to Components.common, and MmCommunicationDxe is AArch64 only. Move it to Components.AARCH64 to stop the ARM build breaking. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/PlatformBootManagerLib: don't connect all devices on each bootArd Biesheuvel2020-06-061-10/+0
| | | | | | | | | | | | | | | | | In order to avoid boot delays from devices such as network controllers that may not even be involved in booting at all, drop the call to EfiBootManagerConnectAll () from the boot path. It will be called by UiApp, so when going through the menu, all devices will be connected as usual, but for the default boot, it is really not necessary so let's get rid of this. Enumerating all possible boot options and creating Boot#### variables for them is equally unnecessary in the default case, and also happens automatically in UiApp, so drop that as well. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/PlatformBootManagerLib: hide UEFI Shell as a regular boot optionArd Biesheuvel2020-06-061-3/+1
| | | | | | | | | | | | | Without ConnectAll() being called on the boot path, the UEFI shell will be entered with no block devices or anything else connected, and so for the novice user, this is not a very accommodating environment. Now that we have made the UiApp the last resort on boot failure, and made the UEFI Shell accessible directly via the 's' hotkey if you really need it, let's hide it as an ordinary boot option. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/PlatformBootManagerLib: fall back to the UiApp on boot failureArd Biesheuvel2020-06-061-1/+11
| | | | | | | | | | | | | | As a last resort, drop into the UiApp application when no active boot options could be started. Doing so will connect all devices, and so it will allow the user to enter the Boot Manager submenu and pick a network or removable disk option. Note that this only occurs if even the default removable filepath could not be booted (e.g., \EFI\BOOT\BOOTAA64.EFI on AArch64) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/PlatformBootManagerLib: register 's' as UEFI Shell hotkeyArd Biesheuvel2020-06-061-2/+9
| | | | | | | | | | | | | | | | In preparation of hiding the UEFI Shell boot option as an ordinary boot option, make sure we can invoke it directly using the 's' hotkey. Without ConnectAll() having been called, this results in a shell that may have no block devices or other things connected, so don't advertise the 's' in the console string that is printed at boot - for novice users, we will go through the UiApp which connects everything first. For advanced use, having the ability to invoke the UEFI shell without any devices connected may be an advantage, so let's keep this behavior as is for now. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/PlatformBootManagerLib: connect non-discoverable USB hostsArd Biesheuvel2020-06-062-0/+46
| | | | | | | | | | | | | | | | | | | | | | The way the BDS handles the short-form USB device path of the console keyboard relies on USB host controllers to be locatable via their PCI metadata, which implies that these controllers already have a PCI I/O protocol installed on their handle. This is not the case for non-discoverable USB host controllers that are supported by the NonDiscoverable PCI device driver. These controllers must be connected first, or the BDS will never notice their existence, and will not enable any USB keyboards connected through them. Let's work around this by connecting these handles explicitly. This is a bit of a stopgap, but it is the cleanest way of dealing with this without violating the UEFI driver model entirely. This ensures that platforms that do not rely on ConnectAll() will keep working as expected. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/ArmSvcLib: prevent speculative execution beyond svcVijayenthiran Subramaniam2020-06-053-3/+12
| | | | | | | | | | | | | | | | | | | | | Supervisor Call instruction (SVC) is used by the Arm Standalone MM environment to request services from the privileged software (such as ARM Trusted Firmware running in EL3) and also return back to the non-secure caller via EL3. Some Arm CPUs speculatively executes the instructions after the SVC instruction without crossing the privilege level (S-EL0). Although the results of this execution are architecturally discarded, adversary running on the non-secure side can manipulate the contents of the general purpose registers to leak the secure work memory through spectre like micro-architectural side channel attacks. This behavior is demonstrated by the SafeSide project [1] and [2]. Add barrier instructions after SVC to prevent speculative execution to mitigate such attacks. [1]: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc [2]: https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmPkg.dsc: set terminal type PCD to the right valueArd Biesheuvel2020-06-031-0/+3
| | | | | | | | | PlatformBootManagerLib now asserts at build time that the correct terminal type is used, and so leaving it unset breaks the ArmPkg DSC build. So fix that. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/PlatformBootManagerLib: reject 'default' parity and stop bit countArd Biesheuvel2020-06-031-0/+4
| | | | | | | | | | | | | | | | | | | | In the ArmPkg version of PlatformBootManagerLib, we construct a serial device path based on the default settings for baud rate, parity and the number of stop bits, to ensure that a serial console is available even on the very first boot. This assumes that PcdUartDefaultParity or PcdUartDefaultStopBits are not set to '0', meaning 'the default', as there is no default for these when constructing a device path. So add a couple of STATIC_ASSERT()s to make sure that we catch this condition, since it otherwise ignores the bogus device path silently, which is rather tedious to debug,. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/PlatformBootManagerLib: use static assertion for console typeArd Biesheuvel2020-06-031-1/+3
| | | | | | | | | | | | | | | | Replace the runtime ASSERT with the build time STATIC_ASSERT on the check that ensures that the terminal type we use for the serial console matches the one we explicitly add to the ConIn/ConOut/StdErr variables. This helps catch serial console issues early, even in RELEASE builds, reducing the risk of ending up with no console at all, which can be tricky to debug on bare metal. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/CompilerIntrinsicsLib: provide atomics intrinsicsedk2-stable202005Ard Biesheuvel2020-06-022-0/+145
| | | | | | | | | | | | | | | | | Gary reports the GCC 10 will emit calls to atomics intrinsics routines unless -mno-outline-atomics is specified. This means GCC-10 introduces new intrinsics, and even though it would be possible to work around this by specifying the command line option, this would require a new GCC10 toolchain profile to be created, which we prefer to avoid. So instead, add the new intrinsics to our library so they are provided when necessary. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Tested-by: Gary Lin <glin@suse.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* ArmPkg/MmCommunicationDxe: expose MM Communicate 2 protocolArd Biesheuvel2020-05-122-48/+43
| | | | | | | | | | | | | Implement the new MmCommunication2 protocol which supports the use of standalone MM at runtime inside an address space that has been virtually remapped by the OS. Note that the implementation of the old MM Communicate protocol is removed: it never worked correctly so there is no point in keeping it. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: rename misleading local #define in CpuDxeLeif Lindholm2020-04-061-7/+7
| | | | | | | | | | | The local #define TT_ATTR_INDX_INVALID is used as a local error code in the AArch64 implementation, but is misleadingly named to match the definitions in ArmPkg/Include/Chipset/AArch64Mmu.h. Rename it INVALID_ENTRY to reduce confusion and improve readability. Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmMmuLib: drop unused TT_ATTR_INDX_INVALID CPP macroArd Biesheuvel2020-04-021-3/+0
| | | | | | | | | | | TT_ATTR_INDX_INVALID is #define'd but never used so drop it. Note that this leaves a CPP macro of the same name in CpuDxe, but there, it is actually being used, and although the name suggests that this value is somehow defined by the architecture, this is really not the case and it only has meaning within the scope of CpuDxe's implementation. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib: get rid of GetRootTranslationTableInfo()Ard Biesheuvel2020-04-021-16/+6
| | | | | | | | | Only a single call to GetRootTranslationTableInfo() remains, which only provides the root table level. So let's create a new static helper function that returns just this value, and use it instead. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib: drop pointless LookupAddresstoRootTable() routineArd Biesheuvel2020-04-021-34/+15
| | | | | | | | | | | | | | LookupAddresstoRootTable() uses a loop to go over its MaxAddress argument, essentially to do a log2() and determine how many bits are needed to represent it. Since the argument is the result of a shift-left expression, there is some room for improvement here, and we can simply use the bit count directly to calculate the value of T0SZ. At the same time, we can omit calling GetRootTranslationTableInfo() to determine the number of root table entries, and add a new helper that applies the trivial calculation directly. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/CpuDxe: move PageAttributeToGcdAttribute() out of ArmMmuLibArd Biesheuvel2020-04-023-50/+46
| | | | | | | | | The routine PageAttributeToGcdAttribute() is exported by ArmMmuLib but only ever used in the implementation of CpuDxe. So let's move the function there and make it STATIC. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/CpuDxe: use private copy of GetRootTranslationTableInfo()Ard Biesheuvel2020-04-022-7/+15
| | | | | | | | | | | | | | | | | Before getting rid of GetRootTranslationTableInfo() and the related LookupAddresstoRootTable() in AARCH64's version of ArmMmuLib, add a version of the former to CpuDxe, which will be its only remaining user. While at it, simplify it a bit, since in the CpuDxe cases, both OUT arguments are always provided. Note that this removes the declaration of GetRootTranslationTableInfo() as well, but this is a declaration that is private to CpuDxe, and it really doesn't belong here in the first place. Since ArmMmuLib's version of GetRootTranslationTableInfo() is going to be replaced shortly anyway, don't bother moving this .h declaration elsewhere. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib AARCH64: preserve attributes when replacing a table entryArd Biesheuvel2020-03-261-4/+21
| | | | | | | | | | | | | | | | | | | | | | Currently, depending on the size of the region being (re)mapped, the page table manipulation code may replace a table entry with a block entry, even if the existing table entry uses different mapping attributes to describe different parts of the region it covers. This is undesirable, and instead, we should avoid doing so unless we are disregarding the original attributes anyway. And if we make such a replacement, we should free all the page tables that have become orphaned in the process. So let's implement this, by taking the table entry path through the code for block sized regions if a table entry already exists, and the clear mask is set (which means we are preserving attributes from the existing mapping). And when we do replace a table entry with a block entry, free all the pages that are no longer referenced. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/ArmMmuLib AARCH64: use helpers to determine table entry typesArd Biesheuvel2020-03-261-5/+35
| | | | | | | | | | | | Given how the meaning of the attribute bits for page table entry types is slightly awkward, and changes between levels, add some helpers to abstract from this. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/ArmMmuLib AARCH64: limit recursion when freeing page tablesArd Biesheuvel2020-03-261-6/+12
| | | | | | | | | | | | | | | | | | | | FreePageTablesRecursive () traverses the page table tree depth first to free all pages that it finds, without taking into account the level at which it is operating. Since TT_TYPE_TABLE_ENTRY aliases TT_TYPE_BLOCK_ENTRY_LEVEL3, we cannot distinguish table entries from block entries unless we take the level into account, and so we may be dereferencing garbage if we happen to try and free a hierarchy of page tables that has level 3 pages in it. Let's fix this by passing the level into FreePageTablesRecursive (), and limit the recursion to levels < 3. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/ArmPkg.dsc: Add missing componentsMichael Kubacki2020-03-251-0/+5
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2574 The following components are currently missing from the [Components] section of ArmPkg.dsc: * ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf * ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf * ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf * ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf This commit includes the components in the package DSC build. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmLib: Fix cache-invalidate initial page tablesAshish Singhal2020-03-191-1/+1
| | | | | | | | Because of a bug, current EL gets passed to DC IVAC instruction instead of the VA entry that needs to be invalidated. Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib AARCH64: cosmetic fixupsArd Biesheuvel2020-03-101-19/+37
| | | | | | | | | | | Some cosmetic fixups to the AArch64 MMU code: - reflow overly long lines unless it hurts legibility - add/remove whitespace according to the [de facto] coding style - use camel case for goto labels Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-Id: <20200307091008.14918-3-ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib AARCH64: drop pointless page table memory type checkArd Biesheuvel2020-03-101-15/+0
| | | | | | | | | | | This is the AARCH64 counterpart of commit 1f3b1eb3082206e4, to remove a pointless check against the memory type of the allocations that the page tables happened to land in. On ArmV8, we use writeback cacheable exclusively for all memory. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-Id: <20200307091008.14918-2-ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating themArd Biesheuvel2020-03-101-0/+14
| | | | | | | | | | | | As it turns out, ARMv8 also permits accesses made with the MMU and caches off to hit in the caches, so to ensure that any modifications we make before enabling the MMU are visible afterwards as well, we should invalidate page tables right after allocation like we do now on ARM, if the MMU is still disabled at that point. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Message-Id: <20200307083849.8940-3-ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib AARCH64: rewrite page table codeArd Biesheuvel2020-03-101-238/+143
| | | | | | | | | | | | | | Replace the slightly overcomplicated page table management code with a simplified, recursive implementation that should be far easier to reason about. Note that, as a side effect, this extends the per-entry cache invalidation that we do on page table entries to block and page entries, whereas the previous change inadvertently only affected the creation of table entries. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-Id: <20200307083849.8940-2-ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib ARM: drop memory type check for page tablesArd Biesheuvel2020-03-051-18/+2
| | | | | | | | | | We already expect normal memory to be mapped writeback cacheable if EDK2 itself is to make use of it, so doing an early sanity check on the memory type of the allocation that the page tables happened to land in isn't very useful. So let's drop it. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib ARM: simplify assignment of TTBR0 system registerArd Biesheuvel2020-03-051-1/+1
| | | | | | | | | | | | | | | The expression passed into ArmSetTTBR0 () in ArmConfigureMmu() is sub-optimal at several levels: - TranslationTable is already aligned, and if it wasn't, doing it here wouldn't help - TTBRAttributes is guaranteed not to have any bits set outside of the 0x7f mask, so the mask operation is pointless as well, - an additional (UINTN) cast for good measure is also not needed. So simplify the expression. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: ASSERT on set/way cache ops being used with MMU onArd Biesheuvel2020-03-053-0/+17
| | | | | | | | | | | On ARMv7 and up, doing cache maintenance by set/way is only permitted in the context of on/offlining a core, and any other uses should be avoided. Add ASSERT()s in the right place to ensure that any uses with the MMU enabled are caught in DEBUG builds. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: remove bogus protocol declarationArd Biesheuvel2020-03-051-3/+0
| | | | | | | | | ArmLib is a BASE type library, which should not depend or even be aware on DXE type protocols. So drop the reference to gEfiCpuArchProtocolGuid. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: clean up library includesArd Biesheuvel2020-03-053-10/+11
| | | | | | | | | | | | Suspiciously, ArmLib's INF does not contain a [LibraryClasses] section at all, but it turns out that all the library includes it contains (except for ArmLib.h itself) are actually bogus so let's just drop all of them. While at it, replace <Uefi.h> with the more accurate <Base.h> for a BASE type module, and put the includes in a consistent order. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: move set/way helper functions into private headerArd Biesheuvel2020-03-053-18/+36
| | | | | | | | | | | | | The clean/invalidate helper functions that operate on a single cache line identified by set, way and level in a special, architected format are only used by the implementations of the clean/invalidate routines that operate on the entire cache hierarchy, as exposed by ArmLib. The latter routines will be deprecated soon, so move the helpers out of ArmLib.h and into a private header so they are safe from abuse. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib AARCH64: cache-invalidate initial page table entriesArd Biesheuvel2020-03-052-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the AARCH64 version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, update ArmUpdateTranslationTableEntry () to invalidate each page table entry *after* it is written if the MMU is still disabled at this point. On ARMv8, it is guaranteed that memory accesses done by the page table walker are cache coherent, and so we can ignore the case where the MMU is on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib ARM: cache-invalidate initial page table entriesArd Biesheuvel2020-03-051-14/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, invalidate each page table right after allocating it, and each section entry after it is updated (to address all the little corner cases that the ARMv7 spec permits), and invalidate sets of level 2 entries in blocks, using the generic invalidation routine from CacheMaintenanceLib On ARMv7, cache maintenance may be required also when the MMU is enabled, in case the page table walker is not cache coherent. However, the code being updated here is guaranteed to run only when the MMU is still off, and so we can disregard the case when the MMU and caches are on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib ARM: use AllocateAlignedPages() for alignmentArd Biesheuvel2020-03-051-9/+10
| | | | | | | | | | | | Instead of overallocating memory and align the resulting base address manually, use the AllocateAlignedPages () helper, which achieves the same, and might even manage that without leaking a chunk of memory of the same size as the allocation itself. While at it, fix up a variable declaration in the same hunk, and drop a comment whose contents add nothing to the following line of code. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: split ArmMmuLibCore.c into core and update codeArd Biesheuvel2020-03-054-434/+469
| | | | | | | | | | | | | | | | | | | Unlike the AArch64 implementation of ArmMmuLib, which combines the initial page table population code with the code that runs at later stages to manage permission attributes in the page tables, ARM uses two completely separate sets of routines for this. Since ArmMmuLib is a static library, we can prevent duplication of this code between different users, which usually only need one or the other. (Note that LTO should also achieve the same.) This also makes it easier to reason about modifying the cache maintenance handling, and replace the set/way ops with by-VA ops, since the code that performs the set/way ops only executes when the MMU is still off. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmMmuLib ARM: remove dummy constructorArd Biesheuvel2020-03-052-9/+2
| | | | | | | | Make the CONSTRUCTOR define in the .INF AARCH64 only, so we can drop the empty stub that exists for ARM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/MmCommunicationDxe: fix logic bug in DXE driver entrypointArd Biesheuvel2020-03-041-0/+8
| | | | | | | | | | | | | | | Commit 2fe25a74d6fee3c2 ("ArmPkg/MmCommunicationDxe: relay architected PI events to MM context") update the ARM specific standalone MM client driver to register for certain events in the entrypoint code, but did so in a way that makes the entrypoint always return with an error. Instead, return EFI_SUCCESS if registering for those events succeeds, and back out the registrations that did succeed if one fails, and return an error. Fixes: 2fe25a74d6fee3c2 ("ArmPkg/MmCommunicationDxe: relay architected PI events to MM context") Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: convert LFs to CRLF, expand hard TABsLaszlo Ersek2020-03-045-430/+430
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're going to switch the internal line terminators globally to LF at some point, but until then, let's use CRLF consistently. Convert source files with LFs in them to CRLF, using "unix2dos". "git show -b" prints no code changes for this patch. (I collected all the file name suffixes in this package, with: $ git ls-files -- $PACKAGE | rev | cut -f 1 -d . | sort -u | rev I eliminated those suffixes that didn't stand for text files, then blanket-converted the rest with unix2dos. Finally, picked up the actual changes with git-add.) At the same time, the following three files had to undergo TAB expansion: ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c ArmPkg/Library/GccLto/liblto-aarch64.s ArmPkg/Library/GccLto/liblto-arm.s I used "expand -t 2", in order to stay close to the edk2 coding style (which uses two spaces for indentation.) Both the CRLF conversion and the TAB expansion are motivated by "PatchCheck.py". "PatchCheck.py" is also the reason why CRLF conversion and TAB expansion have to happen in the same patch. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1659 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20200227213903.13884-2-lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* ArmPkg/ArmSmcPsciResetSystemLib: remove EnterS3WithImmediateWake ()Ard Biesheuvel2020-01-147-201/+0
| | | | | | | | | | | | EnterS3WithImmediateWake () no longer has any callers, so remove it from ResetSystemLib. Note that this means the hack to support warm reboot by jumping to the SEC entry point with the MMU and caches off is also no longer used, and can be removed as well, along with the PCD PcdArmReenterPeiForCapsuleWarmReboot that was introduced for this purpose. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/MmCommunicationDxe: relay architected PI events to MM contextArd Biesheuvel2019-12-112-2/+50
| | | | | | | | | | PI defines a few architected events that have significance in the MM context as well as in the non-secure DXE context. So register notify handlers for these events, and relay them into the standalone MM world. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* ArmPkg: Dispatch deferred images after EndOfDxeSami Mujawar2019-12-051-1/+6
| | | | | | | | | | | | | | Third party driver images loaded from Option ROM get queued for execution after EndOfDxe. These queued images need to be dispatched from the PlatformBootManagerLib. Since the queued images were not dispatched, the PCI Option ROM drivers were not getting loaded on Juno. Therefore, add call to EfiBootManagerDispatchDeferredImages() for dispatching deferred images from PlatformBootManagerLib. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: strip trailing whitespaceLeif Lindholm2019-10-041-2/+2
| | | | | | | Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* ArmPkg: ArmScmiDxe - convert .h to from 8859-x to 7-bitLeif Lindholm2019-10-041-1/+1
| | | | | | | | | | | | A paragraph sign in a comment came from some ISO8859 encoding, convert it to the word "section" to remain 7-bit safe, since we're not actually doing anything special. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 20:21:31 +0000