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* ArmPkg/ArmCacheMaintenanceLib: Fixed comment (and coding style)Olivier Martin2014-07-011-4/+3
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15608 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe/ArmV6: Return error status when ExceptionHandlersStart is not ↵Olivier Martin2014-07-011-2/+6
| | | | | | | | | | | | | 32-byte aligned The function should detect and return the error in non-debug builds when the ASSERT does nothing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15606 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Fixed missing braces (the warning was disabled by GCC)Olivier Martin2014-06-202-11/+11
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15578 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AsmMacroIoLib: Add support for ARM Compiler 6.00Olivier Martin2014-06-031-52/+27
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15554 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt ↵Olivier Martin2014-06-034-14/+28
| | | | | | | | | | | | | | | handling See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in "Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions" Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Added new ARM Processor Feature Register definitionsOlivier Martin2014-06-033-3/+9
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15552 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Drain Write Buffer before DCache maintenance operations.Olivier Martin2014-06-033-1/+12
| | | | | | | | | | | | | | | | Cache maintenance operations by Set/Way require that the Write Buffer be drained before the cache is flushed. Without that, the flush can miss the most recent values written as they are still "pipelined". That has unfortunate consequences, especially where code is being copied to RAM. The fix is to add DSB instructions before the affected operations. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/DefaultExceptionHandlerLib/Aarch64: Added friendly debug messageOlivier Martin2014-06-031-4/+79
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15549 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Added support for TFTP servers without 'tsize' extensionOlivier Martin2014-05-193-29/+75
| | | | | | | | | | | | | Some TFTP servers do not have 'tsize' extension. This change allows to download files from TFTP servers that do not have this extension by trying to download the file into a pre-allocated buffer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15539 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib/AArch64: Added more useful error messages when loading LinuxBrendan Jackman2014-05-141-4/+4
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <Brendan.JackMan@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15528 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Fix allocating kernel buffer in TFTPBrendan Jackman2014-05-141-8/+11
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <Brendan.JackMan@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15527 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-levelOlivier Martin2014-05-141-2/+1
| | | | | | | | | | | | | | | If the first entry of the memory map is in the third level (case when the region at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3 (=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3). The first condition in GetFirstPageAttribute() needed the table level to not mix these two descriptor types. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Fix booting with partial pathsMark Salter2014-05-081-27/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | Boot entries created by efibootmgr may contain a partial device path to the EFI application to boot. These entries begin with a partition device path whereas entries created via ARM Boot Manager contain a full path to the EFI application. The ARM BDS code will fill in the missing parts of this partial device path as it does for removeable device paths. This allows the application to be loaded and started. However, the current code passes the original partial device path to gBS->LoadImage() and thus LoadImage is unable to find a DeviceHandle for the path. This means the application being booted cannot find the boot device from the Loaded Image Protocol structure. In the case of grub, this prevents the grub config file from being found. This patch fixes this by making sure the full path is propagated back to the caller of gBS->LoadImage() so that a proper DeviceHandle gets passed to the application being booted. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15518 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Use .8byte instead of .dword for pointersBrendan Jackman2014-05-081-1/+1
| | | | | | | | | | | | Clang doesn't recognise .dword Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15510 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Use AND instead of BIC instruction with immediateBrendan Jackman2014-05-081-7/+6
| | | | | | | | | | | | | | AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a AND with the immediate inverted, but Clang's integrated assembler emits an error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe/AArch64: use STUR instruction for signed offsetBrendan Jackman2014-05-081-4/+4
| | | | | | | | | | | | | | | The AARCH64 LDR and STR instructions only support signed offsets for post- and pre-indexed addressing. For normal signed offset addressing, the mnemonic is STUR. GNU As automatically assembles STR with signed offset as STUR, but Clang's integrated assembler doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15508 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe/AArch64/ExceptionSupport.S: Fix immediate syntaxBrendan Jackman2014-05-081-13/+13
| | | | | | | | | | | | GNU as assembles instructions without the '#' before immediates. Clang doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15507 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: use GCC_ASM_EXPORT to export functionsBrendan Jackman2014-05-084-27/+27
| | | | | | | | | | | | This ensures the .type directive is used to mark them as function symbols Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
* ArmLib/AArch64Support.S: remove export of unimplemented functionBrendan Jackman2014-05-081-1/+0
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15505 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Remove GCC filter for AARCH64 assembly filesBrendan Jackman2014-05-0811-20/+20
| | | | | | | | | | | | Some non-GCC toolchain might support the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Fixed AArch64 MMU code when a region overlaps 2 level-3 page ↵Olivier Martin2014-04-241-3/+10
| | | | | | | | | | | tables Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15483 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Restore AArch64 system registers before returning from exceptionoliviermartin2014-04-231-2/+19
| | | | | | | | | | | | | Current EDK2 source code does actually trigger nested interrupted (even if the PI spec says interrupt should not be nested). This issue has highlighted the lack of restoring ELR_EL2/ELR_EL1 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15481 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Fixed GetEnvironmentVariable() when the UEFI Variable did not existOlivier Martin2014-04-022-2/+36
| | | | | | | | | | | | | | | The function was allocating a buffer for the read value from the UEFI Variable. But it was returning the pointer of the default value when the variable was not present. It could cause error when the default value and the returned value were free when these addresses were the same (double FreePool on the same address). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15427 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmCpuLib: Added A57 Errata 806969Olivier Martin2014-03-261-0/+8
| | | | | | | | | | | This rare errata only affects r0p0 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15400 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Correct Error Handling in AArch64Olivier Martin2014-03-261-6/+22
| | | | | | | | | | | | | | | There are several instances of asserts which do not also handle the error condition in Release builds. Because these functions are called in different location of the code and their parameters might change during the execution, it is safer to handle the error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15399 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmCortexA5xLib: Fixed setting of SMP bitOlivier Martin2014-03-261-2/+2
| | | | | | | | | | | On CortexA5x the SMP bit is BIT6 of CPUECTLR_EL1 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15398 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmCortexA5x: Declared the helper functions to access the CPU ↵Olivier Martin2014-03-265-14/+88
| | | | | | | | | | | | | | Extended Control Register This register is A5x specific. It is the reason why the code moved from ArmLib to ArmCpuLib/ArmCortexA5xLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15397 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Added helper functions for accessing CPU ACTLROlivier Martin2014-03-265-5/+109
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15396 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Chipset: Added ARMv8 CPU's PartNumOlivier Martin2014-03-262-3/+13
| | | | | | | | | | | PartNum is the field of MIDR that returns the CPU name. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15395 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/SemihostFs: Various fixes for the file systemHarry Liebel2014-03-252-9/+22
| | | | | | | | | | | | | - Fix file deletion from the shell. - Fix file creation using the shell editor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15390 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/SemihostLib: Made arguments 'native' sizeHarry Liebel2014-03-251-8/+9
| | | | | | | | | | | | | The arguments passed to the semi-hosing backend should be of 'native' size to match register widths. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15389 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CompilerIntrinsicsLib: Added memset() to AArch64Olivier Martin2014-03-242-0/+26
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15384 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Removed unused AArch64 filesOlivier Martin2014-03-244-139/+6
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15382 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Renamed Cp15CacheInfo into ArmCacheInfoOlivier Martin2014-03-244-17/+18
| | | | | | | | | | | | | CTR (Cache Type Register) has the same format on ARMv7 and AArch64. Renaming Cp15CacheInfo() into ArmCacheInfo() makes this function architecture independent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15381 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Removed unused ArmSwitchProcessorMode & ArmProcessorMode ↵Olivier Martin2014-03-242-31/+0
| | | | | | | | | | | functions Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15380 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Removed unused header files from source filesOlivier Martin2014-03-241-3/+0
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15379 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Fix typo in comment and trailing spacesOlivier Martin2014-03-241-15/+15
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15378 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Tidy assembler codeOlivier Martin2014-03-014-13/+10
| | | | | | | | | | | | - Fixed typo - Removed unreachable 'dead' loop Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15277 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Rationalise ArmReadMidr and cognate functions.Olivier Martin2014-03-018-34/+9
| | | | | | | | | | | | | The function ArmReadMidr has been recently added, but that functionality was already present under other names such as Cp15IdCode and ArmMainIdCode. This change removes redundant code and moves the function to the Common library. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15276 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Fix compilation error with -O3 switchOlivier Martin2014-03-011-17/+17
| | | | | | | | | | | | A warning is reported because ArmArchTimerReadReg may theoretically result in an unititialised value. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15275 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: ArmReadVBar implementation missing in AArch64Olivier Martin2014-03-011-0/+11
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15274 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Replace single dead loop.Olivier Martin2014-03-013-18/+13
| | | | | | | | | | | | | | Several assembler macros use a loop at the label "dead" to trap an error. This is difficult to debug as there is no indication of how one arrived at the loop. This change replaces dead with distinct loops locally in the macro, which means the cause of the hang is detectable to the debugger. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15273 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Move common definitions from ArmV7Lib.h & AArch64Lib.h to ↵Olivier Martin2014-03-013-107/+43
| | | | | | | | | | | ArmLib.h Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15272 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AsmMacroIoLibV8.h: Correct 32 bit accesses in asm macrosOlivier Martin2014-02-241-85/+20
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15257 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Include 'AsmMacroIoLibV8.h' instead of the 32bit versionOlivier Martin2014-02-241-2/+2
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15256 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Support ignoring EfiReservedMemoryType when updating the FDT.Garrett Kirkendall2014-02-241-1/+2
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15255 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: CRLF fixupLeif Lindholm2014-02-121-4/+4
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15241 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Added ArmReadMidr()Olivier Martin2014-02-125-4/+29
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15240 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Removed unused MachineType argument (AArch64)Olivier Martin2014-02-121-5/+2
| | | | | | | | | | | MachineType was used on 32-bit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15239 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Removed unused header 'BdsUnixLib.h'Olivier Martin2014-02-121-38/+0
| | | | | | | | | | | This header contains a function that does not exist. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15238 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-09 06:23:34 +0000