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* ArmPlatformPkg/Bds: Remove any use of the "Fdt" UEFI variableRonald Cron2015-02-2615-121/+20
| | | | | | | | | | | | | | | | Remove the option to update the "Fdt" UEFI variable in the ARM BDS as the "setfdt" EFI Shell command provides this service from now. Remove the use of this variable in the legacy kernel boot loader and use the FDT installed in the configuration table instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16940 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoDxe: Set the platform dependent FDT device pathRonald Cron2015-02-266-24/+83
| | | | | | | | | | | | | | | The MIDR register of the CPU on which the UEFI firmware is running on is used to infer if the platform is a Juno r0 or a Juno r1. The right device path to the platform FDT is then stored in the "gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths" dynamic PCD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16939 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg : Use FdtPlatformDxe driver to install the FDTRonald Cron2015-02-2611-503/+31
| | | | | | | | | | | | | | Remove the installation of the FDT for Juno into the UEFI Configuration Table from the Juno specific DXE driver. Use the FdtPlatformDxe driver to do it instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16938 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpressDxe: Load FDT into the EFI Configuration TableRonald Cron2015-02-2629-55/+340
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16937 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpressPkg: Added support to differentiate ARMv8 FVP variantsOlivier Martin2015-02-255-20/+75
| | | | | | | | | | | | | | | | There are three FVP variants for the Base and Foundation models: - model with GICv2 legacy memory map (same location as the Versatile Express model) - model with GICv2 and Base model memory map - model with GICv3 and Base model memory map The new code detects the variants to load the appropriate device tree. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16932 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpressDxe: Identify the current platformOlivier Martin2015-02-2511-18/+365
| | | | | | | | | | | | Add a function to ArmVExpressDxe to identify the current platform we are running on. This includes ARM32 and AArch64 models and hardware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16931 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpress-FVP-AArch64.dsc: Switch to Linux kernel with EFI ↵Olivier Martin2015-02-251-3/+3
| | | | | | | | | | | stub by default Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16929 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJuno: Use EFI Stub and updated the command lineOlivier Martin2015-02-251-2/+4
| | | | | | | | | | | | | | - 'earlycon' is the new name for 'earlyprintk' - Support Linux EFI stub by default - The command line is expected to be in unicode when booting an EFI application. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16928 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/QemuFwCfgLib: Fixed build errorOlivier Martin2015-02-251-1/+1
| | | | | | | | | | | | ARM toolchain raises the build error: Error #188-D: enumerated type mixed with another type Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16927 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: PlatformIntelBdsLib: display TianoCore logoLaszlo Ersek2015-02-253-0/+15
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16925 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: PlatformIntelBdsLib: detect consoles dynamicallyLaszlo Ersek2015-02-252-0/+354
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect the video displays dynamically, and add them to the console and error output variables. Add a short-form, "wild card" USB_CLASS_DEVICE_PATH to the console input variable, which causes the USB keyboard to be handled automatically. Add the fixed location serial console to all of the console input, console output, and error output variables. This patch enables QEMU users to drop "addr=..." PCI address specifications from the -device options (or to use whatever addresses they like). For example, the following works: -device VGA \ \ -device ich9-usb-ehci1,multifunction=on,id=ehci \ -device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0 \ -device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2 \ -device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4 \ -device usb-kbd,bus=ehci.0 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16924 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: PlatformIntelBdsLib: remove ties to ARM BDSLaszlo Ersek2015-02-254-202/+6
| | | | | | | | | | | | | | | | | | | | | | | In this patch we remove all dependencies on ARM BDS libraries. We also remove empty and/or unneeded functions, includes, etc. PlatformIntelBdsLib "goes back to basics" temporarily -- there are no consoles configured, and it's practically not possible to interact with the user interface. Bisection remains available in the sense that "ArmVirtualizationQemu.dsc" continues to build and should boot preexistent boot options, but user interaction does regress temporarily. The reason for this is that it's preferable to keep this patch and the next one separate for readability's sake -- they amount to a rewrite from scratch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16923 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: PlatformIntelBdsLib: beautify sourceLaszlo Ersek2015-02-253-31/+33
| | | | | | | | | | | | This patch introduces no functional changes. It sorts #include directives, sorts INF file sections, and reformats license blocks. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16922 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/ArmVirtualizationQemu: add USB keyboard inputLaszlo Ersek2015-02-233-2/+33
| | | | | | | | | | | Similarly to the previous patch, we can now multiplex input from the USB keyboard. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16914 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/ArmVirtualizationQemu: add VGA console outputLaszlo Ersek2015-02-232-2/+32
| | | | | | | | | | | | | | | | | | | Alex Graf's QEMU patchset enables "-device VGA" for the virt machtype as well. We can now include OvmfPkg/QemuVideoDxe in the firmware, and set PcdDefaultConOutPaths such that the console output is multiplexed to the video window as well. (Our platform BDS lib doesn't (yet) locate the VGA device automatically.) OvmfPkg/PlatformDxe is included too; it allows users to select a video resolution. (Note that PcdSetupVideoHorizontalResolution and PcdSetupVideoVerticalResolution are independent; see git commit 848834cb (SVN r16311) for explanation.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16913 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: PlatformIntelBdsLib: fix multiconsole setupLaszlo Ersek2015-02-231-98/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the following call chain: PlatformBdsPolicyBehavior() PlatformBdsConnectConsole() InitializeConsolePipe() x 3 BdsConnectDevicePath() [ArmPkg/Library/BdsLib/BdsFilePath.c] the three InitializeConsolePipe() function calls pass through - (&gST->ConsoleOutHandle, &gST->ConOut), - (&gST->ConsoleInHandle, &gST->ConIn), - (&gST->StandardErrorHandle, &gST->StdErr) to BdsConnectDevicePath(), in ArmPkg's BdsLib. At least when more than one console device paths are specified in the ConIn / ConOut / ErrOut variables, the above resuls in: - unchanged protocol interfaces (ConOut, ConIn, StdErr) in the system table (because ConSplitterDxe installs its non-NULL interfaces first), - but, changed handles in the system table. This effectively separates the handle fields in the system table from the protocol interfaces in the same that should always be associated with the handles. The end result is that clients using the handles break (splitting / multiplexing doesn't work for them), while clients directly using the protocol interfaces work. Therefore, do not attempt to connect consoles separately. ConSplitterDxe is dispatched before PlatformBdsPolicyBehavior() is called (the latter happens in the BDS phase), and ConSplitterDxe installs virtual handles and protocol interfaces for input / output / error. BdsLibConnectAll() covers all devices, including consoles; as those consoles are connected, ConPlatformDxe and ConSplitterDxe pick them up nicely as "slaves". We just need to make sure that the variables are set first, for the variables -> ConPlatformDxe -> ConSplitterDxe dependency chain. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16912 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: PlatformIntelBdsLib: kernel boot should provide ACPILaszlo Ersek2015-02-231-3/+6
| | | | | | | | | | | | If there is a PCI host, then PCI enumeration (which happens inside BdsLibConnectAll()) blocks ACPI table installation (correctly). Make sure we install ACPI tables before trying to direct-boot a QEMU kernel. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16911 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/ArmVirtualizationQemu: enable PCI supportLaszlo Ersek2015-02-233-1/+19
| | | | | | | | | | | | Beyond including the foundational drivers in the DSC and FDF files, we enable virtio-over-PCI, and turn on QemuBootOrderLib's OFW-to-UEFI device path translation for PCI devices. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16910 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: clone BasePciExpressLib, cache PCIe config baseLaszlo Ersek2015-02-232-0/+1475
| | | | | | | | | | | | | | | | | | | | | | | | The BarExisted() function in "MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c" raises the TPL to TPL_HIGH_LEVEL before accessing PCI config space. The PciExpressLib instance under "MdePkg/Library/BasePciExpressLib" -- serving the PCI config space access -- calls PcdGet64(PcdPciExpressBaseAddress) in turn, for each such call. The PcdGet64() function, when issued at TPL_HIGH_LEVEL, triggers an ASSERT(). PcdGet64() is based on a protocol in this UEFI phase, and protocol handler services are not allowed above TPL_NOTIFY (see Table 23 "TPL Restrictions" in the UEFI spec). Clone the library, and in a new constructor, cache the PCD in a global variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16909 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: handle 0 in GetProposedResources()Laszlo Ersek2015-02-231-1/+9
| | | | | | | | | | | | | | | | | When there are no devices connected to the root bridge, no resources are needed. GetProposedResources() currently considers this an invalid condition (the PI spec doesn't regulate it). Emitting an empty set of EFI_ACPI_ADDRESS_SPACE_DESCRIPTORs, followed by the required EFI_ACPI_END_TAG_DESCRIPTOR, allows PciHostBridgeResourceAllocator() [MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c] to advance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16908 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: skip 0 AddrLen in SubmitResources()Laszlo Ersek2015-02-231-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Volume 5 of the PI spec, 10.8.2 PCI Host Bridge Resource Allocation Protocol, SubmitResources(), It is considered an error if no resource requests are submitted for a PCI root bridge. If a PCI root bridge does not require any resources, a zero-length resource request must explicitly be submitted. Under MdeModulePkg/Bus/Pci/PciBusDxe/, we have: PciHostBridgeResourceAllocator() [PciLib.c] ConstructAcpiResourceRequestor(..., &AcpiConfig) [PciEnumerator.c] PciResAlloc->SubmitResources(..., &AcpiConfig) ASSERT_EFI_ERROR () If ConstructAcpiResourceRequestor() finds no resources to request (for example because no PCI devices are on the root bridge), it places a zero-length EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR followed by an EFI_ACPI_END_TAG_DESCRIPTOR in "AcpiConfig"; satisfying the PI spec. However, PciHostBridgeDxe's SubmitResources() function does not expect such input; the following part of the code rejects it: switch (Ptr->ResType) { case 0: // // Check invalid Address Sapce Granularity // if (Ptr->AddrSpaceGranularity != 32) { return EFI_INVALID_PARAMETER; } Skip EFI_ACPI_ADDRESS_SPACE_DESCRIPTORs with zero AddrLen early. Also, allow PciHostBridgeResourceAllocator() to proceed to the AllocateResources phase by setting "ResourceSubmited" to TRUE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16907 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: get MMIO BARs from our own apertureLaszlo Ersek2015-02-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is our MMIO space map: > GCD:AddMemorySpace(Base=0000000010000000,Length=000000002EFF0000) > GcdMemoryType = MMIO > Capabilities = 0000000000000001 > Status = Success > GCDMemType Range Capabilities Attributes > ========== ================================= ================ ================ > NonExist 0000000000000000-0000000003FFFFFF 0000000000000000 0000000000000000 > MMIO 0000000004000000-0000000007FFFFFF C000000000000001 8000000000000001 NorFlashDxe adds this, but does not allocate it. > NonExist 0000000008000000-000000000900FFFF 0000000000000000 0000000000000000 > MMIO 0000000009010000-0000000009010FFF C000000000000001 8000000000000001 Added by RealTimeClockRuntimeDxe, but also not allocated. > NonExist 0000000009011000-000000000FFFFFFF 0000000000000000 0000000000000000 > MMIO 0000000010000000-000000003EFEFFFF C000000000000001 0000000000000000 Added by ourselves. > NonExist 000000003EFF0000-000000003FFFFFFF 0000000000000000 0000000000000000 > SystemMem 0000000040000000-00000000BFFFFFFF 800000000000000F 0000000000000008* > NonExist 00000000C0000000-0000FFFFFFFFFFFF 0000000000000000 0000000000000000 In the EfiPciHostBridgeAllocateResources phase, we allocate memory BARs bottom up, from whichever MMIO range comes first and has room left. Unfortunately, this places memory BARs into MMIO ranges that belong to other devices. (Arguably, their respective drivers should not just add, but immediately allocate those ranges as well.) ( This problem is not seen in OVMF / PcAtChipsetPkg, because there we allocate bottom-up from the range [max(2GB, top-of-low-RAM), 0xFC000000). (See the MMIO resource descriptor HOB created in MemMapInitialization() [OvmfPkg/PlatformPei/Platform.c].) That MMIO range fits in the static [2GB, 4GB) aperture given in "mResAperture" in PcAtChipsetPkg/PciHostBridgeDxe; plus other MMIO ranges (IO-APIC, HPET, LAPIC, flash chip) are higher than 0xFC000000. Hence the bottom-up BAR allocation in OvmfPkg always finds the right MMIO range first. ) In ArmVirtualizationPkg/PciHostBridgeDxe we can solve the problem by working our way downwards from the top of our own aperture. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16906 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: allocate IO BARs top-downLaszlo Ersek2015-02-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we allocate IO BARs bottom-up in the EfiPciHostBridgeAllocateResources phase of the enumeration. > GCD:AddIoSpace(Base=0000000000000000,Length=0000000000010000) > GcdIoType = I/O > Status = Success > GCDIoType Range > ========== ================================= > I/O 0000000000000000-000000000000FFFF Because the IO aperture is based at zero, the first allocation happens to get the zero address. However, a zero address for a PCI BAR is considered unmapped; see eg.: - <http://www.pcisig.com/reflector/msg00459.html>, - the (new_addr == 0) part in QEMU, pci_bar_address() [hw/pci/pci.c]: new_addr = pci_get_long(d->config + bar) & ~(size - 1); last_addr = new_addr + size - 1; /* Check if 32 bit BAR wraps around explicitly. * TODO: make priorities correct and remove this work around. */ if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) { return PCI_BAR_UNMAPPED; } We can avoid this problem by allocating top-down in the IO aperture. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16905 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: MMIO aperture must not be uncachedLaszlo Ersek2015-02-234-2/+50
| | | | | | | | | | | | | | | | | | | | | Quite non-intuitively, we must allow guest-side writes to emulated PCI MMIO regions to go through the CPU cache, otherwise QEMU, whose accesses always go through the cache, may see stale data in the region. This change makes no difference for QEMU/TCG, but it is important for QEMU/KVM, at the moment. Because gDS->SetMemorySpaceAttributes() is ultimately implemented by EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() -- see "MdeModulePkg/Core/Dxe/Gcd/Gcd.c" and "ArmPkg/Drivers/CpuDxe/" -- we add the CPU architectural protocol to the module's DepEx. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16904 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: add room for PCI resource allocationLaszlo Ersek2015-02-231-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VirtFdtDxe parses the following address space properties from the DTB (and saves them in PCDs) : ProcessPciHost: Config[0x3F000000+0x1000000) Bus[0x0..0xF] Io[0x0+0x10000)@0x3EFF0000 Mem[0x10000000+0x2EFF0000)@0x0 In order to allow PCI enumeration to allocate IO and MMIO resources from the above ranges for devices, we must add the ranges to the Global Coherency Domain. There are two ways for that: - building resource descriptor HOBs in the HOB producer phase (basically, PEI), and letting the DXE core process them, - calling gDS->AddIoSpace() and gDS->AddMemorySpace() during DXE. We opt for the second method for simplicity. In the address space maps, the corresponding ranges change from "nonexistent" to "IO" and "MMIO", from which the gDS->AllocateIoSpace() and gDS->AllocateMemorySpace() services can later allocate PCI BARs. GCD:AddIoSpace(Base=0000000000000000,Length=0000000000010000) GcdIoType = I/O Status = Success GCDIoType Range ========== ================================= -> I/O 0000000000000000-000000000000FFFF GCD:AddMemorySpace(Base=0000000010000000,Length=000000002EFF0000) GcdMemoryType = MMIO Capabilities = 0000000000000001 Status = Success GCDMemType Range Capabilities Attributes ========== ================================= ================ ================ NonExist 0000000000000000-0000000003FFFFFF 0000000000000000 0000000000000000 MMIO 0000000004000000-0000000007FFFFFF C000000000000001 8000000000000001 NonExist 0000000008000000-000000000900FFFF 0000000000000000 0000000000000000 MMIO 0000000009010000-0000000009010FFF C000000000000001 8000000000000001 NonExist 0000000009011000-000000000FFFFFFF 0000000000000000 0000000000000000 -> MMIO 0000000010000000-000000003EFEFFFF C000000000000001 0000000000000000 NonExist 000000003EFF0000-000000003FFFFFFF 0000000000000000 0000000000000000 SystemMem 0000000040000000-00000000BFFFFFFF 800000000000000F 0000000000000008* NonExist 00000000C0000000-0000FFFFFFFFFFFF 0000000000000000 0000000000000000 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16903 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/ArmVirtualizationQemu: enable IO addressingLaszlo Ersek2015-02-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Set gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize to 16, which determines the maximum "I/O address width". This ensures, through the BuildCpuHob() call in "ArmPkg/Drivers/CpuPei/CpuPei.c", that the inital I/O Space Map will consist of a 16-bit wide "splittable" entry, when the DXE core starts (see CoreInitializeGcdServices() in "MdeModulePkg/Core/Dxe/Gcd/Gcd.c"): GCD:Initial GCD I/O Space Map GCDIoType Range ========== ================================= NonExist 0000000000000000-000000000000FFFF Otherwise this range would have size 0, and (since it could not be split) any gDS->AddIoSpace() calls would fail. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16902 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: accommodate general address spacesLaszlo Ersek2015-02-231-13/+22
| | | | | | | | | | | | The RootBridgeIoCheckParameter() function currently relies on the range limit being of the form (2^n - 1). This assumption is not necessarily true; handle the general case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16901 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: IO space is emulated with MMIOLaszlo Ersek2015-02-231-6/+6
| | | | | | | | | | | | | | | There is no IO space on ARM, and there are no special instructions that access it. QEMU emulates the IO space for PCI devices with a special MMIO range. We're ready to use it at this point, we just have to switch the Io(Read|Write)(8|16|32) primitives to their MMIO counterparts, because in "MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c", the IO primitives correctly ASSERT (FALSE). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16900 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: translate addresses for IOLaszlo Ersek2015-02-232-4/+17
| | | | | | | | | | | | Unlike the one in PcAtChipsetPkg, our PciHostBridgeDxe module must handle address space translation. IO addresses expressed in the respective aperture are mapped to a different base in CPU address space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16899 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: abort if there's no PCI host bridgeLaszlo Ersek2015-02-232-0/+7
| | | | | | | | | | | | | | | | If VirtFdtDxe found no PCI host in the DTB, then the config space base address will be left at zero -- the default is set in the DSC --, and we should exit PciHostBridgeDxe immediately. This causes gEfiPciRootBridgeIoProtocolGuid not to be installed, which in turn prevents MdeModulePkg/Bus/Pci/PciBusDxe from binding (see PciBusDriverBindingSupported()). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16898 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: set Root Bridge apertures from PCDsLaszlo Ersek2015-02-233-3/+26
| | | | | | | | | | | | | | | | Our PciHostBridgeDxe module creates one root bridge on the one and only host bridge. The resource apertures of the root bridge (bus range, IO space, MMIO space) are configured with the "mResAperture" array, which at the moment carries static values inherited from PcAtChipsetPkg. Set the array as first thing from the PCDs that we parsed from the device tree. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16897 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: ECAM enables 4KB config spaceLaszlo Ersek2015-02-231-1/+1
| | | | | | | | | | | | | | The Enhanced Configuration Access Mechanism provides access to 4096 register bytes per PCIe B/D/F. The MAX_PCI_REG_ADDRESS macro that we're changing here is used by RootBridgeIoCheckParameter() for verifying config space boundaries in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() and .Write(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.Martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16896 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/PciHostBridgeDxe: clone from PcAtChipsetPkgLaszlo Ersek2015-02-234-0/+3870
| | | | | | | | | | | | | | | | | | | | | | | MdeModulePkg/Bus/Pci/PciBusDxe depends on EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL and EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. Here we clone the driver that produces these from PcAtChipsetPkg, with the following immediate changes: - a new FILE_GUID is generated; - the assembly-language Ia32 / X64 specific IoFifo "accelerators" are not copied, and their client code (which would be dead code anyway) is removed; - UNI files are not copied: they are used in conjunction with the UEFI Packaging Tool (UPT), but the driver under ArmVirtualizationPkg will not be part of UDK. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16895 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg/VirtFdtDxe: parse "pci-host-ecam-generic" propertiesLaszlo Ersek2015-02-233-11/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Linux kernel tree, "Documentation/devicetree/bindings/pci/host-generic-pci.txt" describes the device tree bindings of a Generic PCI host controller. Recent QEMU patches from Alexander Graf implement such a controller on the "virt" machine type of qemu-system-(aarch64|arm): pcie@10000000 { // // (devfn<<8, 0, 0) PCI irq // ---------------- ------- interrupt-map-mask = <0x1800 0x0 0x0 0x7>; // gic irq // (devfn<<8, 0, 0) pin+1 phandle (type, nr, level) // ---------------- ----- -------- ----------------- interrupt-map = < 0x0 0x0 0x0 0x1 0x8001 0x0 0x3 0x4 0x0 0x0 0x0 0x2 0x8001 0x0 0x4 0x4 0x0 0x0 0x0 0x3 0x8001 0x0 0x5 0x4 0x0 0x0 0x0 0x4 0x8001 0x0 0x6 0x4 0x800 0x0 0x0 0x1 0x8001 0x0 0x4 0x4 0x800 0x0 0x0 0x2 0x8001 0x0 0x5 0x4 0x800 0x0 0x0 0x3 0x8001 0x0 0x6 0x4 0x800 0x0 0x0 0x4 0x8001 0x0 0x3 0x4 0x1000 0x0 0x0 0x1 0x8001 0x0 0x5 0x4 0x1000 0x0 0x0 0x2 0x8001 0x0 0x6 0x4 0x1000 0x0 0x0 0x3 0x8001 0x0 0x3 0x4 0x1000 0x0 0x0 0x4 0x8001 0x0 0x4 0x4 0x1800 0x0 0x0 0x1 0x8001 0x0 0x6 0x4 0x1800 0x0 0x0 0x2 0x8001 0x0 0x3 0x4 0x1800 0x0 0x0 0x3 0x8001 0x0 0x4 0x4 0x1800 0x0 0x0 0x4 0x8001 0x0 0x5 0x4>; #interrupt-cells = <0x1>; // // child base cpu base // type address address size // --------- -------------- -------------- -------------- ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>; // // PCIe config PCIe config // space base space size // -------------- ------------- reg = <0x0 0x3f000000 0x0 0x1000000>; // // allowed bus numbers; inclusive range // bus-range = <0x0 0xf>; #size-cells = <0x2>; #address-cells = <0x3>; device_type = "pci"; compatible = "pci-host-ecam-generic"; }; Parse those properties of the compatible="pci-host-ecam-generic" node into PCDs that are relevant for PCI enumeration in edk2: - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress controls MdePkg/Library/BasePciExpressLib, - gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration controls OvmfPkg/AcpiPlatformDxe at this point, - the rest have been introduced earlier in this patchset, and will control PCI range checks and translation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16894 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: introduce PCDs for describing PCI address spacesLaszlo Ersek2015-02-231-0/+62
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16893 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: Set PcdPciDisableBusEnumeration to TRUEJordan Justen2015-02-191-0/+4
| | | | | | | | | | | | This setting makes OvmfPkg/AcpiPlatformDxe not wait for PCI enumeration to complete before installing ACPI tables. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16886 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpress-FVP-AArch64.dsc: Fixed buildOlivier Martin2015-02-171-6/+6
| | | | | | | | | | | | The FeaturePcd gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy was not defined in the correct section. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16881 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpress-FVP-AArch64: Force GICv3 into GICv2 legacy modeOlivier Martin2015-02-161-0/+6
| | | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16876 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Added GICv3 specific definitionsOlivier Martin2015-02-161-1/+2
| | | | | | | | | | | | | | | | | | ARM GICv3 specification introduces some new components and registers. This patch adds their definitions. The most important GICv3 component is the GIC Redistributor. It supports LPIs (Locality-specific peripheral Interrupt), 8+ CPU configuration. Some GIC distributor registers have moved to the GIC redistributor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16872 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoDxe: Added missing headerOlivier Martin2015-02-041-2/+3
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16756 6f19259b-4bc3-4df7-8a09-765794883524
* */Contributions.txt: Update example email addressJordan Justen2015-02-031-2/+2
| | | | | | | | | | | | | Use the example.com domain as recommended in RFC 2606. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Bruce Cran <bruce.cran@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16724 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: add simple ACPI Platform Driver to the QEMU platformLaszlo Ersek2015-02-023-0/+13
| | | | | | | | | | | | | Introduce an ACPI platform driver for ARM / AARCH64 virtual machines. "OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpiPlatformDxe.inf" downloads ACPI blobs from QEMU over fw_cfg, processes them, and installs the resultant ACPI tables. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16698 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationQemu: ask the hardware for the timer frequencyLaszlo Ersek2015-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Roughly, there are two ways to "measure ticks" in UEFI: - the SetTimer() boot service, which sets up a one-shot or periodic event callback, and takes the interval length in units of 100ns, - the Stall() boot service, which stalls the caller (but does not yield the CPU) for the interval specified. The interval is taken as a number of microseconds. If the platform in question also follows the PI (Platform Init) specification, then it is recommended to implement the above UEFI services on top of the following DXE Architectural Protocols (described in PI Volume 2): - Timer Architectural Protocol: "Used to set up a periodic timer interrupt using a platform specific timer, and a processor-specific interrupt vector. This protocol enables the use of the SetTimer() Boot Service. [...]" - Metronome Architectural Protocol: "Used to wait for ticks from a known time source in a platform. This protocol may be used to implement a simple version of the Stall() Boot Service. [...]" Edk2 in general, and ArmVirtualizationQemu in particular, follow the above pattern. SetTimer() works correctly. The underlying Timer Architectural Protocol is provided by "ArmPkg/Drivers/TimerDxe", and that driver calls the internal function ArmGenericTimerGetTimerFreq() to retrieve the timer frequency. Ultimately it boils down to reading the CNTFRQ_EL0 register. The correct behavior of SetTimer() can be observed for example: - in the grub-efi countdown ("grub-core/kern/arm/efi/init.c"), - in the Intel BDS front page countdown ("IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c"). However, Stall() doesn't work correctly. The underlying Metronome Architectural Protocol is provided by "EmbeddedPkg/MetronomeDxe", which further delegates the job to the TimerLib library class. That in turn is resolved to the "ArmPkg/Library/ArmArchTimerLib" instance, which (finally!) takes the timer frequency from "PcdArmArchTimerFreqInHz". In ArmVirtualizationQemu we currently specify 100MHz for this PCD. Alas, that's incorect for: - both QEMU/TCG (which emulates 62.5MHz, see GTIMER_SCALE in "target-arm/internals.h"), - and KVM (where the host's virtualized timer can tick at 50 MHz, for example). Set the PCD to 0, asking ArmArchTimerLib to interrogate CNTFRQ_EL0 as well. The change can be tested with eg. the following callers of Stall(): - the UEFI Shell's countdown -- before it runs "startup.nsh" -- relies on Stall(), - the UEFI shell command "stall" also uses Stall(). (Time it with a stopwatch.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16692 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: detect correct pl011 fifo depthLeif Lindholm2015-01-232-2/+13
| | | | | | | | | | | | | | | | | pl011 releases earlier than r1p5 has a fifo depth of 16 bytes, whereas version r1p5 upwards has a fifo depth of 32 bytes. The pl011 driver was hardwired to 32 byte depth, causing dropped characters on some platforms (including default settings on FVP Base and Foundation models). Update driver to select 16 or 32 on port initialization by checking the component revision. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16656 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/NorFlashDxe : Fix the check of flash addressesRonald Cron2015-01-231-11/+2
| | | | | | | | | | | | Fix the check to prevent any reading past the end of the nor flash. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16655 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg/AcpiTables: Updated with new ACPI 5.1 Tables & ↵Olivier Martin2015-01-236-66/+197
| | | | | | | | | | | | Definitions Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16654 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg: Added the ACPI 5.0 TablesOlivier Martin2015-01-239-0/+556
| | | | | | | | | | | | | | | | | | These tables are: - Differentiated System Description Table Fields (DSDT) - Firmware ACPI Control Structure (FACS) - Fixed ACPI Description Table (FADT) - Generic Timer Description Table (GTDT) - Multiple APIC Description Table (MADT) - Secondary System Description Table Fields (SSDT) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16652 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg: Added ACPI supportOlivier Martin2015-01-235-0/+22
| | | | | | | | | | | | | This support makes the Juno UEFI Firmware to look into the Firmware Volume for the ACPI Tables. But it does not provide the ACPI Tables. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16651 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVirtualizationPkg: PlatformIntelBdsLib: get front page timeout from QEMULaszlo Ersek2015-01-142-19/+1
| | | | | | | | | | | | | | | | Put QemuBootOrderLib's GetFrontPageTimeoutFromQemu() to use, so that ArmVirtualizationPkg's Platform BDS policy can consume QEMU's command line option -boot menu=on,splash-time=N RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1172756 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16612 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Fixed builds after some ShellPkg libraries have movedOlivier Martin2015-01-133-9/+5
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16605 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 03:08:49 +0000