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* ArmPlatformPkg/ArmVExpressFastBootDxe: drop bogus gArmGlobalVariableGuid depArd Biesheuvel2015-11-271-3/+0
| | | | | | | | | | | ArmVExpressFastBootDxe does not use gArmGlobalVariableGuid so drop the declaration from the .inf. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19000 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoDxe: drop bogus gArmGlobalVariableGuid dependencyArd Biesheuvel2015-11-271-1/+0
| | | | | | | | | | | ArmJunoDxe does not use gArmGlobalVariableGuid so drop the declaration from the .inf. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18999 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/Bds: drop bogus ArmGlobalVariable dependenciesArd Biesheuvel2015-11-273-4/+0
| | | | | | | | | | | Remove the GUID references to gArmGlobalVariableGuid and includes of ArmGlobalVariableHob.h since they are not used by the ARM BDS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18998 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/Sec: remove global variable allocation from lowlevel initArd Biesheuvel2015-11-274-17/+3
| | | | | | | | | | | | Now that we dropped all ArmPlatformGlobalVariableLib dependencies, there is no longer a need to allocate and clear out the global variable region in the Sec init code. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18995 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: remove global variable allocation from lowlevel initArd Biesheuvel2015-11-277-52/+3
| | | | | | | | | | | | Now that we dropped all ArmPlatformGlobalVariableLib dependencies, there is no longer a need to allocate and clear out the global variable region in the PrePeiCore init code. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18994 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PlatformPeim: remove ArmGlobalVariable lowlevel initArd Biesheuvel2015-11-272-39/+0
| | | | | | | | | | | | Now that we dropped all ArmPlatformGlobalVariableLib dependencies, there is no longer a need to query the ArmGlobalVariable PPI and install the ArmGlobalVariable HOB. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18993 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePi: remove global variable allocation from lowlevel initArd Biesheuvel2015-11-279-61/+4
| | | | | | | | | | | | Now that we dropped all ArmPlatformGlobalVariableLib dependencies, there is no longer a need to allocate and clear out the global variable region in the PrePi init code. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18992 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: remove all ArmPlatformGlobalVariableLib implementationsArd Biesheuvel2015-11-279-553/+0
| | | | | | | | | | | | This removes the SEC, PEI and DXE variants of ArmPlatformGlobalVariableLib, which is no longer used, and should not be used since it violates the PI spec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18990 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: remove PeiServicesTablePointerLib implementationArd Biesheuvel2015-11-273-136/+2
| | | | | | | | | | | | | This removes the PeiServicesTablePointerLib implementation under ArmPlatformPkg that violates the PI spec, and hence should not be used. Instead, the implementation that resides under ArmPkg should be used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18989 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: drop ArmPlatformGlobalVariableLib resolutionsArd Biesheuvel2015-11-277-30/+4
| | | | | | | | | | | We can remove all mention of ArmPlatformGlobalVariableLib now that there are no remaining [transitive] dependencies on it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18988 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: move to ArmPkg version of PeiServicesTablePointerLibArd Biesheuvel2015-11-272-4/+4
| | | | | | | | | | | | | | | | | As pointed out by Eugene, the ArmPlatformPkg implementation of PeiServicesTablePointerLib violates the PI sec, since it uses ArmPlatformGlobalVariableLib to store the PEI services table pointer rather than the thread ID cpu registers as the spec requires. So instead, move to the ArmPkg version of this library, which does adhere to the PI spec. Reported-by: Eugene Cohen <eugene@hp.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18987 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePiHobListPointerLib: use thread ID registerArd Biesheuvel2015-11-273-15/+7
| | | | | | | | | | | | | | | | | | This updates the PrePiHobListPointerLib implementation in ArmPlatformPkg to move away from ArmPlatformGlobalVariableLib and instead use the thread ID CPU registers (TPIDRURW and TPIDR_EL0 for v7 and v8, respectively) for storing the HobList pointer. Since PrePiHobListPointerLib is specific to PrePi (where PEI core is skipped) we can share these registers with the PEI services table pointer. By the same reasoning, the PEI services table pointer and the HobList pointer already shared the same offset in the ArmPlatformGlobalVariable array. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18982 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: add missing entries to AArch64 vector tableArd Biesheuvel2015-11-271-0/+40
| | | | | | | | | | | | | | | | | The PrePeiCore vector table for AArch64 mode is only half populated. However unlikely, if exceptions from lower exception levels are ever taken, they should be reported correctly, rather than causing a recursive undefined instruction fault on the zero padding that was introduced by commit SVN r18904 ("ArmPkg/ArmPlatformPkg: position vectors relative to base"). So add the missing entries, and wire them up to the default handler. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18976 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Use SerialDxe in MdeModulePkg instead of EmbeddedPkgStar Zeng2015-11-2612-191/+131
| | | | | | | | | | | | | | It is also to integrate PL011SerialPortExtLib to PL011SerialPortLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18971 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPlatformPkg: position vectors relative to baseMark Rutland2015-11-191-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVExpressPkg/ArmVExpressLibRTSM: map NOR flash as normal memoryArd Biesheuvel2015-11-181-1/+1
| | | | | | | | | | | | | | | | | | Some users of this library (i.e., FVP-AArch64 and RTSM-A15_MPCore) may be built to execute straight from NOR flash. Since device mappings should have the XN attribute set (according to the architecture), mapping the NOR flash as a device may prevent it from being executable. Since the NOR flash DXE driver is perfectly capable of setting the correct attributes for the region it needs to write to, and since we will be executing from DRAM by that time anyway, we can simply map the NOR flash as normal memory initially. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18890 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: bring DS-5 scripts in line with linker script changesArd Biesheuvel2015-11-121-23/+3
| | | | | | | | | | | | | | | The ARM and AARCH64 linker scripts have recently been updated so that the memory layouts of the ELF and PE/COFF versions of each module are identical. In particular, this means that the ELF images now have a hole before the first section rather than starting at offset 0x0, which means we no longer have to correct for this difference when loading the ELF image into the debugger. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18775 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Juno - add correct SPI interrupt numbers for MSIJeremy Linton2015-11-032-1/+7
| | | | | | | | | | | | | | | | | | | The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware that has some memory mapped locations that can trigger traditional SPI interrupts. This allows some basic PCIe MSI capabilities. Setup the SPI range that is mapped by the MSI window. This range is described in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is described as "GICv2m PCI Express MSI". In the future when these tables are generated programmatically the information may be found in the MSI_TYPER register as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18723 6f19259b-4bc3-4df7-8a09-765794883524
* Update the ACPI device information for ARM Juno.Jeremy Linton2015-10-192-2/+13
| | | | | | | | | | | | | | | | | | | | | These patches correct a number of problems with the JUNO ACPI tables. First, put CCA attributes on the devices which can do DMA. This is because the linux kernel now requires ARM64 devices specify a coherency model. Without CCA the devices are unable to perform DMA. Update the EHCI window to a full 64k as documented in the Juno Platform SoC TRM. This makes it match the values used in some other places. Finally, add some _DSD entries for the SMSC ethernet chip. The latter changes are required for the mainline kernels to use the adapter. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18628 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: CRLF fixups for Juno ACPILeif Lindholm2015-10-192-194/+194
| | | | | | | | | | All of AcpiSsdtRootPci.asl and some bits of Gtdt.aslc used LF-only line separators. Fix before committing new modifications. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18627 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: NorFlashDxe: mellow DEBUG messages about flash reinitLaszlo Ersek2015-10-161-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ValidateFvHeader() function checks several conditions against the firmware volume header. Failure of the first of these checks, reported as "No Firmware Volume header present", is a common situation for unformatted flash images, especially when a new virtual machine is created. Similarly, "Variable Store Guid non-compatible" is common when the firmware binary is switched from Secure Boot-incapable to Secure Boot-capable, or vice versa. The only caller of ValidateFvHeader(), NorFlashFvbInitialize(), handles all these mismatches by installing a new FVB header. It also emits another, loud ERROR message (which is even less justified when it is triggered by (BootMode == BOOT_WITH_DEFAULT_SETTINGS)). Downgrade these messages from EFI_D_ERROR to EFI_D_INFO, so that they don't clutter the debug output when the PcdDebugPrintErrorLevel mask only enables EFI_D_ERROR (i.e., in a "silent" build). These messages have annoyed / confused users; see for example: - https://bugzilla.redhat.com/show_bug.cgi?id=1270279 - http://thread.gmane.org/gmane.comp.bios.edk2.devel/2772/focus=2869 Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Drew Jones <drjones@redhat.com> Cc: Yehuda Yitschak <yehuday@marvell.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18618 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Fixes for Juno ACPISupreeth Venkatesh2015-10-071-7/+20
| | | | | | | | | | | | | | 1. Change Interrupt for Juno PCI Routing table Interrupt Number Reference: http://www.arm.com/files/pdf/DDI0515D1a_juno_arm_development_platform_soc_trm.pdf table 3-3 page 3-7 2. Support for PCI IO range with ACPI on JUNO Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18576 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg/Madt.aslc: Fix MADT header versionSudeep Holla2015-10-061-12/+12
| | | | | | | | | | | | | Currently the MADT signature and revision is mapped to v1.0 macros which results in MADT with incorrect entries in the header for Juno. This patch fixes these EFI_ACPI_*_0_MULTIPLE_APIC_DESCRIPTION_TABLE macros by using appropriate v5.0 versions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18572 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/RTSM: remove obsolete Foundation model librariesArd Biesheuvel2015-10-066-491/+0
| | | | | | | | | | | These are no longer used by any platform in the tree, nor are they of any significance to any out of tree platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18571 6f19259b-4bc3-4df7-8a09-765794883524
* ArmVExpressPkg: use 4 KB section alignment for ARM DXE_RUNTIME_DRIVER modulesArd Biesheuvel2015-10-011-1/+2
| | | | | | | | | | | | In order to support the Properties Table memory protection feature on 32-bit ARM, build DXE_RUNTIME_DRIVER type binaries with 4 KB section alignment by setting the common-page-size linker command line option. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18567 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: ASSERT that PcdSystemMemoryBase does not exceed MAX_ADDRESSArd Biesheuvel2015-09-091-0/+1
| | | | | | | | | | | | | For 32-bit ARM platforms, it is essential that system memory starts below the 4 GB limit, since that is the only memory we can address using the UEFI spec mandated 1:1 mapping. So assert that this is the case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18429 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/MemoryInitPeim: handle memory above 4 GB on 32-bit ARMArd Biesheuvel2015-09-091-2/+5
| | | | | | | | | | | | | Make sure that the PEI memory region is carved out of memory that is 32-bit addressable, by taking MAX_ADDRESS into account (which is defined as '4 GB - 1' on ARM) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18426 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/HdLcd: add missing LcdIdentify()Ard Biesheuvel2015-09-041-0/+8
| | | | | | | | | | | | | | | | Commit r18308 ("ArmPlatformPkg/LcdGraphicsOutputDxe: check PrimeCell ID before initializing") introduced a LcdIdentify() function to the PL111 LCD driver that makes it fail gracefully when executed on hardware that does not have the IP. However, the LcdGraphicsOutputDxe driver is shared with the HdLcd driver, which now fails to build due to the fact that it has no LcdIdentity() function. So add a dummy implementation that always returns EFI_SUCCESS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18395 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: signal EndOfDxe event in PlatformBsdInitArd Biesheuvel2015-09-043-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | Like the ArmVirtPkg platforms up until SVN r17713, the ArmPlatformPkg platforms built with the Intel BDS fail to signal the end-of-DXE event 'gEfiEndOfDxeEventGroupGuid' when entering the BDS phase, which results in some loss of functionality, i.e., variable reclaim in the VariableDxe drivers, and the splitting of the memory regions that is part of the recently added UEFI 2.5 properties table feature. As discussed on the edk2-devel mailing list here: http://thread.gmane.org/gmane.comp.bios.tianocore.devel/16088/focus=16109 it is up to the platform BDS to signal that event, since there may be platform specific ordering constraints with respect to the signalling of the event that are difficult to honor at the generic level. So add the SignalEvent () call to PlatformBdsInit () of ArmPlatformPkg's PlatformBdsLib implementation for the Intel BDS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18394 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpress-FVP: enable UEFI Secure BootArd Biesheuvel2015-09-013-0/+44
| | | | | | | | | | | | | | | | | This allows the FVP target to be built with UEFI Secure Boot enabled, by passing -D SECURE_BOOT_ENABLE to the build command line. Note that this requires the Intel BDS, or you will not be able to enroll certificates, since the ARM BDS does not provide a GUI to do so. The FVP Base model is recommended in this case, since the certificate store is kept in NOR flash. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18379 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpress-FVP: add support for the Intel BDSArd Biesheuvel2015-09-013-0/+34
| | | | | | | | | | | | | | This adds support for the Intel BDS and enables it by default. To revert to using the ARM BDS, pass '-D USE_ARM_BDS' on the build command line. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18378 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PlatformIntelBdsLib: add splash screen supportArd Biesheuvel2015-09-012-0/+6
| | | | | | | | | | | | | Add a call to EnableQuietBoot () to BdsPlatformPolicyBehavior(), so that a splash screen is shown in case one is present under the correct GUID in the FV, and we have graphics support. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18377 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PlatformIntelBdsLib: fix and clean up error handlingArd Biesheuvel2015-09-011-5/+5
| | | | | | | | | | | | | InitializeConsolePipe () shadowed its own Status variable, and then clobbered the top one before printing its error message. Instead, use a NULL check on the LocateProtocol () output argument. Also clean up coding style on the error path. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18376 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PlatformIntelBdsLib: remove ARM BDS dependencyArd Biesheuvel2015-09-013-8/+15
| | | | | | | | | | | | The Intel BDS platform library still depends on the ARM BDS specific BdsLib. So replace its invocations with GenericBdsLib counterparts, and fix up where needed, so that we can drop the dependency. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18375 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/FVP: unify support for Foundation and Base modelsArd Biesheuvel2015-08-252-17/+0
| | | | | | | | | | | | | Now that the PL180 and PL111 drivers know how to behave when executed on the Foundation model (which does not emulate the hardware), we can remove the ARM_FOUNDATION_FVP ifdefs and produce a single build that runs on both the Foundation model and the Base model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18309 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/LcdGraphicsOutputDxe: check PrimeCell ID before initializingArd Biesheuvel2015-08-254-1/+37
| | | | | | | | | | | | To deal gracefully with the absence of the PL111 hardware on the Foundation model, check the PrimeCell ID before proceeding with the installation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18308 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PL180MciDxe: check PrimeCell ID before initializingArd Biesheuvel2015-08-252-0/+33
| | | | | | | | | | | | To deal gracefully with the absence of the PL180 hardware on the Foundation model, check the PrimeCell ID before proceeding with the installation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18307 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Link separated VarCheckUefiLib NULL class library instanceStar Zeng2015-08-254-4/+16
| | | | | | | | | | Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18291 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Add VarCheckLib library mappingStar Zeng2015-08-251-0/+1
| | | | | | | | | | | | Since Variable driver has been updated to consume the separated VarCheckLib. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18284 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: remove mention of ARMGCC and ARMLINUXGCCArd Biesheuvel2015-08-123-175/+2
| | | | | | | | | | | | | Remove the ARMGCC and ARMLINUXGCC from comments in the respective Makefiles of ArmPlatformPkg and ArmJunoPkg. Also drop the wildly outdated Versatile Express instructions, since they refer to ARMGCC as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18209 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/FVP: use 'auto' alignment and FIXED placement for XIP modulesArd Biesheuvel2015-08-101-6/+6
| | | | | | | | | | | | | | | | | | Now that GenFw correctly propagates the minimum alignment of the ELF input sections to the PE/COFF binary, we can simply select 'auto' alignment in the FDF Rule section instead of tweaking it by hand. Also add the FIXED FFS attribute to the module types that may execute in place. This enables a newly added optimization in GenFfs that strips redundant padding, preventing excessive waste of FV space if the section alignment is considerable (i.e., 2 KB or 4 KB) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18196 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg: use TE 'auto' alignment for SEC modulesArd Biesheuvel2015-08-101-4/+4
| | | | | | | | | | | | | | | | No need to hardcode the TE alignment anymore, now that GenFw sets the PE/COFF alignment according to the alignment requirements of the ELF input sections. Also enable FIXED FFS placement so that we can reclaim some of the space wasted to padding when using clang with 4 KB section alignment. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18195 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmJunoPkg: use a rodata symbol for ReferenceAcpiTableArd Biesheuvel2015-08-104-44/+20
| | | | | | | | | | | | | | | | | | | | The ACPI .aslc files contain a ReferenceAcpiTable() function whose sole purpose is to ensure that the table itself does not get optimized away. However, when using clang, these dummy functions result in a 4 KB section alignment requirement, which is silly since everything except the .data section is discarded later anyway. So instead, make ReferenceAcpiTable a CONST pointer to VOID*. This way, we still have a .text section, which is mandatory for the PE/COFF conversion, but no executable code with small model relocations that impose additional alignment requirements. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18194 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PlatformPeim: constify EFI_PEI_PPI_DESCRIPTOR globalsArd Biesheuvel2015-08-071-2/+2
| | | | | | | | | | | Make global EFI_PEI_PPI_DESCRIPTOR instances CONST to prevent them from being emitted into the .data section. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18189 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: constify PPI globalsArd Biesheuvel2015-08-071-5/+5
| | | | | | | | | | | | | | | Since PrePeiCore's .text section contains an AARCH64 exception vector table, its 2 KB alignment propagates to other sections as well. Since this is a SEC module, it should not have any writable data in the first place, so change some non-const PPI globals to const. The resulting binary has no .data section at all, which saves 2 KB in the XIP image. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18188 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpressPkg: move to unified GCC linker scriptArd Biesheuvel2015-08-031-1/+1
| | | | | | | | | | | | | | Move to the parametrised generic GCC linker script and set 64 KB alignment, instead of using the AARCH64 specific incremental linker script for 64 KB alignment which is about to be removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18139 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: remove obsolete ARM and AARCH64 platformsArd Biesheuvel2015-07-2953-8538/+0
| | | | | | | | | | | | | | | | Remove obsolete ARM and AARCH64 platforms so the maintainers can focus on the ones that are still supported, which are: - TC2 (ArmVExpress-CTA15-A7.dsc) - Foundation model and Fast model emulators (ArmVExpress-FVP-AArch64.dsc) - Juno (ArmJunoPkg/ArmJuno.dsc) - Cortex-A15 MPcore RTSM (ArmVExpress-RTSM-A15_MPCore) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18110 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: copy ArmGicArchLib to ArmGicArchSecLibArd Biesheuvel2015-07-284-0/+7
| | | | | | | | | | | | | | Clone ArmGicArchLib into a SEC phase specific ArmGicArchSecLib so that we can modify the former in a subsequent patch to cache the GIC revision in a global variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18099 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: split off ArmGicArchLib from ArmGicLibArd Biesheuvel2015-07-284-0/+4
| | | | | | | | | | | | | | | | | | | | | | | The current implementation of ArmGicGetSupportedArchRevision () that is used by all ARM platforms is entirely stateless (in order to support being executed from flash) so it needs to interrogate the hardware for the supported GIC revision upon each invocation. However, this statelessness is only needed for SEC type modules; in all other cases, we could easily determine the GIC revision once, and store the result in a global variable. In preparation of having separate early and normal versions, this patch introduces the ArmGicArchLib library class and default implementation, and moves the existing ArmGicGetSupportedArchRevision () into it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/Bds: Use HandleProtocol to get SNP instanceHeyi Guo2015-07-161-1/+1
| | | | | | | | | | | | | | | | LocateProtocol only gets the 1st SNP instance and this will be wrong in a system with multiple SNP instances installed. Use HandleProtocol instead. Cc: Olivier Martin <olivier.martin@arm.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Olivier Martin <Olivier.Martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18030 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-13 23:28:47 +0000