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* Coreboot*Pkg: Retire CorebootPayloadPkg and CorebootModulePkgMaurice Ma2019-05-101-1089/+0
| | | | | | | | | | | | | | RFC: https://edk2.groups.io/g/devel/message/39126 Since UefiPayloadPkg in EDK2 supports Coreboot and Slim Bootloader, and I don't receive any concerns for the RFC to remove CorebootModulePkg and CorebootPayloadPkg from EDK2, here is the action patch to remove CorebootPayloadPkg and CorebootModulePkg. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootModulePkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootModulePkg: Fix various typosAntoine Coeur2019-02-121-6/+6
| | | | | | | | Fix various typos in CorebootModulePkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Coeur <coeur@gmx.fr> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* CorebootModulePkg/BaseSerialPortLib: Set DTR and RTSLeahy, Leroy P2016-05-101-2/+3
| | | | | | | | | | | | | | | Ensure communication between the host and the UEFI system running CorebootPayloadPkg. In cases where the host has flow control enabled and the serial connection is providing the flow control signals, the host will not be able to send data to the UEFI system because DTR and RTS are not present. The host may also discard all output data from the UEFI system because DTR is not present. By setting DTR and RTS in the UART initialization code this case works properly. Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/BaseSerialPortLib16550: Remove white-spaceLeahy, Leroy P2016-05-101-63/+63
| | | | | | | | | Remove trailing white space. Change-Id: I73c3a3e1e55eec20b09443de1966573c97fa74f8 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg: Add BaseSerialPortLib16550Leahy, Leroy P2016-05-101-0/+1094
Copy MdeModulePkg/Library/BaseSerialPortLib16550 revision 89ecd4cf8078aa946083cdcbf9af81ff29f8d9f5. Change-Id: Ie2fd0123bdd7aaba4335afdb1cb017f3690455c6 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>