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* CorebootPayloadPkg: Replace PciHostBridge driver with PciRootBridgeNoEnumerationMaurice Ma2015-05-113-4/+4
| | | | | | | | | | | | | | | Current CorebootPayloadPkg uses PciHostBridge and PciBusNoEnumeration driver. It will cause the PCI bus resource incorrectly set in root bridge instance. As a result all PCI devices behind a PCI bridge will not show up in Shell 'PCI' command. To resolve it use PciRootBridgeNoEnumeration driver instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17408 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Use the new PCDs defined in MdePkg.Ruiyu Ni2015-05-061-1/+1
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17325 6f19259b-4bc3-4df7-8a09-765794883524
* Coreboot*Pkg/Contributions.txt: Update example email addressJordan Justen2015-04-141-2/+2
| | | | | | | | | | | | | | | Use the example.com domain as recommended in RFC 2606. This was changed for the other EDK II packages in r16724. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17169 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Rename CorebootPayloadPkgX64.dsc X64 -> Ia32X64Jordan Justen2015-04-142-2/+2
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17168 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Rename CorebootPayloadPkgIA32.dsc IA32 -> Ia32Jordan Justen2015-04-142-11/+2
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17167 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Remove empty folder reference in DEC fileMaurice Ma2015-04-101-3/+0
| | | | | | | | | | | | | | | In current CorebootPayloadPkg.dec an empty 'Include' directory is listed in [includes] section. However, this empty directory will not be mirrored into git repo. If the source tree is pulled from git, the 'Include' empty folder will not exist and it will cause build failure. The fix is to remove the whole [Includes] section in the DEC file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17164 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Avoid page table memory allocation failureScott Duplichan2015-04-101-0/+1
| | | | | | | | | | | | | | Enable use of 1GB pages to avoid page table memory allocation failure. The failure occurs when allocating enough 4KB pages to map a large virtual address space, such as the 48-bit virtual address space of AMD family 10h and family 15h processors. The change is needed only for the X64 build because page tables are not used by the IA32 build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17151 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Use unique path for IA32 and X64 payload binariesScott Duplichan2015-04-102-2/+2
| | | | | | | | | | | Use unique output directory names so that both IA32 and X64 payloads can be built without overwriting one another. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17150 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Add NOOPT build to accommodate source level debuggingScott Duplichan2015-04-102-2/+2
| | | | | | | | | | | | Add NOOPT build to accommodate source level debugging. The NOOPT build avoids the use of compiler optimization so that every local variable is accessible by a source level debugger. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17149 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Increase payload size limitScott Duplichan2015-04-101-4/+4
| | | | | | | | | | | Increase payload size limit to accomodate large binaries, such as those produced by Microsoft NOOPT builds and gcc DEBUG builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17148 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Use extra braces to prevent gcc compile failScott Duplichan2015-04-101-3/+3
| | | | | | | | | | | Use extra braces around initialization data to prevent gcc compile error: -Werror=missing-braces. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17147 6f19259b-4bc3-4df7-8a09-765794883524
* Pkg-Module: CorebootPayloadPkgMaurice Ma2015-03-3121-0/+6082
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial coreboot UEFI payload code check in. It provides UEFI services on top of coreboot that allows UEFI OS boot. CorebootPayloadPkg is source code package of coreboot Payload Modules, Provides definitions of payload image's layout and lists the modules required in DSC file. It supports the following features: - Support Unified Extensible Firmware Interface (UEFI) specification 2.4. - Support Platform Initialization(PI) specification 1.3. - Support execution as a coreboot payload. - Support USB 3.0 - Support SATA/ATA devices. - Support EFI aware OS boot. The following features are not supported currently and have not been validated: - GCC Tool Chains - SMM Execution Environment - Security Boot It was tested on a Intel Bay Trail CRB platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17081 6f19259b-4bc3-4df7-8a09-765794883524
* Pkg-Module: Add Coreboot Payload Packagelaurie01312015-03-252-0/+243
Full-commit-message Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: laurie0131 <Laurie.jarlstrom@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17074 6f19259b-4bc3-4df7-8a09-765794883524
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