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* CorebootPayloadPkg: Fix build failure due to Tftp/Dp library removalRuiyu Ni2017-11-293-35/+41
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* edk2: Move License.txt file to rootMichael D Kinney2017-08-031-25/+0
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=642 Add top level License.txt file with the BSD 2-Clause License that is used by the majority of the EKD II open source project content. Merge copyright statements from the BSD 2-Clause License files in each package directory and remove the duplication License.txt file from package directories. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* edk2: Move TianoCore Contribution Agreement to rootMichael D Kinney2017-08-031-218/+0
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=629 Move Contributions.txt that contains the TianoCore Contribution Agreement 1.0 to the root of the edk2 repository and remove the duplicate Contributions.txt files from all packages. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* CorebootPayloadPkg: Use EfiEventGroupSignal from UefiLibStar Zeng2017-01-201-23/+2
| | | | | | | | | | | | | | | Use EfiEventGroupSignal from UefiLib and remove InternalBdsEmptyCallbackFuntion. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=298 Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg: Add APRIORI file in FDF fileMaurice Ma2017-01-121-0/+6
| | | | | | | | | | | | Add APRIORI file to allow status code related DXE drivers to be dispatched earlier so that debug message can also be seen much earlier. With this, lots of DXE driver debug message will be missing. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Remove improper build flags in DSC fileMaurice Ma2017-01-101-2/+0
| | | | | | | | | | | | | | | | | Current CorebootPayloadPkgIa32X64.dsc contains "-flto" flag to request GCC link time optimization. However, this feature is only supported by newer GCC compiler, and it will break the debug build with GCC4.8. To fix it, the extra compiling flags are removed. It allows the default build flags set by the EDKII build environment to be used. With this fix, CorebootPayloadPkg 64bit debug build can pass using GCC 4.8. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* CorebootPayloadPkg: Allow PciLib instance selectionMaurice Ma2016-11-172-0/+10
| | | | | | | | | | | | | | | On old platform without PCIe express support, the PciLib needs to be mapped to PciLibCf8 instance to make it work. On new platform with PCIe express support, the PciLib needs to be mapped to PciLibPciExpress to allow access to extended PCIe configuration space. This patch allows to select the PciLib instance between PciLibCf8 and PciLibPciExpress using the PCIE_BASE macro through build command line. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayload/PlatformBds: Dispatch deferred images after EndOfDxeRuiyu Ni2016-11-101-0/+5
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Reviewed-by: Sunny Wang <sunnywang@hpe.com>
* CorebootPayloadPkg: Fix GCC build issue on macro definitionMaurice Ma2016-11-092-2/+2
| | | | | | | | | | | | | The previous change to disable deprecated APIs in CorebootPayloadPkg used "/D" instead of "-D". It caused Linux GCC build error. Correct it to use "-D" instead. Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Rusty Coleman <rcoleman@sigovs.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> Reviewed-by: Rusty Coleman <rcoleman@sigovs.com>
* CorebootPayloadPkg: Fix typos in commentsMaurice Ma2016-11-071-2/+2
| | | | | | | | | | | - dirver -> driver - futhure -> future Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg: Add "Down" key to Boot Manager Menugdong12016-10-271-2/+11
| | | | | | | | | Also add Down key to Boot Manager Menu since some serial terminals don't support F2 key. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg: Make EFI shell the last boot option.gdong12016-10-271-5/+5
| | | | | | | | | To let it boot to OS automatically, make built in shell as the last boot option. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg: Add an option to use HPET timer driverMaurice Ma2016-10-273-0/+24
| | | | | | | | | | | | The current CorebootPayloadPkg will use the legacy 8254 timer driver as the default. However, on some platforms legacy timer might not exist anymore. This patch adds HPET timer driver as a build option. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Notify EndOfDxe and install ReadyToLock protocol.gdong12016-10-263-4/+69
| | | | | | | | | Update PlatformBootManagerLib to notify EndOfDxe event and install SmmReadyToLock protocol since other modules depend on them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: gdong1 <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootModulePkg: Add a library to parse platform specific info.gdong12016-10-262-0/+2
| | | | | | | | | | Update CbSupportPei to consume the new library, so platform could provide platform specific library instance to parse platform specif info. And add a NULL library instance to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: gdong1 <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg DSC: Add build option to disable deprecated APIsMaurice Ma2016-10-262-0/+2
| | | | | | | | | | | | | | | Add the following definition in the [BuildOptions] section in package DSC files to disable APIs that are deprecated. As a result replaced PcdSet32 with PcdSet32S accordingly to make the build pass. [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES Cc: Prince Agyeman <prince.agyeman@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=163 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg DSC: Change the section alignment optionMaurice Ma2016-10-263-0/+7
| | | | | | | | | | | | The current CorebootPayloadPkg will print the following message "InsertImageRecord - Section Alignment(0x20) is not 4K" during boot. It is caused by the section alignment arranged by the linker. This patch change the alignment to 4K for runtime drivers. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Switch to use StatusCode driver in MdeModulePkgMaurice Ma2016-10-263-10/+16
| | | | | | | | | | | The current CorebootPayloadPkg uses PEI/DXE StatusCode drivers from IntelFrameworkModulePkg. This patch switches to use the StatusCode driver from MdeModulePkg instead. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limitMaurice Ma2016-10-181-2/+2
| | | | | | | | | | | The current PCI resource limit calculation in CorebootPayloadPkg PciHostBridgeLib is wrong. Adjusted it to match the PciHostBridge driver's expectation. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg/ResetSystemLib: Implement ResetPlatformSpecificRuiyu Ni2016-09-021-1/+22
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: fixed GCC49 and GCC5 hang in PeiCorePrince Agyeman2016-08-171-2/+2
| | | | | | | | | | Section alignment of .data in GCC49 and GCC5 are 0x40 rather than 0x20 in GCC48 and below. This causes a hang in PeiCore. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Prince Agyeman <prince.agyeman@intel.com> Reviewed by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg : Added MpInitLib to CorebootPayloadPkg.dscPrince Agyeman2016-08-172-0/+2
| | | | | | | | MpInitLib is consumed by CpuDxe Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Prince Agyeman <prince.agyeman@intel.com> Reviewed by: Maurice Ma <maurice.ma@intel.com>
* CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issueMaurice Ma2016-05-271-1/+5
| | | | | | | | | | | | | | The current PCI 64bit memory BAR size calculation in PciHostBridgeLib assumes all 32 bits in the upper BAR are fully writable. However, platform might only support partial address programming, such as 40bit PCI BAR address. In this case the complement cannot be used for size calculation. Instead, the lowest non-zero bit should be used for BAR size calculation. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Consume PlatformHookLib in PlatformBootManagerLibMaurice Ma2016-05-231-1/+2
| | | | | | | | | | | | | | When coreboot uses different baud rate from the default (115200), the current BDS driver will not be able to enable serial console display due to the inconsistent serial port PCD settings. By adding the PlatformHookLib reference in the inf file, it will enforce the PCDs to be aligned with what have been passed from coreboot. Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Lee Leahy <leroy.p.leahy@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed by: Lee Leahy <leroy.p.leahy@intel.com>
* CorebootPayloadPkg: Use generic PciBus/PciHostBridge driverMaurice Ma2016-05-237-10/+976
| | | | | | | | | | | | | Current CorebootPayloadPkg uses PciBusNoEnumerationDxe and PciRootBridgenoEnumerationDxe copied from the DuetPkg. Now it will switch to use the standard PciBusDxe and PciHostBridgeDxe from MdeModulePkg. As a result, a coreboot specific PciHostBridgeLib is added to collect pre-allocated PCI resources. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg/PlatformBootManagerLib: Fix Linux buildLeahy, Leroy P2016-05-231-2/+1
| | | | | | | | | Fix Linux build failure with GCC 4.8.4 due to missing braces. Change-Id: Ic0de6520605149f1bb74f8b60ce8cab8beda10a4 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg: Remove BdsPlatform libraryMaurice Ma2016-05-204-1298/+0
| | | | | | | | | | Since the new BdsDxe driver in MdeModulePkg is used, the old BdsPlatform library is not used any more and should be removed. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Switch to use generic BdxDxe driverMaurice Ma2016-05-204-14/+55
| | | | | | | | | Switch over to use BdxDxe generic driver in MdeModulePkg. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Add coreboot PlatfromBootManagerLib implementationMaurice Ma2016-05-207-12/+1133
| | | | | | | | | | | In order to use the generic BdsDxe in MdeModulePkg, a platform specific PlatfromBootManagerLib is required. This library will help update the ConIn, ConOut and ErrOut variables. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
* CorebootPayloadPkg: Use generic SerialDxe driverMaurice Ma2016-05-133-6/+3
| | | | | | | | | | | Use generic SerialDxe driver in MdeModulePkg instead of the one in CorebootModulePkg. By doing this the reference for PciSioSerialDxe driver will also be removed from DSC and FDF file. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
* CorebootPayloadPkg: Add OHCI driverLeahy, Leroy P2016-05-123-49/+64
| | | | | | | | | Add the USB OHCI driver from revision 24ca2f35 of QuarkSocPkg. Change-Id: Ie7aa0bc47d4ff06adc57976a5efb0e40ce4e1673 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg: Add SD/eMMC supportLeahy, Leroy P2016-05-123-0/+21
| | | | | | | | | | Add SD and eMMC DXE driver support to CorebootPayloadPkg. Change-Id: Ibfd3a2cc32a653ce51e38d9157ea3c6da25a5474 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Set the proper Shell file GUIDLeahy, Leroy P2016-05-122-0/+22
| | | | | | | | | | | Set the proper Shell file GUID so that the BDS transfers control to the Shell. Change-Id: I816636a340bbe2f76ac1973b9cb685084c4f88a0 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Use correct BaseSerialPortLib16550Leahy, Leroy P2016-05-122-2/+2
| | | | | | | | | | | | | Use the BaseSerialPortLib16550 which sets RTS and DTR during initialization. This fixes the mis-matched flow control issue when the flow control signals are connected between the host and target and the host has flow control enabled. Change-Id: I3505e129b2de3c5c17fff23c62553f15cd892dca Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Assume no PCI serial devicesLeahy, Leroy P2016-05-122-4/+4
| | | | | | | | | | Set the vendor to 0xffff which indicates the end of the list. Change-Id: If6475e04d3675f0a932571a85d1dd3f301416b6a Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> eviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Use DOS line endingsLeahy, Leroy P2016-05-123-460/+455
| | | | | | | | | Convert to using DOS line endings. Change-Id: Ie2f148867d9b2b386d556583afb6716ec21399e9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg/PlatformBdsLib: Pass more serial parametersLeahy, Leroy P2016-05-104-5/+71
| | | | | | | | | | Pass the serial port baudrate, register stride, input clock rate and ID from coreboot to CorebootPayloadPkg. Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Use serial drivers with PlatformHookLibLeahy, Leroy P2016-05-053-3/+6
| | | | | | | | | | Use the serial drivers which update the serial PCDs from PlatformHookLib. Change-Id: Ie6a3526d56332ee1cf07edb24ff39634a981183f Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Allow MaxLogicalProcessorNumber to be changedLeahy, Leroy P2016-05-052-0/+14
| | | | | | | | | | Add a define and use it with MaxLogicalProcessorNumber to enable this PCD to be changed via the command line. Quark needs to set this value to one during the builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Make serial I/O configurableLeahy, Leroy P2016-05-052-16/+131
| | | | | | | | | | Allow the serial port configuration to be overriden from the command line. Make the debug serial PCDs patchable in module. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Make shell selectableLeahy, Leroy P2016-05-053-6/+170
| | | | | | | | | | | | | | | | Add all of the shell options from ShellBinPkg including building the shell from source. Enable link time optimization for GCC debug builds to keep the size under 0x3e0000. Test: Use -DSHELL_TYPE=BUILD_SHELL command line options to build the shell from source. Run the result on Galileo Gen2. Change-Id: I1e12adb57960ac5e75e682073540a9322aa03081 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg: Remove DuetPkg referencesLeahy, Leroy P2016-05-023-9/+9
| | | | | | | | | | | | | | | | | Remove the references to DuetPkg. Copy the files from revision ffea0a2ce21e8e9878587de2419959a7bfea4021 of DuetPkg into CorebootModulePkg. The components include: * PciBusNoEnumerationDxe * PciRootBridgeNoEnumerationDxe * SataControllerDxe TEST=Build and run on Galileo Gen2 Change-Id: Id07185f7e226749e5f7c6b6cb427bcef7eac8496 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Remove trailing white spaceLeahy, Leroy P2016-05-023-133/+126
| | | | | | | | Remove trailing white space from existing .dsc and .fdf files. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: Convert to build FatPkg from sourceJusten, Jordan L2016-04-073-8/+6
| | | | | | | | | | | Now that FatPkg is open source (and therefore can be included in the EDK II tree) we build and use it directly. Note: Build tested with GCC 5.3 on IA32 and IA32+X64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg: PlatformBdsLib: remove set but unused variablesLaszlo Ersek2016-03-251-2/+0
| | | | | | | | | Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* CorebootPayloadPkg: FbGop: remove set but unused variablesLaszlo Ersek2016-03-251-11/+6
| | | | | | | | | Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* FW: [PATCH 3/9] CorebootPayloadPkg/PlatformBdsLib: Fix spelling errorLeahy, Leroy P2016-03-073-4/+4
| | | | | | | | | | | | | | | -----Original Message----- From: Leahy, Leroy P Sent: Friday, March 4, 2016 8:58 AM To: Ni, Ruiyu <ruiyu.ni@intel.com>; edk2-devel@lists.01.org; Bjorge, Erik C <erik.c.bjorge@intel.com> Cc: Leahy, Leroy P <leroy.p.leahy@intel.com> Subject: [PATCH 3/9] CorebootPayloadPkg/PlatformBdsLib: Fix spelling error Change vender to vendor Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg PlatformHookLib: Fix GCC build failureStar Zeng2015-11-301-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Add return status check to fix GCC build failure below. error: right-hand operand of comma expression has no effect [-Werror=unused-value] ((_gPcd_BinaryPatch_PcdSerialUseMmio = (Value)), RETURN_SUCCESS) error: right-hand operand of comma expression has no effect [-Werror=unused-value] ((_gPcd_BinaryPatch_PcdSerialRegisterBase = (Value)), RETURN_SUCCESS) http://article.gmane.org/gmane.comp.bios.edk2.devel/4949 Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Suggested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19069 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkg: Use SerialDxe in MdeModulePkgStar Zeng2015-11-269-794/+92
| | | | | | | | | | | | | | | | | | | | 1. Update fdf and dsc to use SerialDxe in MdeModulePkg. 2. Separate the code that gets SerialRegBase and SerialRegAccessType by CbParseLib from CorebootPayloadPkg/Library/SerialPortLib to PlatformHookLib, and then leverage BaseSerialPortLib16550 in MdeModulePkg. 3. Remove CorebootPayloadPkg/SerialDxe and CorebootPayloadPkg/Library/SerialPortLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18968 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootPayloadPkgIa32: Don't specify X64 architectureJordan Justen2015-07-271-1/+1
| | | | | | | | | | | CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc doesn't use any X64 modules, so it should not specify the X64 architecture. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18073 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-03 13:44:54 +0000