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* IntelFsp2Pkg: Add FSP*_ARCH_UPD.Chasel Chiu2020-06-231-1/+80
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781 Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events and multi-phase silicon initialization. For backward compatibility the original structures are kept and new ARCH_UPD structures will be included only when UPD header revision equal or greater than 2. GenCfgOpt script also updated to prevent from generating duplicate FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add FunctionParametePtr to FspGlobalData.Chasel Chiu2020-05-212-3/+27
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2726 When FSP switching stack and calling bootloader functions, the function parameter in stack may not be accessible easily. We can store the function parameter pointer to FspGlobalData and retrieve it after stack switched. Also need to add Loader2PeiSwitchStack () to header file as public function for platform FSP code to consume. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.Chasel Chiu2020-05-144-9/+158
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Also new SecCore module created for FspMultiPhaseSiInit API New ARCH_UPD introduced for enhancing FSP debug message flexibility now bootloader can pass its own debug handler function pointer and FSP will call the function to handle debug message. To support calling bootloader functions, a FspGlobalData field added to indicate if FSP needs to switch stack when FSP running on separate stack from bootloader. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Fix various typosAntoine Cœur2019-07-112-6/+6
| | | | | | | | Fix various typos in IntelFsp2Pkg. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* Revert "FmpDevicePkg: Fix various typos"Antoine Cœur2019-07-112-6/+6
| | | | | | | | This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b. Commit message was incorrect. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* FmpDevicePkg: Fix various typosAntoine Cœur2019-07-092-6/+6
| | | | | | | | Fix one typo in FmpDevicePkg. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: add TempRamExitPpi.h.Chasel Chiu2019-06-201-0/+52
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883 Add header file for FSP_TEMP_RAM_EXIT_PPI which is defined by FSP 2.1 spec. Test: Build successfully. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0915-105/+15
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add function to get bootloader stack pointerChasel, Chiu2019-01-281-5/+16
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1391 FSP on-going enhancement for stack utilization required to know bootloader stack pointer and this pointer can be retrieved by first input parameter address when FSP-M entry API invoked by bootloader. Test: Verified on internal platform and booting successfully Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Remove unused keyword in new PPI headerChasel, Chiu2019-01-211-1/+0
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1477 There was unused keyword added in FspmArchConfigPpi.h header block and should be removed. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch modeChasel, Chiu2019-01-171-0/+54
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381 In Dispatch mode FSP may consume PPI directly so creating FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD. Also Keeps new structure size 8 bytes alignment as other structures. Test: Verified on internal platform to boot with this PPI installed successfully. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Support FSP Dispatch modeChasel, Chiu2018-10-191-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241 Add support for both API (original mode) and DISPATCH mode: 1. Add FspMode field from reserved byte of Global Data Structure to tell which mode is selected by boot loader. If boot loader invoking FSP-M API this field will remain as default 0 (API mode), otherwise platform FSP should set this field to 1 (Dispatch mode) when initializing Global Data Structure. 2. gFspInApiModePpiGuid will be instaled when FSP running in API mode and modules only for API mode should have this in depex. 3. If it is DISPATCH mode, FSP will return to PEI dispatcher, not directly return to boot loader. 4. DISPATCH mode supports DXE NotifyPhase drivers so FSP will not wait for PEI NotifyPhase callbacks, instead it will install gFspReadyForNotifyPhasePpiGuid PPI for platform to complete late initialization before transferring to DXE. Test: Verified FSP API and DISPATCH modes on 2 internal platforms and both boot successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg: Clean up source filesLiming Gao2018-06-283-6/+6
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg: Support to return error status from FSP API doneThomaiyar, Richard Marian2016-11-141-0/+35
| | | | | | | | | | | | | | | | Added FspMemoryInitDone2, FspTempRamExitDone2, FspSiliconInitDone2 to return error status to Boot Loader for FSP API calls. To maintain backward compatibility existing functions (FspMemoryInitDone, FspTempRamExitDone, FspSiliconInitDone) declaration left untouched. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Removing FSP Data TableSatya Yarlagadda2016-10-281-32/+0
| | | | | | | | | | | | | | | | FSP Base address is part of FSP_INFO_HEADER and we don't need additional table to report the base address of FSP components. we expect Boot loaders to parse the FSP INFO Header to get the base address. Also, this the FSP_DATA_TABLE is not defined in the FSP EAS and we don't see a need for it. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Added changes to enable FPDT performance measurementsYarlagadda, Satya P2016-10-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | IntelFsp2Pkg: 1.Defined performance measure mask to mask the Perf id (Bits 63:56) of the Perf Data from FSP Global data. 2.Replaced the hard coded perf ids to use the standard defines from FspStatuscode.h 3.Add the PerfData form Fsp Global data ( for TempRaminit entry, TempramInit exit, memoryinit entry) to FPDT entries IntelFsp2WrapperPkg: Moved the code to add the FSP FPDT records and wrapper FPDT records from ReadytoBoot event to EndofFirmware event Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Fix typos in commentsGary Lin2016-10-241-1/+1
| | | | | | | | | | | | | | - tempory -> temporary - immediatly -> immediately - permenent -> permanent - funciton -> function Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Only include required header files in FspEas.hMaurice Ma2016-08-051-1/+1
| | | | | | | | | | | | | Current FspEas.h file includes Uefi.h which also refers to lots of other UEFI header files not used by FSP consumer. It caused many unnecessary header file overhead for a bootloader that consumes FSP, such as coreboot. This change reduces the required header file number down to 3. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Remove CarBase and CarSize from FSP_GLOBAL_DATASatya Yarlagadda2016-07-232-22/+0
| | | | | | | | | | | | | | CarBase and CarSize in Fsp Global data structure are no longer needed as Boot loader doesn't pass them to FSP even in case that BL chooses to skip calling the FspTempRamInit API. In case of FspTempramInit is called, we can use the PCDs to identify the CarBase and Size. Hence we remove the relevant code. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg BaseFspPlatformLib: Remove Boot Loader tempram MigrationSatya Yarlagadda2016-07-181-9/+0
| | | | | | | | | | | | | In FSP2.0, Boot loader should migrate its temp ram before calling the tempramexit API to tear down the tempram. so, we don't need the function to migrate the BL TempRam in the IntelFsp2Pkg. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg-BaseFspCommonLib: Add funtion to return the reset required statusYarlagadda, Satya P2016-06-271-0/+11
| | | | | | | | | | | | Added new funtion in FSPCommonLib to update the FSP API return status with the requested return status and return the control to the boot loader. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: rename GetFspVpdDataPointer() to GetFspCfgRegionDataPointer()Jiewen Yao2016-06-181-3/+3
| | | | | | | | | | | | | | | FSP2.0 removed VPD concept. Rename GetFspVpdDataPointer() to GetFspCfgRegionDataPointer() to follow FSP2.0 specification (CfgRegionOffset). Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
* IntelFsp2Pkg: Add missing OEM status code defines.Giri P Mudusuru2016-06-011-0/+14
| | | | | | | | | | | Adding defines from FSP EAS v2.0 section 11.2.2 Oem Status code. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* IntelFsp2Pkg/FspApi.h: Add comment for structure definition.Jiewen Yao2016-05-201-0/+33
| | | | | | | | | | | | Add doxygen style comment for structure definition. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* Add IntelFsp2Pkg and IntelFsp2WrapperPkg.Jiewen Yao2016-05-1315-0/+1371
Add FSP2.0 support. This series of patch is to support FSP2.0 specification at https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf Some major updates include: 1) One FSP binary is separated to multiple components: FSP-T, FSP-M, FSP-S, and optional FSP-O. Each component has its own configuration data region. 2) All FSP-APIs use same UPD format - FSP_UPD_HEADER. 3) Add EnumInitPhaseEndOfFirmware notifyphase. 4) FSP1.1/FSP1.0 compatibility is NOT maintained. 5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg, to indicate that it is for FspWrapper only. IntelFspPkg and IntelFspWrapperPkg will be deprecated. The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg and IntelFsp2WrapperPkg. The old platform can still use IntelFspPkg and IntelFspWrapperPkg for compatibility consideration. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
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