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* IntelFsp2Pkg: Consume MdeLibs.dsc.inc for RegisterFilterLibDandan Bi2021-03-311-0/+2
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 MdeLibs.dsc.inc was added for some basic/default library instances provided by MdePkg and RegisterFilterLibNull Library was also added into it as the first version of MdeLibs.dsc.inc. So update platform dsc to consume MdeLibs.dsc.inc for RegisterFilterLibNull which will be consumed by IoLib and BaseLib. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add YAML file generation supportLoo Tung Lun2021-02-0911-132/+2421
| | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3091 Add support for YAML format file generation in addition to current BSF structure. Configuration of YAML format output will be supported by an open source ConfigEditor. Reference to YAML code, test and ConfigEditor is at https://github.com/joshloo/fsp_yaml_cfg/tree/master/Tools A unit test is also added in Tests folder. This test compares the generated yaml file against the expected output to know if it is constructing the yaml data structure as expected. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Incremental build with UPD in sub DSC.Chasel Chiu2020-12-091-2/+11
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3107 Current script only compares main DSC and output file datetime to determine if re-generation required or not. When UPD defined in sub DSC and was modified current script cannot detect and will not re-generate output files which caused incremental build issue. Since UPD can be defined in any sub DSC the script has been updated to compare all DSC datetime with output files to determine re-generation is needed or not. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Tested-by: Yuwei Chen <yuwei.chen@intel.com>
* IntelFsp2Pkg/Tools: Fixed PatchFv.py to parse new Fv map file formatBob Feng2020-11-191-3/+6
| | | | | | | | | | | | | | | | | | | The commit 76e8aac158b0717fa27f12e4d008f79161ddb050 changed Fv map format. It added the image type to better support source level debug. But it broke the function of PatchFv.py because PatchFv.py also consume Fv map file. This patch is to update PatchFv.py to make it work again. Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Yunhua Feng <fengyunhua@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* IntelFsp2Pkg: Fix FSP binary rebasing issue for PE32+ imageMaurice Ma2020-11-151-2/+6
| | | | | | | | | | | | | | | | | | | | | Current FSP rebasing script SplitFspBin.py has support for both PE32 and PE32+ image formats. However, while updating the ImageBase field in the image header, it always assumed the ImageBase field is 32bit long. Since PE32+ image format defined ImageBase as 64bit, the current script will only update the lower 32bit value and leave the upper 32bit untouched. It does not work well for PE32+ image that requires update in the upper 32bit ImageBase field. The expected behavior is to update the full 64bit field. This patch implemented this fix. Signed-off-by: Maurice Ma <maurice.ma@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/Tools: Fix a typo issuefengyunhua2020-10-191-1/+1
| | | | | | | | | | | | | | | Error message: raise Exception ("'%s' is not a valid directory!" % FvDir) NameError: name 'FvDir' is not defined FvDir should be fvDir. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Yunhua Feng <fengyunhua@byosoft.com.cn> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/GenCfgOpt: skip unnecessarily header/BSF recreating.Chasel Chiu2020-10-121-18/+42
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2967 When no change in FSP UPD DSC files, GenCfgOpt.py should skip recreating UPD header and BSF files. This patch added a check to handle this case. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* IntelFsp2Pkg GenCfgOpt.py: Initialize IncLines as empty listgaoliming2020-09-251-0/+1
| | | | | | | | | | | IncLines as empty list for the case when InputHeaderFile is not specified. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg/Tools/GenCfgOpt.py: Fix a bug about parse macroTan, Ming2020-07-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2827 Fix a bug about parse the macro value which use another macro. Use the following example to verify: [Define] DEFINE M1 = V1 DEFINE M2 = $(M1)/V2 !include $(M2)/pcd.dsc The old code will failed parse M2 and cause following error: Traceback (most recent call last): File "Edk2\IntelFsp2Pkg\Tools\GenCfgOpt.py", line 1550, in <module> sys.exit(Main()) File "Edk2\IntelFsp2Pkg\Tools\GenCfgOpt.py", line 1513, in Main if GenCfgOpt.ParseDscFile(DscFile, FvDir) != 0: File "Edk2\IntelFsp2Pkg\Tools\GenCfgOpt.py", line 533, in ParseDscFile NewDscLines = IncludeDsc.readlines() ValueError: I/O operation on closed file. The tool should support the value use another macro, and expand it. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Ming Tan <ming.tan@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add FSP*_ARCH_UPD.Chasel Chiu2020-06-231-3/+3
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781 Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events and multi-phase silicon initialization. For backward compatibility the original structures are kept and new ARCH_UPD structures will be included only when UPD header revision equal or greater than 2. GenCfgOpt script also updated to prevent from generating duplicate FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Coverity scan flags issues.Chasel Chiu2020-02-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1706 Issues were: 1. copy_paste_error: PeOptHdr vs PePlusOptHdr. 2. invalid_operation: Invalid operation on null-like value "roffset". 3. invalid_operation: Invalid operation on null-like value "rsize". Fixed them by initializing roffset and rsize as PE32 image type and overriding them when PE32+ header found. Test: Compared script output before and after this patch and the result is identical. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Coverity scan flags issues.Chasel Chiu2020-02-131-1/+2
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1706 Issue was: invalid_operation: Invalid operation on null-like value "Base". Fixed it by initializing Base to 0 before entering while loop. Test: Compared script output before and after this patch and the result is identical. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Command crashed when FV almost full.Chasel Chiu2019-10-281-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2310 When target FV 99% used and only few bytes space left, SplitFspBin.py may crash with below error: File "SplitFspBin.py", line 457, in ParseFv ffshdr = EFI_FFS_FILE_HEADER.from_buffer (self.FvData, offset) ValueError: Buffer size too small (40960 instead of at least 40968 bytes) It was because the offset used by FFS_HEADER parser out of bounds. It should stop parsing when offset equal or larger than (buffer size - FFS_HEADER size). This patch also fixed another crash issue when running script with Python 3.x and no input parameter given: File "SplitFspBin.py", line 868, in main if args.which in ['rebase', 'split', 'genhdr', 'info']: AttributeError: 'Namespace' object has no attribute 'which' Test: 1. Ran script with both py2 and py3 with no input and no crash observed. 2. Compare the script result before and after the patch are identical. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Improve FSP Python scripts to support 3.x.Ching JenX Cheng2019-08-021-3/+3
| | | | | | | | | | | | | | | | | BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2041 When running with Python 3.x and relying on GenCfgOpt.py to automatically assign UPD offsets, the script crashed because some float type variable not compatible with the operations. Converted those float variable to int to fix these issues. Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Ching JenX Cheng <ching.jenx.cheng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Fix various typosAntoine Cœur2019-07-114-4/+4
| | | | | | | | Fix various typos in IntelFsp2Pkg. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* Revert "FmpDevicePkg: Fix various typos"Antoine Cœur2019-07-114-4/+4
| | | | | | | | This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b. Commit message was incorrect. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* FmpDevicePkg: Fix various typosAntoine Cœur2019-07-094-4/+4
| | | | | | | | Fix one typo in FmpDevicePkg. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: FSP Python scripts to support 3.x.Chasel Chiu2019-07-013-62/+109
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1930 Updated FSP Python scripts to support both 2.x and 3.x. Test: . Verified with Python 2.7.12 and 3.6.6. . Verified tool result is the same before the change. . Both py -2 and py -3 built binary can boot. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.Chasel Chiu2019-06-112-30/+38
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308 Support rebasing FSP 1.x binary. FSP 1.x has single component in binary so not supported by split command and rebase can be done with the same command for rebasing FSP-T component in FSP 2.x image. Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary can be rebased successfully. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Revert FSP 1.x support.Chasel Chiu2019-05-312-38/+30
| | | | | | | | | | This reverts commit: 591b8cb7f3d026d2fa4483c59f3d5fb14be181bf. Will submit again after freeze done. Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.Chasel Chiu2019-05-312-30/+38
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308 Support rebasing FSP 1.x binary. FSP 1.x has single component in binary so not supported by split command and rebase can be done with the same command for rebasing FSP-T component in FSP 2.x image. Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary can be rebased successfully. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-093-21/+3
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Support PCD input from command lineChasel, Chiu2018-10-111-1/+16
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1231 Build system already support override PCD value by command line so add this support to GenCfgOpt.py Also update revision to 0.53 Test: Verified UPD header files generated can reflect different PCD values from --pcd build command input Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Zhu Yonghong <yonghong.zhu@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: remove tailing space from output fileChasel, Chiu2018-09-281-2/+9
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212 UPD header files generated by GenCfgOpt.py may have tailing white space from some of the UPD description in DSC, especially when python script automatically switching lines for long description string. This patch will always remove tailing white space for UPD header files. Test: Verified the patch can remove tailing space in output header files when UPD DSC contains intentional tailing white space. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignmentChasel, Chiu2018-09-281-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211 For reducing maintenance effort, the UPD offset can be automatic assigned by GenCfgOpt.py following by alignment requirements. The usage model as below: . If UPD offset in DSC file are all '*', GenCfgOpt.py will assign offset for all UPD automatically. In this case no need to manually hardcode offset to all UPD in DSC. . If UPD offset in DSC file are all not '*', GenCfgOpt.py will use hardcoded offset directly (original usage model) . Tool does not support mixing scenario so UPD offset in DSC should be all '*' or all hardcoded but not mixed. In auto mode UPD offset will be assigned following natural alignment (size aligned) rule and the whole structure size will align to either 32bits or 64bits depends on maximal UPD size in the structure. Test: Verified by both UPD offset hardcoded or '*' in DSC and generated UPD header files are correct. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCDChasel, Chiu2018-09-281-3/+3
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210 FixedAtBuild PCD is suggested to be used instead of FeatureFlag PCD so extend this tool to support. Also skipped PCDs which commented out by '#'. Test: Verified with FixedAtBuild PCD for including or excluding lines in generated UPD header files successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812bChasel, Chiu2018-09-281-76/+7
| | | | | | | | | | | | Commit formats had issues so reverted 9 commits from IntelFsp2Pkg and IntelFsp2WrapperPkg. Will re-submit them with correct formats. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* GenCfgOpt.py: remove tailing space from output fileChasel, Chiu2018-09-281-2/+9
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212 UPD header files generated by GenCfgOpt.py may have tailing white space from some of the UPD description in DSC, especially when python script automatically switching lines for long description string. This patch will always remove tailing white space for UPD header files. Test: Verified the patch can remove tailing space in output header files when UPD DSC contains intentional tailing white space. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignmentChasel, Chiu2018-09-281-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211 For reducing maintenance effort, the UPD offset can be automatic assigned by GenCfgOpt.py following by alignment requirements. The usage model as below: . If UPD offset in DSC file are all '*', GenCfgOpt.py will assign offset for all UPD automatically. In this case no need to manually hardcode offset to all UPD in DSC. . If UPD offset in DSC file are all not '*', GenCfgOpt.py will use hardcoded offset directly (original usage model) . Tool does not support mixing scenario so UPD offset in DSC should be all '*' or all hardcoded but not mixed. In auto mode UPD offset will be assigned following natural alignment (size aligned) rule and the whole structure size will align to either 32bits or 64bits depends on maximal UPD size in the structure. Test: Verified by both UPD offset hardcoded or '*' in DSC and generated UPD header files are correct. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCDChasel, Chiu2018-09-281-3/+3
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210 FixedAtBuild PCD is suggested to be used instead of FeatureFlag PCD so extend this tool to support. Also skipped PCDs which commented out by '#'. Test: Verified with FixedAtBuild PCD for including or excluding lines in generated UPD header files successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Fix typo in SplitFspBinChasel, Chiu2018-09-211-1/+1
| | | | | | | Signed-off-by: Patrick Georgi <pgeorgi@google.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Clean up source filesLiming Gao2018-06-281-4/+4
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg: SplitFspBin.py to support x64 driversChasel, Chiu2018-06-251-12/+70
| | | | | | | | | | | FSP binary potentially can include X64 drivers to simplify implementation or support new features so update SplitFspBin.py to support x64 image headers. Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg-Tools: GenCfgOpt.py shouldn't include specific UPD nameChasel, Chiu2017-11-081-12/+0
| | | | | | | | | | | PcdSerialIoUartDebugEnable UPD is platform specific and should not be included in generic GenCfgOpt.py script. Remove this and platform DSC should control the default value instead. Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg: Raise exception for invalid BSF optionThomaiyar, Richard Marian2017-03-161-1/+5
| | | | | | | | | | Raise exception for invalid BSF option in GenCfgOpt.py Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* Make [-D Macros] as optional argument for GenCfgOptedk2-devel On Behalf Of rthomaiy2017-03-011-4/+5
| | | | | | | | | Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: 41d739e breaks flat tree buildZeng, Star2016-12-051-5/+8
| | | | | | | | | | | | | | | | | There may be no environment variable PACKAGES_PATH defined in flat tree, then 41d739e breaks flat tree build. This patch is to update GenCfgOpt.py to be compatible with both flat tree and package path build. Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Tested-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
* IntelFsp2Pkg: Add PACKAGES_PATH supportThomaiyar, Richard Marian2016-11-301-3/+7
| | | | | | | | | | | | Add PACKAGES_PATH support in GenCfgOpt.py Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg/Tools: Add PE32 section rebasing supportMaurice Ma2016-10-051-29/+145
| | | | | | | | | | | | The current SplitFspBin.py can only support TE image format rebasing in an FSP binary. This patch adds PE32 image format rebasing support. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Satya Yarlagadda <Satya.p.yarlagadda@intel.com>
* IntelFsp2Pkg: Align #Pragma in UPD header files to rest of EDK2 PkgsSatya Yarlagadda2016-09-201-4/+7
| | | | | | | | | | | | | | | | | | | Changed the GenCfgOpt.py script to insert pragma pack(1) instead of pragma pack (push, 1) in the upd header files generated during fsp build. This is to align with rest of the EDKII pkgs pragma pack usage. Also, this scripts generates UnusedUpdSpace for UPD address gaps. Currently it uses UIN16/UINT32/UINT64 for 2/4/8 bytes instead of UINT8[], thus causing upd space waste to have Natural Alignment. Hence changed the script to use UINT8[] for any unusedUpd fields above 1 byte. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Converted PatchFvUserManual from .docx to .md formatMudusuru, Giri P2016-08-082-0/+123
| | | | | | | | | | | | | | | Converted the the word format of the documentation into markdown format for PatchFv.py V2: updated the commit message descripton Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Converted GenCfgOptUserManual from .docx to .md formatMudusuru, Giri P2016-08-082-0/+353
| | | | | | | | | | | | Converted the the word format of the documentation into markdown format for GenCfgOpt.py Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* InterFsp2Pkg:Tool: Add user manual for SplitFspBin tool.Jiewen Yao2016-06-161-0/+69
| | | | | | | | | | | | | Besides Split FSP binary, we added some more feature to SplitFspBin tool. Here we add user manual for it to describe all usage. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* IntelFsp2Pkg/Tools: Add FSP rebasing function into SplitFspBin toolMaurice Ma2016-06-011-254/+570
| | | | | | | | | | | | Enhanced the SplitFspBin tool in IntelFsp2Pkg to support: - Rebase FSP 2.0 components to a different base address - Display FSP 2.0 information header Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg/Tools: Add BSF bit field support in GenCfgOpt toolMaurice Ma2016-05-271-111/+113
| | | | | | | | | | | | | | The current GenCfgOpt tool does not generate bit fields in BSF. This change will allow bit fields to be created in BSF for a specific FSP UPD item. The argument for the tool is also updated to be in sync with the old usage model in IntelFspPkg. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* Add IntelFsp2Pkg and IntelFsp2WrapperPkg.Jiewen Yao2016-05-135-0/+2775
Add FSP2.0 support. This series of patch is to support FSP2.0 specification at https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf Some major updates include: 1) One FSP binary is separated to multiple components: FSP-T, FSP-M, FSP-S, and optional FSP-O. Each component has its own configuration data region. 2) All FSP-APIs use same UPD format - FSP_UPD_HEADER. 3) Add EnumInitPhaseEndOfFirmware notifyphase. 4) FSP1.1/FSP1.0 compatibility is NOT maintained. 5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg, to indicate that it is for FspWrapper only. IntelFspPkg and IntelFspWrapperPkg will be deprecated. The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg and IntelFsp2WrapperPkg. The old platform can still use IntelFspPkg and IntelFspWrapperPkg for compatibility consideration. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 23:36:51 +0000