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* IntelFsp2Pkg/Library/BaseFspCommonLib: Fix OVERRUN Coverity issueRanbir Singh2023-05-301-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4200 FspData->PerfIdx is getting increased for every call unconditionally in the function SetFspMeasurePoint and hence memory access can happen for out of bound FspData->PerfData[] array entries also. Example - FspData->PerfData is an array of 32 UINT64 entries. Assume a call is made to SetFspMeasurePoint function when the FspData->PerfIdx last value is 31. It gets incremented to 32 at line 400. Any subsequent call to SetFspMeasurePoint functions leads to FspData->PerfData[32] getting accessed which is out of the PerfData array as well as the FSP_GLOBAL_DATA structure boundary. Hence keep array access and index increment inside if block only and return invalid performance timestamp when PerfIdx is invalid. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Ranbir Singh <rsingh@ventanamicro.com> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directlyDuggapu, Chinni B2023-04-182-1/+33
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4412 After shrinking the FSP (FV) component using FMMT, Image size in FSP info header is not in sync with the FV length in FV header. This enhancement helps to patch the FSP image size offset with correct length & can be used to patch any offset directly on the FSP Component Fd. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.Chasel Chiu2023-04-042-43/+48
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. This patch also removed unnecessary LoadCheck code after supporting CPU microcode already loaded scenario. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.Chasel Chiu2023-04-042-1/+27
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395 FSP specification defines the TempRamInit API preserved register list which including EBX/RBX, however current implementation unexpectedly overriding EBX/RBX register that should be fixed. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Fix NASM X64 build warnings.Chasel Chiu2023-03-242-11/+9
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-105-5/+0
| | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Fix GCC Compiler warning.S, Ashraf Ali2023-03-101-0/+1
| | | | | | | | | | | | | | | Function definition should match with declaration. [-Wlto-type-mismatch] Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-TKuo, Ted2022-11-115-46/+55
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: FSP should support input UPD as NULL.Chasel Chiu2022-11-043-34/+91
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114 FSP specification supports input UPD as NULL cases which FSP will use built-in UPD region instead. FSP should not return INVALID_PARAMETER in such cases. In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed to platform FSP code to consume. In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating corresponding pointer field in FspGlobalData. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com>
* IntelFsp2Pkg: Update Function header to support IA32/X64.Chasel Chiu2022-11-022-8/+8
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4126 Common functions will have either 32bit or 64bit instances which having different return code size. Function header should support both scenarios. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add CI YAML fileMichael Kubacki2022-10-041-0/+90
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048 Adds IntelFsp2Pkg to the list of supported build packages for edk2 CI and defines an initial set of CI configuration options. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney>
* IntelFsp2Pkg/BaseFspMultiPhaseLib: Replace duplicate GUIDMichael Kubacki2022-10-041-1/+1
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048 The FILE_GUID for this library instance file is a duplicate of Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf. This change replaces the duplicated GUID value with a unique GUID. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney>
* IntelFsp2Pkg: Fix code formatting errorsMichael Kubacki2022-10-043-9/+10
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048 This package did not have CI enabled so code changes were merged that fail uncrustify formatting. This change updates those files to include uncustify formatting. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney>
* IntelFsp2Pkg: Fix FspSecCoreI build failure.Chasel Chiu2022-09-152-0/+22
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4049 Link error occurred in certain compiling environment when building FspSecCoreI: unresolved external symbol _TempRamInitApi. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: NvsBufferPtr is missing in Fsp24ApiEntryM.nasmKuo, Ted2022-09-152-2/+4
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4063 Added NvsBufferPtr to FSPM_UPD_COMMON_FSP24 in Fsp24ApiEntryM.nasm to align with FSP 2.4 SPEC. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.Chasel Chiu2022-09-0710-0/+969
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916 Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM. For backward compatibility, new INF are created for new modules. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface.Chasel Chiu2022-08-3110-29/+450
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916 Provide FSP 2.4 MultiPhase interface and scripts support. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: FSPM_ARCH2_UPD mismatching bug.Chasel Chiu2022-08-152-2/+4
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4019 FSPM_ARCH2_UPD in FspApiEntryM.nasm was not up-to-date and should be fixed for both IA32 and X64 builds. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Fix GenCfgOpt bug for FSPI_UPD support.Chasel Chiu2022-07-291-1/+1
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Fixed a logic bug in GenCfgOpt.py to skip FSPI_UPD when platforms do not support. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: FSPI_UPD is not mandatory.Chasel Chiu2022-07-282-26/+31
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 FSPI_UPD is required only When platforms implemented FSP_I component. Updated the scripts to allow FSPI_UPD not present scenario. Also fixed FSP_GLOBAL_DATA structure alignment issue and unnecessary non-backward compatibility change in previous FSP_I patch. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Add FSPI_ARCH_UPD.Chasel Chiu2022-07-224-11/+85
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Adding the missing FSPI_ARCH_UPD, FSP_GLOBAL_DATA_VERSION bumpping up, and some comments for clarification. Also fixed a bug in SplitFspBin.py for FSP-I support. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.Hongbin1 Zhang2022-07-2013-53/+245
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Add FSP-I API entry point for SMM support. Also update 64bit API entry code to assign ApiIdx to RAX to avoid confusion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Support 64bit FspResetType for X64 build.Chasel Chiu2022-07-194-36/+41
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999 FspResetType will be either 32bit or 64 bit basing on the build type. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add Definition of EDKII_PEI_VARIABLE_PPINate DeSimone2022-07-182-1/+202
| | | | | | | | Adds definition of EDKII_PEI_VARIABLE_PPI. Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Update SEC_IDT_TABLE structKuo, Ted2022-07-144-20/+21
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957 The reserved IDT table size in SecCore is too small for X64. Changed the type of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have sufficient size reserved in IdtTable for X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling ConventionDuggapu, Chinni B2022-05-312-19/+48
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 This API accept one parameter using RCX and this is consumed in mutiple sub functions. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: cbduggap <chinni.b.duggapu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add FSP 2.3 header supportLoo, Tung Lun2022-05-312-8/+69
| | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3921 This patch adds a couple of fields supported in FSP 2.3 header from both header generation and tool support perspective. Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add CpuLib to module INFs that depend on UefiCpuLibYu Pu2022-05-062-0/+2
| | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build failure, add CpuLib dependency to all modules that depend on UefiCpuLib. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64Ted Kuo2022-04-164-4/+79
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: FspSecCore support for X64Ted Kuo2022-04-1618-19/+1493
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64Ted Kuo2022-04-162-17/+38
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support both IA32 and X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64Ted Kuo2022-04-164-24/+252
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64. 2.Added FSPx_UPD_COMMON_FSP24 structures. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: X64 compatible changes to support PEI in 64bitTed Kuo2022-04-1610-41/+45
| | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint, SwapStack and PEI_CORE_ENTRY. 2.Treat both MAX_ADDRESS and MAX_UINT32 as invalid address for FSP global data in FspApiCallingCheck(). 3.Changed AsmReadEsp to AsmReadStackPointer. 4.Changed the type of the return value of AsmReadStackPointer from UINT32 to UINTN. 5.Changed the type of TemporaryMemoryBase, PermenentMemoryBase and BootLoaderStack from UINT32 to UINTN. 6.Some type casting to pointers are UINT32. Changed them to UINTN to accommodate both IA32 and X64. 7.Corrected some typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: BaseFspCommonLib Support for X64Kuo, Ted2022-03-225-32/+45
| | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3867 Add BaseFspCommonLib Support for X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: BaseFspSwitchStackLib Support for X64Kuo, Ted2022-03-174-5/+147
| | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3832 Add BaseFspSwitchStackLib Support for X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: BaseFspDebugLibSerialPort Support for X64Kuo, Ted2022-03-173-16/+53
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3833 Add BaseFspDebugLibSerialPort Support for X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/FspSecCore: ExtendedImageRevision was not printed.Chasel Chiu2021-12-291-3/+7
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3791 ExtendedImageRevision should be printed when Header revision >= 6. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Apply uncrustify changesMichael Kubacki2021-12-0733-899/+894
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the IntelFsp2Pkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg SplitFspBin.py: Correct file name in file headerZeng, Star2021-11-011-1/+1
| | | | | | | | | Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: adopt FSP 2.3 specification.Chasel Chiu2021-10-271-22/+44
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3705 FSP 2.3 has updated FSP_INFO_HEADER to support ExtendedImageRevision and SplitFspBin.py needs to support it. Also updated script to display integer value basing on length. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Adopt FSP 2.3 specification.Chasel Chiu2021-10-043-1/+57
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3674 Add ExtendedImageRevision in FSP_INFO_HEADER structure, also add FSP_NON_VOLATILE_STORAGE_HOB2 header. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Support Config File and Binary delta comparisonLoo, Tung Lun2021-09-012-14/+150
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3567 This patch is to enable config editor to have a new feature that can spell out the delta between the default configuration files' data, such as YAML and BSF, against the data stored in the binary. This can help users understand and track the difference when modifications are made. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add search function for Config EditorLoo, Tung Lun2021-07-153-13/+76
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3482 This patch adds a search function in the Config Editor GUI at the top right corner. Once users key in the words to search, it will look for the option containing the string in the same page and display it. It also includes a README for this function. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: BaseCacheLib EfiProgramMtrr MtrrNumber Should be UINT32S, Ashraf Ali2021-07-142-4/+4
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3485 CacheLib EfiProgramMtrr Function takes MTRR number as a input parameter, in the function the parameter is defined as UINTN were as the caller calling MTTR number in UINT32. Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Digant H Solanki <digant.h.solanki@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: PatchFv parseInfFile function modificationS, Ashraf Ali2021-07-081-5/+13
| | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476 parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the address found still it's continues to read the complete inf file which is not required. once the EFI_BASE_ADDRESS read from the INF no need to read the INF further. MSFT compiler can generate the map file address 8 or 16 based on which architecture the INF is compiler. currently it's support for IA32, modified the patchfv to support for all. modification of few typo errors in parseModMapFile, getCurr function required verification : Working Fine Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add Config Editor tool supportLoo, Tung Lun2021-06-307-293/+7337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3396 This is a GUI interface that can be used by users who would like to change configuration settings directly from the interface without having to modify the source. This tool depends on Python GUI tool kit Tkinter. It runs on both Windows and Linux. The user needs to load the YAML file along with DLT file for a specific board into the ConfigEditor, change the desired configuration values. Finally, generate a new configuration delta file or a config binary blob for the newly changed values to take effect. These will be the inputs to the merge tool or the stitch tool so that new config changes can be merged and stitched into the final configuration blob. This tool also supports binary update directly and display FSP information. It is also backward compatible for BSF file format. Running Configuration Editor: python ConfigEditor.py Co-authored-by: Maurice Ma <maurice.ma@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: YAML script bug fixLoo, Tung Lun2021-05-182-3/+11
| | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3395 This patch fixes the issue observed during BSF file to YAML file conversion. It also addresses the issue during multibyte array data conversion check, for example the data representation of 0xFFFF instead of 0xFF, 0xFF would be thrown exception "Array size is not proper" without this patch. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Consume MdeLibs.dsc.inc for RegisterFilterLibDandan Bi2021-03-312-1/+5
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 MdeLibs.dsc.inc was added for some basic/default library instances provided by MdePkg and RegisterFilterLibNull Library was also added into it as the first version of MdeLibs.dsc.inc. So update platform dsc to consume MdeLibs.dsc.inc for RegisterFilterLibNull which will be consumed by IoLib and BaseLib. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add YAML file generation supportLoo Tung Lun2021-02-0911-132/+2421
| | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3091 Add support for YAML format file generation in addition to current BSF structure. Configuration of YAML format output will be supported by an open source ConfigEditor. Reference to YAML code, test and ConfigEditor is at https://github.com/joshloo/fsp_yaml_cfg/tree/master/Tools A unit test is also added in Tests folder. This test compares the generated yaml file against the expected output to know if it is constructing the yaml data structure as expected. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Support FSP private temporary memory.Chasel Chiu2021-01-073-6/+15
| | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3153 In FSP the temporary memory provided by bootloader typically will be totally given to PeiCore as Heap, but in some cases FSP may have to reserve some more temporary memory for private usage. This commit adds this flexibility for FSP to reserve some temporary memory before giving them to PeiCore. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:34:59 +0000