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* Remove IntelSiliconPkg that has been moved to edk2-platform repoLiming Gao2019-06-2556-12948/+0
| | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1890 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
* IntelSiliconPkg/IntelVTdDxe: Do global invalidation before bootZhichao Gao2019-05-102-2/+43
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1547 V2: Abandon V1. Do global invalidation of context-cache and IOTLB at ExitBootServices. V1: Only doing IOTLB invalidation would cause a BSOD 'DRIVER_VERIFIER_DMA_VIOLATION' while changing the second level page entry's attributes. So always do the global invalidation of context-cache and IOTLB. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelSiliconPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0954-377/+54
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* IntelSiliconPkg/IntelSiliconPkg.dsc: Add a driver to buildBret Barkelew2019-03-261-0/+1
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1647 Add a driver MicrocodeFlashAccessLibNull.inf to the [Components] section to make sure it would build correctly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* IntelSiliconPkg/MicrocodeUpdate: Fix incorrect checksum issueChen A Chen2019-02-251-1/+9
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1020 The same issue has fixed in UefiCpuPkg/Microcode.c file. Please reference b6f67b4d58b81f12f63f5f8c94cf8af3600297ab to get more detail information. Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* IntelSiliconPkg/MicrocodeUpdateDxe: Error message enhancementShenglei Zhang2019-02-201-1/+1
| | | | | | | | | | | | The error message of ExtendedTableCount is not clear. Add the count number into the debug message. https://bugzilla.tianocore.org/show_bug.cgi?id=1500 Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
* IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 StructureSolanki, Digant H2019-01-311-4/+4
| | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1454 Based on latest IGD OpRegion Spec, IGD_OPREGION_MBOX3 needs to be updated with two new members : Physical Address of Raw VBT Data (RVDA) and Size of Raw VBT Data (RVDS) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* IntelSiliconPkg VTdDxe: Report status code for VTd errorStar Zeng2018-10-254-0/+10
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1273 Current code only uses DEBUG() for VTd error. This patch updates to also report status code for VTd error. Test done: Created case that has VTd error and confirmed the error status code could be reported as expected. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg VTdDxe: Option to force no early access attr requestStar Zeng2018-10-253-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1272 To have high confidence in usage for platform, add option (BIT2 of PcdVTdPolicyPropertyMask) to force no IOMMU access attribute request recording before DMAR table is installed. Check PcdVTdPolicyPropertyMask BIT2 before RequestAccessAttribute() and ProcessRequestedAccessAttribute(), then RequestAccessAttribute(), ProcessRequestedAccessAttribute() and mAccessRequestXXX variables could be optimized by compiler when PcdVTdPolicyPropertyMask BIT2 = 1. Test done: 1: Created case that has IOMMU access attribute request before DMAR table is installed, ASSERT was triggered after setting PcdVTdPolicyPropertyMask BIT2 to 1. 2. Confirmed RequestAccessAttribute(), ProcessRequestedAccessAttribute() and mAccessRequestXXX variables were optimized by compiler after setting PcdVTdPolicyPropertyMask BIT2 to 1. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Use new EfiLocateFirstAcpiTable()Star Zeng2018-09-271-133/+3
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch updates IntelVTdDxe to use new EfiLocateFirstAcpiTable() and remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Check HeaderType if func 0 is implementedStar Zeng2018-09-171-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1169 Current code checks HeaderType of Function 0 even Function 0 is not implemented. HeaderType value will be 0xFF if Function 0 is not implemented, then MaxFunction will be set to PCI_MAX_FUNC + 1. The code can be optimized to only check HeaderType if Function 0 is implemented. Test done: With this patch, the result is same with the result after the patch at https://lists.01.org/pipermail/edk2-devel/2018-September/029623.html. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Tomson Chang <tomson.chang@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Optimize when func 0 is not implementedStar Zeng2018-09-171-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1169 PCI spec: They are also required to always implement function 0 in the device. Implementing other functions is optional and may be assigned in any order (i.e., a two-function device must respond to function 0 but can choose any of the other possible function numbers (1-7) for the second function). This patch updates ScanPciBus() to not scan other functions if function 0 is not implemented. Test done: Added debug code below in the second loop of ScanPciBus(), compared the debug logs with and without this patch, many non-0 unimplemented functions are skipped correctly. DEBUG (( DEBUG_INFO, "%a() B%02xD%02xF%02x VendorId: %04x DeviceId: %04x\n", __FUNCTION__, Bus, Device, Function, VendorID, DeviceID )); Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Tomson Chang <tomson.chang@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: Amy Chan <amy.chan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg: Removing ipf which is no longer supported from edk2.Chen A Chen2018-09-133-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: <Jiewen.yao@intel.com>
* IntelSiliconPkg: Clean up source filesLiming Gao2018-06-281-1/+1
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Fix incorrect code to clear VTd errorStar Zeng2018-06-061-2/+4
| | | | | | | | | | | | | | | | According to VTd spec, Software writes the value read from this field (F) to Clear it. But current code is using 0 to clear the field, that is incorrect. And R_FSTS_REG register value clearing should be not in the for loop. Without this patch, we will see same VTd error message appears again and again after it occurs first time. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg MicrocodeUpdateDxe: Honor FIT tableStar Zeng2018-05-094-29/+601
| | | | | | | | | | | | It is the second step for https://bugzilla.tianocore.org/show_bug.cgi?id=540. V2: Use error handling instead of ASSERT for FIT table checking result. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg MicrocodeUpdate: Fix typo EFI_SECURITY_VIOLATIOStar Zeng2018-04-252-10/+10
| | | | | | | | | Fix typo EFI_SECURITY_VIOLATIO to EFI_SECURITY_VIOLATION. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/Vtd: Add more debug info.Jiewen Yao2018-03-201-1/+1
| | | | | | | | | Add more debug info for reason code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/Vtd: Add missing dump in ExtContext.Jiewen Yao2018-03-121-0/+1
| | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/Vtd: Add DMA_CTRL_PLATFORM_OPT_IN_FLAG dumpJiewen Yao2018-03-122-0/+8
| | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/Vtd: Add MapHandleInfo in VtdDxe.Jiewen Yao2018-03-092-13/+144
| | | | | | | | | | This information is to record which device requested which DMA buffer. It can be used for DMA buffer analysis. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg VTdPmrPei: Add PcdVTdPeiDmaBufferSize(S3)Star Zeng2018-03-063-7/+22
| | | | | | | | | | Add PcdVTdPeiDmaBufferSize(S3) to replace the hard coded value TOTAL_DMA_BUFFER_SIZE and TOTAL_DMA_BUFFER_SIZE_S3 in IntelVTdPmrPei. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg VTdPmrPei: Return SUCCESS when Mapping == NULL in UnmapStar Zeng2018-03-061-2/+2
| | | | | | | | | | | | | | | NULL is returned to Mapping when Operation is BusMasterCommonBuffer or BusMasterCommonBuffer64 in PeiIoMmuMap(). So Mapping == NULL is valid when calling PeiIoMmuUnmap(). 940dbd071e9f01717236af236740aa0da716805f wrongly changed EFI_SUCCESS to EFI_INVALID_PARAMETER when Mapping == NULL in PeiIoMmuUnmap(). This patch is to correct it. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Install IOMMU PPI for pre-memory phaseStar Zeng2018-02-071-11/+66
| | | | | | | | | | | Install IOMMU PPI for pre-memory phase and return EFI_NOT_AVAILABLE_YET to indicate that DMA protection has been enabled, but DMA buffer are not available to be allocated yet. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Install IoMmu PPI before enabling PMRStar Zeng2018-02-071-34/+29
| | | | | | | | | | | Then the consumer of IoMmu PPI has opportunity to get granted DMA buffer (by callback) to replace old buffer before it is forbidden by enabling PMR. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg PlatformVTdSampleDxe: State it is only for dev/debugStar Zeng2018-02-072-2/+8
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/MicrocodeUpdateDxe: Refine debug messagesHao Wu2018-02-021-5/+14
| | | | | | | | | | Refine the debug messages during the verification of microcode to make them more clear. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg MicrocodeUpdateDxe: TotalSize must be multiples of 1KBStar Zeng2018-01-261-4/+15
| | | | | | | | | | | | | TotalSize must be multiples of 1024 bytes (1 KBytes) according to SDM. Also enhance the debug message for DataSize that must be multiples of DWORDs. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Fix flush cache issueStar Zeng2018-01-241-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes flush cache issue in CreateSecondLevelPagingEntryTable(). We found some video cards still not work even they have been added to the exception list. In CreateSecondLevelPagingEntryTable(), the check "(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done" will be executed, then the FlushPageTableMemory operations at the end of the function will be skipped. Instead of "goto Done", this patch uses "break" to break the for loops, then the FlushPageTableMemory operations at the end of the function could have opportunity to be executed. The patch also fixes a miscalculation for Lvl3End. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Fix DMA does not work issueStar Zeng2018-01-181-3/+7
| | | | | | | | | | Fix DMA does not work issue when system memory is not greater than 4G. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Get high top by host address widthStar Zeng2018-01-173-178/+5
| | | | | | | | | Get high top by host address width instead of resource HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMaskStar Zeng2018-01-173-5/+1
| | | | | | | | | | mVtdHostAddressWidthMask is not been used at all, its definition and related code could be removed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Use HostAddressWidth in DMAR correctlyStar Zeng2018-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | According to VTd spec, HostAddressWidth + 1 should be used as the real host address width value. Host Address Width: This field indicates the maximum DMA physical addressability supported by this platform. The system address map reported by the BIOS indicates what portions of this addresses are populated. The Host Address Width (HAW) of the platform is computed as (N+1), where N is the value reported in this field. For example, for a platform supporting 40 bits of physical addressability, the value of 100111b is reported in this field. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.LimitStar Zeng2018-01-171-3/+3
| | | | | | | | | | | | | According to VTd spec, the real hardware decoded limit should be PHMR/PLMR.Limit value + alignment value. "Bits N:0 of the limit register are decoded by hardware as all 1s." Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Fix potential NULL pointer dereferenceStar Zeng2018-01-161-3/+3
| | | | | | | | | | | | The implementation of MdeModulePkg\Universal\Acpi\AcpiTableDxe reserves first entry of RSDT/XSDT to FADT, the first entry value is 0 when FADT is not installed. So the RSDT/XSDT parsing code should check the entry value first before checking the table signature. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Support early SetAttributes()Star Zeng2018-01-054-3/+202
| | | | | | | | | Support early SetAttributes() before DMAR table is installed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operationStar Zeng2018-01-054-31/+26
| | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Signal AcpiNotificationFunc() initiallyStar Zeng2018-01-052-4/+15
| | | | | | | | | | Signal AcpiNotificationFunc() initially for the case that DMAR table has been installed when creating event. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLength & 0x3)!=0Star Zeng2017-12-211-2/+2
| | | | | | | | | | | | | | | | | | The first 48 bytes contain the microcode update header. DataSize must be a multiple of DWORDs. TotalSize is always a multiple of 1024. Both size of CPU_MICROCODE_EXTENDED_TABLE_HEADER and CPU_MICROCODE_EXTENDED_TABLE are multiple of DWORDs. So (ExtendedTableLength & 0x3)!=0 should be (ExtendedTableLength & 0x3)==0. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
* IntelSilicon: Correct function description for AllocateBufferStar Zeng2017-12-123-3/+3
| | | | | | | | | | | DUAL_ADDRESS_CYCLE is missing in the EFI_UNSUPPORTED return status description. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* IntelSiliconPkg: Update MicrocodeUpdate build path in dscStar Zeng2017-12-011-2/+2
| | | | | | | | | | | That was missed in 43e12eeac8b125165b8a93c3501925a8893544ef. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg: Update MicrocodeUpdate to build with the packageStar Zeng2017-11-303-4/+7
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 This is after patch "IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkg". Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkgStar Zeng2017-11-3019-1/+2723
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 To consume FIT table for Microcode update, UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe needs to be updated to consume IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h, but UefiCpuPkg could not depend on IntelSiliconPkg. Since the Microcode update feature is specific to Intel, we can first move the Microcode update feature code from UefiCpuPkg to IntelSiliconPkg [first step], then update the code to consume FIT table [second step]. This patch series is for the first step. Note: No any code change in this patch, just move. Next patch will update MicrocodeUpdate to build with the package. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* IntelSiliconPkg IntelVTdDxe: Do not SetupVtd againStar Zeng2017-11-233-5/+10
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Tested-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Use ACPI table event to get DMAR tableStar Zeng2017-11-064-30/+46
| | | | | | | | | | | Use ACPI table event to get DMAR table instead of using ACPI SDT notification as ACPI SDT is optional and the default value of PcdInstallAcpiSdtProtocol is FALSE in MdeModulePkg.dec. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/VtdPeiSample: Add premem support.Jiewen Yao2017-10-302-35/+201
| | | | | | | | | | | | | | Before memory is ready, this sample produces one VTd engine. After memory and silicon is initialized, this sample produces both IGD VTd engine and all-rest VTd engine by reinstall the FV_INFO_PPI. This update is to demonstrate how to support pre-mem VTd usage. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VtdPmrPei: Add premem support.Jiewen Yao2017-10-306-596/+1358
| | | | | | | | | | | | | | Remove memory discovered dependency to support both premem VTD_INFO_PPI and postmem VTD_INFO_PPI. If VTD_INFO_PPI is installed before memory is ready, this driver protects all memory region. If VTD_INFO_PPI is installed or reinstalled after memory is ready, this driver allocates DMA buffer and protect rest. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/VTdDxe: return unsupported for exceptionlistJiewen Yao2017-10-301-2/+3
| | | | | | | | | | Since the exception list is not a recommended way, we returns EFI_UNSUPPORTED in the sample code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.Jiewen Yao2017-10-301-2/+2
| | | | | | | | | | Change ExitBootServices TPL to CALLBACK, so that a device can disable BME before IOMMU grants access right. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg IntelVTdDxe: use gEfiAcpi10TableGuid for ACPI 1.0Star Zeng2017-10-262-2/+2
| | | | | | | | | | | | According to definition (Acpi.h and MdePkg.dec), gEfiAcpiTableGuid = gEfiAcpi20TableGuid, and the code is trying to parse ACPI 2.0 first and then ACPI 1.0, but it uses gEfiAcpiTableGuid wrongly for ACPI 1.0, this patch is to fix it. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>