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* IntelSiliconPkg IntelVTdPmrPei: Install IOMMU PPI for pre-memory phaseStar Zeng2018-02-071-11/+66
| | | | | | | | | | | Install IOMMU PPI for pre-memory phase and return EFI_NOT_AVAILABLE_YET to indicate that DMA protection has been enabled, but DMA buffer are not available to be allocated yet. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Install IoMmu PPI before enabling PMRStar Zeng2018-02-071-34/+29
| | | | | | | | | | | Then the consumer of IoMmu PPI has opportunity to get granted DMA buffer (by callback) to replace old buffer before it is forbidden by enabling PMR. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg PlatformVTdSampleDxe: State it is only for dev/debugStar Zeng2018-02-072-2/+8
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/MicrocodeUpdateDxe: Refine debug messagesHao Wu2018-02-021-5/+14
| | | | | | | | | | Refine the debug messages during the verification of microcode to make them more clear. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg MicrocodeUpdateDxe: TotalSize must be multiples of 1KBStar Zeng2018-01-261-4/+15
| | | | | | | | | | | | | TotalSize must be multiples of 1024 bytes (1 KBytes) according to SDM. Also enhance the debug message for DataSize that must be multiples of DWORDs. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Fix flush cache issueStar Zeng2018-01-241-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes flush cache issue in CreateSecondLevelPagingEntryTable(). We found some video cards still not work even they have been added to the exception list. In CreateSecondLevelPagingEntryTable(), the check "(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done" will be executed, then the FlushPageTableMemory operations at the end of the function will be skipped. Instead of "goto Done", this patch uses "break" to break the for loops, then the FlushPageTableMemory operations at the end of the function could have opportunity to be executed. The patch also fixes a miscalculation for Lvl3End. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Fix DMA does not work issueStar Zeng2018-01-181-3/+7
| | | | | | | | | | Fix DMA does not work issue when system memory is not greater than 4G. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Get high top by host address widthStar Zeng2018-01-173-178/+5
| | | | | | | | | Get high top by host address width instead of resource HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMaskStar Zeng2018-01-173-5/+1
| | | | | | | | | | mVtdHostAddressWidthMask is not been used at all, its definition and related code could be removed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Use HostAddressWidth in DMAR correctlyStar Zeng2018-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | According to VTd spec, HostAddressWidth + 1 should be used as the real host address width value. Host Address Width: This field indicates the maximum DMA physical addressability supported by this platform. The system address map reported by the BIOS indicates what portions of this addresses are populated. The Host Address Width (HAW) of the platform is computed as (N+1), where N is the value reported in this field. For example, for a platform supporting 40 bits of physical addressability, the value of 100111b is reported in this field. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.LimitStar Zeng2018-01-171-3/+3
| | | | | | | | | | | | | According to VTd spec, the real hardware decoded limit should be PHMR/PLMR.Limit value + alignment value. "Bits N:0 of the limit register are decoded by hardware as all 1s." Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Fix potential NULL pointer dereferenceStar Zeng2018-01-161-3/+3
| | | | | | | | | | | | The implementation of MdeModulePkg\Universal\Acpi\AcpiTableDxe reserves first entry of RSDT/XSDT to FADT, the first entry value is 0 when FADT is not installed. So the RSDT/XSDT parsing code should check the entry value first before checking the table signature. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Support early SetAttributes()Star Zeng2018-01-054-3/+202
| | | | | | | | | Support early SetAttributes() before DMAR table is installed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operationStar Zeng2018-01-054-31/+26
| | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Signal AcpiNotificationFunc() initiallyStar Zeng2018-01-052-4/+15
| | | | | | | | | | Signal AcpiNotificationFunc() initially for the case that DMAR table has been installed when creating event. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLength & 0x3)!=0Star Zeng2017-12-211-2/+2
| | | | | | | | | | | | | | | | | | The first 48 bytes contain the microcode update header. DataSize must be a multiple of DWORDs. TotalSize is always a multiple of 1024. Both size of CPU_MICROCODE_EXTENDED_TABLE_HEADER and CPU_MICROCODE_EXTENDED_TABLE are multiple of DWORDs. So (ExtendedTableLength & 0x3)!=0 should be (ExtendedTableLength & 0x3)==0. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
* IntelSilicon: Correct function description for AllocateBufferStar Zeng2017-12-123-3/+3
| | | | | | | | | | | DUAL_ADDRESS_CYCLE is missing in the EFI_UNSUPPORTED return status description. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* IntelSiliconPkg: Update MicrocodeUpdate build path in dscStar Zeng2017-12-011-2/+2
| | | | | | | | | | | That was missed in 43e12eeac8b125165b8a93c3501925a8893544ef. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg: Update MicrocodeUpdate to build with the packageStar Zeng2017-11-303-4/+7
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 This is after patch "IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkg". Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkgStar Zeng2017-11-3019-1/+2723
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 To consume FIT table for Microcode update, UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe needs to be updated to consume IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h, but UefiCpuPkg could not depend on IntelSiliconPkg. Since the Microcode update feature is specific to Intel, we can first move the Microcode update feature code from UefiCpuPkg to IntelSiliconPkg [first step], then update the code to consume FIT table [second step]. This patch series is for the first step. Note: No any code change in this patch, just move. Next patch will update MicrocodeUpdate to build with the package. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* IntelSiliconPkg IntelVTdDxe: Do not SetupVtd againStar Zeng2017-11-233-5/+10
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Tested-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Use ACPI table event to get DMAR tableStar Zeng2017-11-064-30/+46
| | | | | | | | | | | Use ACPI table event to get DMAR table instead of using ACPI SDT notification as ACPI SDT is optional and the default value of PcdInstallAcpiSdtProtocol is FALSE in MdeModulePkg.dec. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/VtdPeiSample: Add premem support.Jiewen Yao2017-10-302-35/+201
| | | | | | | | | | | | | | Before memory is ready, this sample produces one VTd engine. After memory and silicon is initialized, this sample produces both IGD VTd engine and all-rest VTd engine by reinstall the FV_INFO_PPI. This update is to demonstrate how to support pre-mem VTd usage. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VtdPmrPei: Add premem support.Jiewen Yao2017-10-306-596/+1358
| | | | | | | | | | | | | | Remove memory discovered dependency to support both premem VTD_INFO_PPI and postmem VTD_INFO_PPI. If VTD_INFO_PPI is installed before memory is ready, this driver protects all memory region. If VTD_INFO_PPI is installed or reinstalled after memory is ready, this driver allocates DMA buffer and protect rest. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/VTdDxe: return unsupported for exceptionlistJiewen Yao2017-10-301-2/+3
| | | | | | | | | | Since the exception list is not a recommended way, we returns EFI_UNSUPPORTED in the sample code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.Jiewen Yao2017-10-301-2/+2
| | | | | | | | | | Change ExitBootServices TPL to CALLBACK, so that a device can disable BME before IOMMU grants access right. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg IntelVTdDxe: use gEfiAcpi10TableGuid for ACPI 1.0Star Zeng2017-10-262-2/+2
| | | | | | | | | | | | According to definition (Acpi.h and MdePkg.dec), gEfiAcpiTableGuid = gEfiAcpi20TableGuid, and the code is trying to parse ACPI 2.0 first and then ACPI 1.0, but it uses gEfiAcpiTableGuid wrongly for ACPI 1.0, this patch is to fix it. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/VtdInfoSample: Fix IGD RMRR memory.Jiewen Yao2017-10-241-1/+1
| | | | | | | | | Fix a calculation problem in IGD RMRR memory. Cc: Zeng Star <zeng.star@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Zeng Star <zeng.star@intel.com>
* IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3Jiewen Yao2017-09-232-2/+59
| | | | | | | | | | In S3 resume, before system transfer to waking vector, the VTdPmr need turn off VTd protection based upon VTdPolicy. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/dec: Clarify VTdPolicy.Jiewen Yao2017-09-231-2/+2
| | | | | | | | | Clarify the VTdPolicy is for both PEI and DXE. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.Jiewen Yao2017-09-232-4/+9
| | | | | | | | | Make sure the context table are flush to memory. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTdInfoSample: Add RMRR table.Jiewen Yao2017-09-202-10/+149
| | | | | | | | | | Let system report RMRR table for the platform support PEI graphic. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.Jiewen Yao2017-09-203-29/+624
| | | | | | | | | | | | | | | | | | | In order to support PEI graphic, we let VTdPmrPei driver parse DMAR table RMRR entry and allow the UMA access. If a system has no PEI IGD, no RMRR is needed. The behavior is unchanged. If a system has PEI IGD, it must report RMRR in PEI phase. The PeiVTdPrm will program the IGD VTd engine to skip the RMRR region, and program the rest PCI VTd engine to skip the another DMA buffer allocated in PEI phase for other device driver. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.Jiewen Yao2017-09-201-11/+14
| | | | | | | | | | | | | We notice that there is real usage in PEI to show the graphic out. As such we need report RMRR table in PEI to let VTdPmrPei driver skip the IGD UMA region. Now the VTD_INFO PPI uses the same DMAR data structure. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTdPei: Fix Linux build error.Jiewen Yao2017-09-183-3/+3
| | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg/PlatformIntelVTdInfoSamplePei: Move to feature dir.Jiewen Yao2017-09-175-1/+1
| | | | | | | | | | Move PlatformIntelVTdInfoSamplePei to Feature/VTd/. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir.Jiewen Yao2017-09-177-1/+1
| | | | | | | | | | Move IntelVTdPmrPei to Feature/VTd/IntelVTdPmrPei. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/PlatformVTdSampleDxe: Move to feature dir.Jiewen Yao2017-09-175-1/+1
| | | | | | | | | | Move PlatformVTdSampleDxe to Feature/VTd/PlatformVTdSampleDxe. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/IntelVTdDxe: Move to feature dir.Jiewen Yao2017-09-1713-1/+1
| | | | | | | | | | Move IntelVTdDxe to Feature/VTd/IntelVTdDxe. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei.Jiewen Yao2017-09-161-0/+1
| | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg: Add PlatformVTdInfoSamplePei.Jiewen Yao2017-09-164-0/+156
| | | | | | | | | This is a sample driver to produce VTD_INFO PPI. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/dsc: Add IntelVTdPmrPeim.Jiewen Yao2017-09-161-0/+9
| | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg: Add IntelVTdPmrPei.Jiewen Yao2017-09-166-0/+1096
| | | | | | | | | | | | | | | This PEIM is to produce IOMMU_PPI, so that PEI device driver can have better DAM management. This PEIM will setup VTD PMR register to protect most DRAM. It allocates a big chunk DMA buffer in the entrypoint, and only use this buffer for DMA. Any other region is DMA protected. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/dec: Add VTD_INFO PPI GUIDJiewen Yao2017-09-161-0/+3
| | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/include: Add VTD_INFO PPI.Jiewen Yao2017-09-161-0/+40
| | | | | | | | | | | | | This VTD_INFO_PPI is to provide VTD information in PEI. As such, we can have a generic VTd driver. It is a lightweight version DMAR table, but it does not contain PCI device information. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTdDxe: Disable PMRJiewen Yao2017-09-161-1/+50
| | | | | | | | | | When VTd translation is enabled, PMR can be disable. Or the DMA will be blocked by PMR. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/Vtd.h: Add definition for PMR.Jiewen Yao2017-09-161-0/+6
| | | | | | | | | Add missing PMR definition in VTd spec. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/IntelVtd: Consume VTd policy PCDJiewen Yao2017-09-073-2/+12
| | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/dec: Add VTd policy PCDJiewen Yao2017-09-071-0/+6
| | | | | | | | | | | | | | BIT0: This is to control if a platform wants to enable VTd based protection during boot. BIT1: This is to control if a platform wants to keep VTd enabled at ExitBootService. The default configuration is BIT0:1, BIT1:0. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/VTd: improve debug message.Jiewen Yao2017-09-061-2/+2
| | | | | | | | | | Add /n for debug message to make error more readable. Suggested-by: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 06:02:49 +0000