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* MdeModulePkg/scsi :Coverity scan flags multiple issues in edk2-stable202205Sivaparvathi C2022-11-042-10/+19
| | | | | | | | | Added changes to resolve the SCSI driver Coverity issues. Cc: Vasudevan Sambandan <vasudevans@ami.com> Cc: Sundaresan Selvaraj <sundaresans@ami.com> Signed-off-by: Sivaparvathi chellaiah <sivaparvathic@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/ScsiDiskDxe: Update proper device name for ScsiDisk driveCheripally Gopi2022-10-313-2/+62
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4100 ScsiDiskDxe driver updates ControllerNameTable with common string "SCSI Disk Device" for all SCSI disks. Due to this, when multiple SCSI disk devices connected, facing difficulty in identifying correct SCSI disk device. As per SCSI spec, standard Inquiry Data is having the fields to know Vendor and Product information. Updated "ControllerNameTable" with Vendor and Product information. So that, device specific name can be retrieved using ComponentName protocol. Cc: Vasudevan Sambandan <vasudevans@ami.com> Cc: Sundaresan Selvaraj <sundaresans@ami.com> Signed-off-by: Cheripally Gopi <gopic@ami.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Fix spelling error in PciSioSerialDxeNate DeSimone2022-10-251-1/+1
| | | | | | | | | | | | gSerialDevTempate should be gSerialDevTemplate Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* Ps2KbdCtrller: Make wait for SUCCESS after BAT non-fatalMatt DeVillier2022-10-251-7/+1
| | | | | | | | | | | | | | Recent model Chromebooks only return ACK, but not BAT_SUCCESS, which causes hanging and failed ps2k init. To mitigate this, make the absence of BAT_SUCCESS reply non-fatal, and reduce the no-reply timeout from 4s to 1s. Tested on google/dracia and purism/librem_14 Acked-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
* MdeModulePkg/XhciDxe: Add boundary check for TRB ring allocationjdzhang2022-10-203-22/+47
| | | | | | | | | | | According the Xhci Spec, TRB Rings may be larger than a Page, however they shall not cross a 64K byte boundary, so add a parameter to indicate whether the memory allocation is for TRB Rings or not. It will ensure the allocation not crossing 64K boundary in UsbHcAllocMemFromBlock if the memory is allocated for TRB Rings. Signed-off-by: jdzhang <jdzhang@kunluntech.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* Fix bug on SRIOV ReservedBusNum when ARI enable.Foster Nong2022-10-143-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a device which support both features SR-IOV/ARI has multi functions, which maybe support 8-255. After enable ARI forwarding in the root port and ARI Capable Hierarchy in the SR-IOV PF0. The device will support and expose multi functions(0-255) with ARI ID routing. In next device loop in below for() code, actually it still be in the same SR-IOV device, and just some PF which is over 8 or higher one(n*8), PciAllocateBusNumber() will allocate bus number(ReservedBusNum - TempReservedBusNum)) for this PF. if reset TempReservedBusNum as 0 in this case,it will allocate wrong bus number for this PF because TempReservedBusNum should be total previous PF's reserved bus numbers. code: for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) { TempReservedBusNum = 0; for (Func = 0; Func <= PCI_MAX_FUNC; Func++) { // // Check to see whether a pci device is present // Status = PciDevicePresent ( PciRootBridgeIo, &Pci, StartBusNumber, Device, Func ); ... Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber); The solution is add a new flag IsAriEnabled to help handle this case. if ARI is enabled, then TempReservedBusNum will not be reset again during all functions(1-255) scan with checking flag IsAriEnabled. Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Fixed extra 1 SR-IOV reserved busFoster Nong2022-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Below code will calculate the reserved bus number for the each PF. Based on the VF routing ID algorithm, PFRid and LastVF in below code already sure that "All VFs and PFs must have distinct Routing IDs". PF will be assigned Routing ID based on secBusNumber, ReservedBusNum will add into SubBusNumber directly. So the SR-IOV device will be assigned bus range as SecBusNumber ~ (SubBusNumber=(SecBusNumber + ReservedBusNum)). Thus "+1" in below code will cause extra 1 bus, and introduce a bus hole. PFRid = EFI_PCI_RID (Bus, Device, Func); LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride; PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1); In SR-IOV spec, there is a note in section 2.1.2: Note: Bus Numbers are a constrained resource. Devices are strongly encouraged to avoid leaving ?holes? in their Bus Number usage to avoid wasting Bus Numbers So the issue can be fixed with below code change. PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus); https://bugzilla.tianocore.org/show_bug.cgi?id=4069 Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Handle InitialVFs=0 case for SR-IOVFoster Nong2022-10-081-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per the section 3.3.5 SR-IOV spec v1.1, InitialVFs (0ch). InitialVFs indicates to SR-PCIM the number of VFs that are initially associated with the PF. The minimum value of InitialVFs is 0. Below code is used to calculate SR-IOV reserved bus number, if InitialVFs =0, it maybe calculate the wrong bus number in this case. LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride we can fix it with below code: if (PciIoDevice->InitialVFs == 0) { PciIoDevice->ReservedBusNum = 0; } else { PFRid = EFI_PCI_RID (Bus, Device, Func); LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride; // // Calculate ReservedBusNum for this PF // PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1); // // Calculate ReservedBusNum for this PF // PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1); } https://bugzilla.tianocore.org/show_bug.cgi?id=4069 Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBufferJeff Brasen via groups.io2022-10-011-2/+62
| | | | | | | | | | | Add support for partial free of non cached buffers. If a request for less than the full size is requested new allocations for the remaining head and tail of the buffer are added to the list. Added verification that Buffer is EFI_PAGE_SIZE aligned. The XHCI driver does this if the page size for the controller is >4KB. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/XhciDxe: Input context update for Evaluate Context commandjdzhang2022-09-271-2/+12
| | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4074 Update XhcEvaluateContext/XhcEvaluateContext64 to properly initialize the input context for Evaluate Context command. Signed-off-by: jdzhang <jdzhang@kunluntech.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/AhciPei: Fix MMIO base assignmentCzajkowski, Maciej2022-09-151-2/+4
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4041 There is a mistake in getting MMIO base using PciDevicePpi that can lead to the data corruption. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Maciej Czajkowski <maciej.czajkowski@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Use configurable PCD for AHCI command retriesBaraneedharan Anbazhagan2022-09-132-2/+3
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4011 AHCI commands are retried internally which prevents platform feature like drive password to process correctly entered password on subsequent attempts. PCD allows the platform to determine the number of retries. Signed-off-by: Baraneedharan Anbazhagan <anbazhagan@hp.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Fix imbalanced debug macrosMichael Kubacki2022-09-093-6/+6
| | | | | | | | | | | | | | | | | | | Updates debug macros in the package that have an imbalanced number of print specifiers to arguments. These changes try to preserve what was likely intended by the author. In cases information was missing due to the bug, the specifier may be removed since it was not previously accurately printing the expected value. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/NvmExpressPei: Use PCI_DEVICE_PPI to manage Nvme deviceChen, Xiao X2022-09-014-247/+483
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4017 This change modifies NvmExpressPei library to allow usage both EDKII_PCI_DEVICE_PPI and EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI to manage Nvme device. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Xiao X Chen <xiao.x.chen@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Enhance bus scan for all root bridge instancesFoster Nong2022-08-121-4/+14
| | | | | | | | | | | | Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=4000 Change flow to bus scan all root bridge instances even when any one root bridge meet bus resource OUT_OF_RESOURCE case. thus platform handler of "EfiPciHostBridgeEndBusAllocation" has an chance to do relative pci bus rebalance to handle this case. Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/AhciPei: Use PCI_DEVICE_PPI to manage AHCI deviceCzajkowski, Maciej2022-08-054-214/+381
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907 This change modifies AhciPei library to allow usage both EDKII_PCI_DEVICE_PPI and EDKII_PEI_ATA_AHCI_HOST_CONTROLLER_PPI to manage ATA HDD working under AHCI mode. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Maciej Czajkowski <maciej.czajkowski@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/XhciDxe: Add access xHCI Extended Capabilities PointerIan Chiu2022-06-274-16/+296
| | | | | | | | | | | | | | | | | | | | | | | Add support process Port Speed field value of PORTSC according to Supported Protocol Capability (define in xHCI spec 1.1) REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3914 The value of Port Speed field in PORTSC bit[10:13] (xHCI spec 1.1 section 5.4.8) should be change to use this value to query thru Protocol Speed ID (PSI) (xHCI spec 1.1 section 7.2.1) in xHCI Supported Protocol Capability and return the value according the Protocol Speed ID (PSIV) Dword. With this mechanism may able to detect more kind of Protocol Speed in USB3 and also compatiable with three kind of speed of USB2. Cc: Jenny Huang <jenny.huang@intel.com> Cc: More Shih <more.shih@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Ian Chiu <Ian.chiu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/XhciDxe: Check return value of XHC_PAGESIZE registerLuo, Heng2022-06-221-2/+8
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954 Report error if reserved bits are not 0 for PageSize Cc: Ray Ni <ray.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Update PciEnumeratorSupport to ignore OptionRom if neededMin Xu2022-04-022-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Function of UpdatePciInfo() in PciEnumeratorSupport.c is used to update the bar information for those incompatible PCI device. It is the right place to check if the OptionRom need to be ignored. According to "Table 20. ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in PI Spec 1.7, Type-specific flags can be set to 0 when Address Translation Offset == 6 to skip device option ROM (do not probe option rom BAR). Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* MdeModulePkg/Ufs: bRefClkFreq attribute be programmed after fDeviceInitBandaru, Purna Chandra Rao2022-03-291-17/+17
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3886 bRefClkFreq UFS card attribute need to be read and written after successful fDeviceInit and NOP response so that link will be stable. Cc: Wu Hao A <hao.a.wu@intel.com> Cc: Albecki Mateusz <mateusz.albecki@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Purna Chandra Rao Bandaru <purna.chandra.rao.bandaru@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/NvmExpressPei: fix check for NVM command setMara Sophie Grosch via groups.io2022-03-251-1/+1
| | | | | | | Previous commit fixed that check in DXE, this one now for PEI. Signed-off-by: Mara Sophie Grosch <littlefox@lf-net.org> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/NvmExpressDxe: fix check for Cap.CssMara Sophie Grosch via groups.io2022-03-251-1/+1
| | | | | | | | | | | | | | Fix the check for NVMe command set being supported by the controller. Was problematic with qemu (6.2.0, Debian 1:6.2+dfsg-3), which sets 0xC1 in that register, making the OVMF think the NVMe controller does not support NVMe. Uncovered by commit 9dd14fc91c174eae87fd122c7ac70073a363527f, which changed the number of bits included in the Css register from 4 to 8. Signed-off-by: Mara Sophie Grosch <littlefox@lf-net.org> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Make timeout for SD card configurableSean Rhodes2022-03-172-1/+6
| | | | | | | | | | | | | The default 1s timeout can delay boot splash on some hardware with no benefit. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Add bRefClkFreq card attribute programming supportBandaru, Purna Chandra Rao2022-03-102-19/+61
| | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3851 When the UFS card comes out of Manufacturer, bRefClkFreq attribute is set to 1h on the UFS card as per the Manufacturer Default Value specified by the spec JESD220*. However, depends on the UFS host system environment, it need to be set to the correct value. Reference Clock Frequency value 0h:19.2 MHz 1h: 26 MHz 2h: 38.4 MHz 3h: Obsolete Others: Reserved Cc: Wu Hao A <hao.a.wu@intel.com> Cc: Albecki Mateusz <mateusz.albecki@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Purna Chandra Rao Bandaru <purna.chandra.rao.bandaru@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Add a check for metadata size in NvmExpress DriverMa, Hua2022-03-072-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3856 Currently this NvmeExpress Driver do not support metadata handling. According to the NVME specs, metadata may be transferred to the host after the logical block data. It can overrun the input buffer which may only be the size of logical block data. Add a check to return not support for the namespaces formatted with metadata. v2 changes: - Change debug log level from INFO to ERROR - Change to if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0) v1: https://edk2.groups.io/g/devel/message/87242 Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Hua Ma <hua.ma@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/Usb/Keyboard.c: Don't request protocol before settingSean Rhodes2022-03-031-13/+5
| | | | | | | | | | | | | | | | | No need to check the interface protocol then conditionally setting, just set it to BOOT_PROTOCOL and check for error. This is what Linux does for HID devices as some don't follow the USB spec. One example is the Aspeed BMC HID keyboard device, which adds a massive boot delay without this patch as it doesn't respond to 'GetProtocolRequest'. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Correct high-memory use in NvmExpressDxeTomas Pilar2022-02-282-25/+28
| | | | | | | | | | | | | | | | | | | | | | Move the logic that stores starting PCI attributes and sets the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute to DriverBindingStart() before the memory that backs the DMA engine is allocated. This ensures that the DMA-backing memory is not forcibly allocated below 4G in system address map. Otherwise the allocation fails on platforms that do not have any memory below the 4G mark and the drive initialisation fails. Leave the PCI device enabling attribute logic in NvmeControllerInit() to ensure that the device is re-enabled on reset in case it was disabled via PCI attributes. Cc: Ray Ni <ray.ni@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Tomas Pilar <quic_tpilar@quicinc.com> Acked-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/Bus/Pci/PciBusDxe: Support platform PCI ROM overrideMichael D Kinney2022-02-041-3/+2
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3811 Remove ASSERT() statements that are triggered if a platform provides an override of PCI ROM attached to a PCI Controller. The PCI Platform Protocol allows the platform to provide a PCI ROM image for a PCI Controller. This works for PCI Controllers that do not have an attached PCI ROM, but the platform is not allowed to replace the PCI ROM for a PCI Controller that has its own PCI ROM. Removing these ASSERT() statements enables this additional use case. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdeModulePkg/SdMmcPciHcDxe: Robust improvements for SD card 1.8V switchAiman Rosli2022-01-241-3/+36
| | | | | | | | | | This changes is by adding 50ms delay during voltage switching from 3.3V to 1.8V, plus adding a goto Voltage33Retry for 3.3V checking and retrying. Change is for Enabling OS boot from SD card through UEFI payload. Signed-off-by: Aiman Rosli <muhammad.aiman.rosli@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Put off UFS HCS.DP checking to fix timing problemKe, VincentX2022-01-041-28/+19
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3776 Put off UFS HCS.DP (Device Attached) checking until UfsDeviceDetection() to fix timing problem. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ian Chiu <Ian.chiu@intel.com> Cc: Maggie Chu <maggie.chu@intel.com> Signed-off-by: VincentX Ke <vincentx.ke@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Refactoring UFS DME request and fix timing problemKe, VincentX2022-01-041-139/+187
| | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3775 Refactoring UFS DME request function and retry up to 5 times. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ian Chiu <Ian.chiu@intel.com> Cc: Maggie Chu <maggie.chu@intel.com> Signed-off-by: VincentX Ke <vincentx.ke@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Replace with UFS_UNIT_DESC to fix timeout problemKe, VincentX2022-01-041-12/+11
| | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3714 Replace with UFS_UNIT_DESC to fix response timeout problem. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ian Chiu <Ian.chiu@intel.com> Cc: Maggie Chu <maggie.chu@intel.com> Signed-off-by: VincentX Ke <vincentx.ke@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RPRay Ni2021-12-291-1/+25
| | | | | | | | | Before trying to access parent root port to check ARI capabilities, enumerator should see if Endpoint device is not Root Complex integrated to avoid undefined parent register accesses. Signed-off-by: Damian Bassa <damian.bassa@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/UsbBusDxe: fix NOOPT build errorGerd Hoffmann2021-12-232-2/+2
| | | | | | | | | | gcc-11 (fedora 35): /home/kraxel/projects/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c: In function ?UsbIoBulkTransfer?: /home/kraxel/projects/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c:277:12: error: ?UsbHcBulkTransfer? accessing 80 bytes in a region of size 8 [-Werror=stringop-overflow=] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/Bus/Pci/UhciDxe: Fix the UsbHc memory allocate and free issuejdzhang2021-12-091-4/+4
| | | | | | | | | When use the UsbHcAllocMemFromBlock() and UsbHcFreeMem() to allocate memory and free memory for the UHC, it should use the corresponding host address but not the pci bus address. Signed-off-by: jdzhang <jdzhang@zd-tech.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Apply uncrustify changesMichael Kubacki2021-12-07280-33644/+34755
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdeModulePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Change complex DEBUG_CODE() to DEBUG_CODE_BEGIN/END()Michael D Kinney2021-12-071-4/+4
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3767 Update use of DEBUG_CODE(Expression) if Expression is a complex code block with if/while/for/case statements that use {}. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Change OPTIONAL keyword usage styleMichael D Kinney2021-12-0711-25/+24
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3760 Update all use of ', OPTIONAL' to ' OPTIONAL,' for function params. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Change use of EFI_D_* to DEBUG_*Michael D Kinney2021-12-0761-881/+852
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3739 Update all use of EFI_D_* defines in DEBUG() macros to DEBUG_* defines. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg AtaAtapiPassThru: Skip the potential NULL pointer accessLiming Gao2021-11-241-0/+7
| | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3732 Recent change c9742578 exposes this potential issue. Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bitsIan Chiu2021-11-101-2/+45
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3703 MMIO base address size will overflow while finding two or more Host controller in the system. Correct it and support 32 and 64 bits address space. Signed-off-by: Ian Chiu <ian.chiu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Cc: Maggie Chu <maggie.chu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg AtaAtapiPassThru: Always do S.M.A.R.T. check if device supportLiming Gao2021-11-091-10/+9
| | | | | | | | | If S.M.A.R.T. is supported, it can be checked. Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Reproduce builds across source format changesMichael D Kinney2021-11-081-1/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3688 Use DEBUG_LINE_NUMBER instead of __LINE__. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdeModulePkg/XhciSched: Fix missing DEBUG argumentsMichael Kubacki2021-11-081-2/+2
| | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3662 Two DEBUG macros in XhciDxe/XhciSched.c are missing the argument that should be passed for the print specifier. In addition, this change updates the print level to "DEBUG_ERROR" and prints the status as well. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/Sd: Corrections for Extra.uni filesKonstantin Aladyshev2021-10-143-5/+8
| | | | | | | | | Add correct content to the 'SdDxeExtra.uni' file. Include 'EmmcDxeExtra.uni' and 'SdDxeExtra.uni' files to their appropriate INF files. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/PciBusDxe: Improve the flow of testing support attributesxueshengfeng2021-09-261-2/+5
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3635 Currently, in order to test the supported attributes, the PciTestSupportedAttribute() will set the command register to 0x27 (EFI_PCI_COMMAND_IO_SPACE, EFI_PCI_COMMAND_MEMORY_SPACE, EFI_PCI_COMMAND_BUS_MASTER, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) firstly, and then read back to check whether these attributes are set successfully in the device. This will cause the other enabled bits (other than EFI_PCI_COMMAND_IO_SPACE,EFI_PCI_COMMAND_MEMORY_SPACE, EFI_PCI_COMMAND_BUS_MASTER,EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) be cleared for a short of time This patch fixes this issue by keeping the origina enabled bits when setting 0x27. Signed-off-by: xueshengfeng <xueshengfeng@byosoft.com.cn> Reviewed-by: Ray <ray.ni@intel.com>
* MdeModulePkg:Increase Nvme capacity displayzhoucheng2021-08-301-0/+2
| | | | | | | | | | | Displays the Nvme total capacity. Signed-off-by: Cheng Zhou <zhoucheng@phytium.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg PciBusDxe: Increase the width of data read during oprom shadowSumana Venur2021-06-171-2/+2
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2989 Long times spent on shadowing oprom from graphics card to system memory. We are currently using 8 bit read cycles. This needs to be wider, at least 32bit reads to reduce the time for oprom shadow. Signed-off-by: Sumana Venur <sumana.venur@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/Xhci: Fix TRT when data length is 0Wenyi Xie2021-06-022-8/+18
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3418 According to xhci spec, at USB packet level, a Control Transfer consists of multiple transactions partitioned into stages: a setup stage, an optional data stage, and a terminating status stage. If Data Stage does not exist, the Transfer Type flag(TRT) should be No Data Stage. So if data length equals to 0, TRT is set to 0. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/PciBusDxe: Fix possible uninitialized useSergei Dmitrouk2021-05-191-3/+2
| | | | | | | | | | | If the function gets invalid value for the `ResizableBarOp` parameter and asserts are disabled, `Bit` can be used uninitialized. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Sergei Dmitrouk <sergei@posteo.net> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
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