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* MdeModulePkg/DxeIplPeim: reserve page 0 for NULL pointer detectionJian J Wang2019-11-092-0/+8
| | | | | | | | | | | | | | | | | | | | | When a boot loader examines the memory map, it can see that location 0 is available memory. If it chooses to use that memory, and PcdNullPointerDetectionPropertyMask is enabled, use of memory in page 0 will cause an exception. This does occur when running the memtest86 program. Leaving page 0 available is for legacy support purpose. Since we have deprecated the support of legacy, the solution is just reserving it so that it cannot be allocated for other uses. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1885 Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/DxeIplPeim: Initialize pointer PageMapLevel5EntryZhang, Shenglei2019-08-161-0/+5
| | | | | | | | | | | | | | | | Initialize PageMapLevel5Entry at the beginning of the function. This commit will fix a GCC 4.8.5 build failure introduced by commit b3527dedc3951f061c5a73cb4fb2b0f95f47e08b. OvmfPkg build failure wtih gcc 4.8.5 still exists at latest edk2 version. The commit 46f8a6891606746ca8b1e684ac379ce271306dc0 seems not to fix the build failure completely. Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/DxeIplPeim: Relocate operation of PageMapLevel5Entry++Zhang, Shenglei2019-08-141-1/+2
| | | | | | | | | | | | | | | | This commit will fix a GCC 4.8.5 build failure introduced by commit b3527dedc3951f061c5a73cb4fb2b0f95f47e08b. PageMapLevel5Entry may be uninitialized in original code, which means uninitialized pointer will be modified at some circumstance. So relocate the operation of PageMapLevel5Entry++ in order to make sure the pointer could be modified only when it is initialized. Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MdeModulePkg/DxeIpl: Create 5-level page table for long modeNi, Ray2019-08-092-77/+153
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 DxeIpl is responsible to create page table for DXE phase running either in long mode or in 32bit mode with certain protection mechanism enabled (refer to ToBuildPageTable()). The patch updates DxeIpl to create 5-level page table for DXE phase running in long mode when PcdUse5LevelPageTable is TRUE and CPU supports 5-level page table. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* MdeModulePkg: Remove RecoveryLib.h and PeiRecoveryLibNullZhang, Shenglei2019-08-051-1/+0
| | | | | | | | | | | | RecoveryLib.h and PeiRecoveryLibNull have been deprecated from 2009, so remove them. https://bugzilla.tianocore.org/show_bug.cgi?id=1299 Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Remove S3Lib.h and PeiS3LibNullZhang, Shenglei2019-08-051-1/+0
| | | | | | | | | | | S3Lib.h and PeiS3LibNull have been deprecated since 2009, so remove them. https://bugzilla.tianocore.org/show_bug.cgi?id=1299 Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/DxeIpl: Support Capsule On Disk.Wei6 Xu2019-06-263-11/+42
| | | | | | | | | | | | | | | | REF: https://github.com/tianocore/tianocore.github.io/wiki/ UEFI-Capsule-on-Disk-Introducation If Capsule On Disk mode, call Capsule On Disk Load PPI to load capsules. When it fails, still goes to Firmware Update boot path. BDS will clear corresponding indicator and reboot later on. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Chao B Zhang <chao.b.zhang@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Chao B Zhang <chao.b.zhang@intel.com> Acked-by: Hao A Wu <hao.a.wu@intel.com>
* Revert "Capsule-on-Disk entire PatchZhang, Chao B2019-06-213-42/+11
| | | | | | | | | | | | | | | | This reverts commit 0d4aa276d1f6e0cb9d71a7fb88b30c416ba6d5a3, 6470a43160183cd48cad8901c912a48811f18b13, fd7286089542ee7a98cfea00be45ceb3561e0b20, 7837d1249807b4248079699097bc993254235d7a, 6b32af2e105f9b5454a55b581f2dc365c5eb6397, 8636f70b5a763ed1c03b292708f9c5543e531ea9, f17935321a5b818a66e999632ef371b374b98f0c due to incorrect review process. Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Zhang, Chao B <chao.b.zhang@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/DxeIpl: Support Capsule On Disk.Wei6 Xu2019-06-203-11/+42
| | | | | | | | | | | | | | | | https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Capsule- on-Disk-Introducation If Capsule On Disk mode, call Capsule On Disk Load PPI to load capsules. When it fails, still goes to Firmware Update boot path. BDS will clear corresponding indicator and reboot later on. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Chao B Zhang <chao.b.zhang@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Chao B Zhang <chao.b.zhang@intel.com>
* MdeModulePkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0912-84/+12
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/DxeIpl: support more NX related PCDsJian J Wang2018-09-264-34/+76
| | | | | | | | | | | | | | | | | | | | | | | | BZ#1116: https://bugzilla.tianocore.org/show_bug.cgi?id=1116 Currently IA32_EFER.NXE is only set against PcdSetNxForStack. This confuses developers because following two other PCDs also need NXE to be set, but actually not. PcdDxeNxMemoryProtectionPolicy PcdImageProtectionPolicy This patch solves this issue by adding logic to enable IA32_EFER.NXE if any of those PCDs have anything enabled. Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/DxeIpl: disable paging before creating new page tableJian J Wang2018-09-101-0/+10
| | | | | | | | | | | | | | | | | | | | PEI Stack Guard needs to enable paging before DxeIpl. This might cause #GP in the transition from 32-bit PEI to 64-bit DXE due to the code trying to write CR3 register with PML4 page table while the processor is enabled with PAE paging. Simply disabling paging before updating CR3 can solve this conflict. There's no such issue for 64-bit PEI so this change applies only to 32-bit code. Cc: Star Zeng <star.zeng@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: "Ware, Ryan R" <ryan.r.ware@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MdeModulePkg: Removing ipf which is no longer supported from edk2.Chen A Chen2018-09-062-89/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeLoadFunc: Add use case for new Perf macroDandan Bi2018-07-263-1/+7
| | | | | | | | | | | Add an example case for the usage of PERF_EVENT_SIGNAL_BEGIN/PERF_EVENT_SIGNAL_END Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg: Clean up source filesLiming Gao2018-06-289-71/+71
| | | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Remove X86 ASM and S filesLiming Gao2018-06-073-171/+1
| | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg DxeIpl: remove the hard code alignment adjustment in Decompress()Liming Gao2018-01-191-13/+3
| | | | | | | | | Section data alignment should be made in the build generation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg DxeIpl: remove the hard code alignment adjustment.Liming Gao2018-01-191-7/+2
| | | | | | | | | Section data alignment should be made in the build generation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Core: Coding style clean-upJian J Wang2017-12-261-0/+5
| | | | | | | | | Cc: Dandan Bi <dandan.bi@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeIplPeim: fix incorrect page table split during protectingJian J Wang2017-12-151-2/+4
| | | | | | | | | | | | | | | | | | The root cause of this issue is that, during splitting page table, the page size should be the value of next level (smaller one) instead of current level. The wrong page size will then cause wrong page table introduced, which will break the normal boot. Validation works include booting to Windows 10 and Fedora 26 on real Intel platform and OVMF emulated platform in addition to manual checks on page table with JTAG tool. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeIpl: Mark page table as read-onlyJian J Wang2017-12-123-4/+364
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will set the memory pages used for page table as read-only memory after the paging is setup. CR0.WP must set to let it take into effect. A simple page table memory management mechanism, page table pool concept, is introduced to simplify the page table memory allocation and protection. It will also help to reduce the potential recursive "split" action during updating memory paging attributes. The basic idea is to allocate a bunch of continuous pages of memory in advance as one or more page table pools, and all future page tables consumption will happen in those pool instead of system memory. If the page pool is reserved at the boundary of 2MB page and with same size of 2MB page, there's no page granularity "split" operation will be needed, because the memory of new page tables (if needed) will be usually in the same page as target page table you're working on. And since we have centralized page tables (a few 2MB pages), it's easier to protect them by changing their attributes to be read-only once and for all. There's no need to apply the protection for new page tables any more as long as the pool has free pages available. Once current page table pool has been used up, one can allocate another 2MB memory pool and just set this new 2MB memory block to be read-only instead of setting the new page tables one page by one page. Two new PCDs PcdPageTablePoolUnitSize and PcdPageTablePoolAlignment are used to specify the size and alignment for page table pool. For IA32 processor 0x200000 (2MB) is the only choice for both of them to meet the requirement of page table pool. Laszlo (lersek@redhat.com) did a regression test on QEMU virtual platform with one middle version of this series patch. The details can be found at https://lists.01.org/pipermail/edk2-devel/2017-December/018625.html There're a few changes after his work. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdeModulePkg DxeIpl: Move ClearFirst4KPage/IsNullDetectionEnabled definitionStar Zeng2017-12-112-27/+26
| | | | | | | | | | | Move ClearFirst4KPage/IsNullDetectionEnabled definition from DxeIpl.h to VirtualMemory.h as they are implemented in VirtualMemory.c and only used in IA32/X64 ARCH. Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/DxeIpl: Enable paging for Stack GuardJian J Wang2017-12-084-15/+46
| | | | | | | | | | | | | | | | | | | Stack guard feature makes use of paging mechanism to monitor if there's a stack overflow occurred during boot. This patch will check setting of PCD PcdCpuStackGuard. If it's TRUE, DxeIpl will setup page table and set the page at which the stack base locates to be NOT PRESENT. If stack is used up and memory access cross into the last page of it, #PF exception will be triggered. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* MdeModulePkg: Fix unix style of EOLJian J Wang2017-11-212-33/+33
| | | | | | | | | Cc: Wu Hao <hao.a.wu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/DxeIpl: Enable paging for heap guardJian J Wang2017-11-172-4/+33
| | | | | | | | | | | | | | | Heap guard feature needs paging to work properly. 64-bit BIOS uses PcdDxeIplBuildPageTables to control the page table setup. 32-bit BIOS has to check heap guard feature to decide enabling paging or not. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/DxeIplPeim: Refine coding style in function commentsDandan Bi2017-10-242-11/+18
| | | | | | | | | | | Make the comments align with the function. And add some missing function comments. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/DxeIpl: Implement NULL pointer detectionJian J Wang2017-10-116-10/+131
| | | | | | | | | | | | | | | | | | | | | | | NULL pointer detection is done by making use of paging mechanism of CPU. During page table setup, if enabled, the first 4-K page (0-4095) will be marked as NOT PRESENT. Any code which unintentionally access memory between 0-4095 will trigger a Page Fault exception which warns users that there's potential illegal code in BIOS. This also means that legacy code which has to access memory between 0-4095 should be cautious to temporarily disable this feature before the access and re-enable it afterwards; or disalbe this feature at all. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ayellet Wolman <ayellet.wolman@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdeModulePkg: Remove unsupported PcdExpression usage in module INFLiming Gao2017-04-061-6/+6
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=442 PcdExpression used in INF to control PCD and Source is unsupported feature. Current sample usage in module INF brings confuse. Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Core/DxeIplPeim: Add support for PCD ↵Leo Duran2017-03-014-11/+50
| | | | | | | | | | | | | | | | | | PcdPteMemoryEncryptionAddressOrMask This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when creating page tables. Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeIplPeim: UINTN used wrongly for EFI_PHYSICAL_ADDRESSJeff Fan2016-11-091-1/+2
| | | | | | | | | | | | | | | | PeiServicesAllocatePages () will output sizeof (EFI_PHYSICAL_ADDRESS) value. IdtTableForX64 is sizeof (UINTN) local variable. It will overwrite other local variable. This issue is found when we dump BaseOfStack value. Cc: Feng Tian <feng.tian@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* MdeModulePkg: Display new stack base and sizeJeff Fan2016-11-091-0/+16
| | | | | | | | | | | | | Dump new stack base and size information could help developer to narrow down stack crash issue. Cc: Feng Tian <feng.tian@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLibArd Biesheuvel2016-07-072-2/+2
| | | | | | | | | | | | Switch all users of ArmLib that depend on the MMU routines to the new, separate ArmMmuLib. This needs to occur in one go, since the MMU routines are removed from ArmLib build at the same time, to prevent conflicting symbols. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg DxeIplPeim: Add ASSERTs for unexpected AllocatePages failureHao Wu2016-07-051-1/+3
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg DxeIplPeim: Convert Ia32/IdtVectorAsm.asm to NASMJordan Justen2016-06-282-0/+78
| | | | | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/IdtVectorAsm.asm to Ia32/IdtVectorAsm.nasm Note: Manually updated code storing @VectorTemplateBase address Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Allow DxeIpl to load without permanent memoryCohen, Eugene2016-05-303-28/+112
| | | | | | | | | | | | | | | | | | PI1.4a spec added "For S3 resume boot modes DXE IPL must be prepared to execute without permanent memory installed and invoke the S3 resume modules." To follow PI1.4a spec, this patch is to update DxeIpl and PeiCore to enable S3 resume from temporary memory. The normal boot path still enforces the permanent memory requirement. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Tested-by: Katie Dellaquila <katie.dellaquila@hp.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg: Convert all .uni files to utf-8Jordan Justen2015-12-152-0/+0
| | | | | | | | | | | | | To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py MdeModulePkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19257 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg/DxeIplPeim: implement non-exec stack for ARM/AARCH64Ard Biesheuvel2015-10-082-0/+15
| | | | | | | | | | | | Mark the DXE stack region as non-executable right before handing off to the DXE core, by invoking the appropriate ArmLib function. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Feng Tian <Feng.Tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18588 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg DxeIpl: Fix IA32 build failure with GCC 5.1.1Star Zeng2015-08-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | Got the build failure feedback below, this patch is to fix that. This broke the IA32 Ovmf build for me, with GCC 5.1.1 (Fedora 22): /home/dwmw2/git/edk2/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c:377:7: error: ‘PageTables’ may be used uninitialized in this function [-Werror=maybe-uninitialized] AsmWriteCr3 (PageTables); ^ /home/dwmw2/git/edk2/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c:224:9: note: ‘PageTables’ was declared here UINTN PageTables; ^ cc1: all warnings being treated as errors Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18190 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg DxeIpl: Add stack NX supportStar Zeng2015-08-055-37/+382
| | | | | | | | | | | | | | This feature is added for UEFI spec that says "Stack may be marked as non-executable in identity mapped page tables". A PCD PcdSetNxForStack is added to turn on/off this feature, and it is FALSE by default. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: "Yao, Jiewen" <Jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18166 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg DxeIpl: Skip install MemoryInfoHob if this hob existsLiming Gao2015-07-161-25/+30
| | | | | | | | | | | | Add the check at DxeLoadCore() on MdeModulePkg\Core\DxeIplPeim\DxeLoad.c to skip install the "gEfiMemoryTypeInformationGuid" hob if it is already installed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18018 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg: Convert non DOS format files to DOS format and remove unused ↵Gao, Liming2014-09-031-0/+0
| | | | | | | | | | | | module UNI files. 1. Module UNI and Package UNI files are not DOS format. Convert them to DOS format. 2. Remove unused SectionExtractionDxeModStrs.uni and SectionExtractionPeiModStrs.uni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gao, Liming <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16044 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg: INF/DEC file updates to EDK II packagesZeng, Star2014-08-282-0/+0
| | | | | | | | | | | | | | | | | | 2. Add MODULE_UNI_FILE file that contains the localized Abstract and Description of a module. a. Addresses an information gap between INF files and the UEFI Distribution Packaging Specification XML schema b. There will be an associated update to UPT in BaseTools to consume MODULE_UNI_FILE and associated UNI file during UDP creation that performs the INF -> XML conversion. c. There will be an associated update to UPT in BaseTools to produce MODULE_UNI_FILE and associated UNI file during UDP installation that performs the XML -> INF conversion. 3. Add Module Extra UNI file that provides the localized Name of a module. a. [UserExtensions.TianoCore."ExtraFiles"] provides an easy method for a module to specify extra files not listed in [Sources] or [Binaries] sections to be added to a UDP without having to list the files in the UPT package information data file. b. There will be an associated update to UPT in BaseTools to package up files listed in [UserExtensions.TianoCore."ExtraFiles"] during UDP creation. c. UNI file contains localized name of a module to go along with the localized Abstract and Description from the MODULE_UNI_FILE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Zeng, Star <star.zeng@intel.com> Reviewed-by: Gao, Liming <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15963 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg: INF/DEC file updates to EDK II packagesZeng, Star2014-08-281-25/+26
| | | | | | | | | | | | 1. Usage information in INF file comment blocks are either incomplete or incorrect. This includes usage information for Protocols/PPIs/GUIDs/PCDs/HOBs/Events/BootModes. The syntax for usage information in comment blocks is defined in the EDK II Module Information (INF) Specification Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Zeng, Star <star.zeng@intel.com> Reviewed-by: Gao, Liming <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15962 6f19259b-4bc3-4df7-8a09-765794883524
* 1. DxeIplPeim will locate Vector Handoff Table PPI and build GUIDed HOB if ↵Jeff Fan2013-11-224-8/+63
| | | | | | | | | | | | | | | | | it has. 2. DxeMain will get Vector Handoff Table GUIDed HOB to install configuration table if it has. 3. Updated CPU Exception Handler Library to provide 3 new APIs to replace original one API and updated NULL instance accordingly. 4. Updated DxeMain/CapsuleX64/BootSriptExectorDxe to use the new API in CPU Exception Handler Lib. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14884 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg: Added ARM Aarch64 architecture supportHarry Liebel2013-08-071-2/+2
| | | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14530 6f19259b-4bc3-4df7-8a09-765794883524
* Check status before reporting error status code.li-elvin2012-12-201-9/+14
| | | | | | | | Signed-off-by: Li Elvin <elvin.li@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14011 6f19259b-4bc3-4df7-8a09-765794883524
* Install CustomGuidedSectionExtractionPpi for Tiano or Lzma DeCompression on ↵lgao42012-10-311-19/+18
| | | | | | | | | | S3 boot in DxeIpl. Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13900 6f19259b-4bc3-4df7-8a09-765794883524
* Add missing status code in several modules.li-elvin2012-10-301-3/+27
| | | | | | | | | | | | Signed-off-by: Li Elvin <elvin.li@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com> Reviewed-by: Gao Liming <liming.gao@intel.com> Reviewed-by: Tian Feng <feng.tian@intel.com> Reviewed-by: Fan Jeff <jeff.fan@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13890 6f19259b-4bc3-4df7-8a09-765794883524
* Add logic to validate variable before use it.ydong102012-05-181-1/+48
| | | | | | | | | Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jiewen Yao <jiewen,yao@intel.com> Reviewed-by: Michael D. Kinney <michael.d.kinney@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13323 6f19259b-4bc3-4df7-8a09-765794883524
* Add core FFS3 support, PeiCore and DxeIpl.lzeng142011-10-271-10/+21
| | | | | | | Signed-off-by: lzeng14 Reviewed-by: lgao4 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12583 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 06:27:38 +0000