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* MdeModulePkg/PeiCore: Ensure FfsFileHeader 8 bytes alignedStar Zeng2019-02-281-2/+2
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=864 REF: CVE-2018-3630 To follow PI spec, ensure FfsFileHeader 8 bytes aligned. Current code only handles (FwVolHeader->ExtHeaderOffset != 0) path, update code to also handle (FwVolHeader->ExtHeaderOffset == 0) path. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/PeiMain: Support EFI_PEI_CORE_FV_LOCATION_PPIChasel, Chiu2019-02-153-15/+44
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524 When shadowing PeiCore the EFI_PEI_CORE_FV_LOCATION_PPI should be checked to see if PeiCore not in BFV, otherwise just shadowing PeiCore from BFV. Test: Verified on internal platform and booting successfully. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/Dxe/Page: take MAX_ALLOC_ADDRESS into accountArd Biesheuvel2018-12-201-26/+26
| | | | | | | | | | | Take MAX_ALLOC_ADDRESS into account in the implementation of the page allocation routines, so that they will only return memory that is addressable by the CPU at boot time, even if more memory is available in the GCD memory map. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/Dxe/Gcd: disregard memory above MAX_ALLOC_ADDRESSArd Biesheuvel2018-12-201-4/+4
| | | | | | | | | | | | | Update the GCD memory map initialization code so it disregards memory that is not addressable by the CPU at boot time. This only affects the first memory descriptor that is added, other memory descriptors are permitted that describe memory ranges that may be accessible to the CPU itself only when executing under the OS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxPpiSupportedStar Zeng2018-12-195-199/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update code to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxPpiSupported in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxFvSupportedStar Zeng2018-12-194-24/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update PeiCore to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxFvSupported in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxPeimPerFvStar Zeng2018-12-194-108/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update code to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxPeimPerFv in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* MdeModulePkg/Core: fix ineffective guard page issueJian J Wang2018-11-071-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1295 This issue originates from following patch which allows to enable paging if PcdImageProtectionPolicy and PcdDxeNxMemoryProtectionPolicy (in addition to PcdSetNxForStack) are set to enable related features. 5267926134d17e86672b84fd57b438f05ffa68e1 Due to above change, PcdImageProtectionPolicy will be set to 0 by default in many platforms, which, in turn, cause following code in MdeModulePkg\Core\Dxe\Misc\MemoryProtection.c fail the creation of notify event of CpuArchProtocol. 1138: if (mImageProtectionPolicy != 0 || PcdGet64 (PcdDxeNxMemoryProtectionPolicy) != 0) { 1139: Status = CoreCreateEvent ( ... 1142: MemoryProtectionCpuArchProtocolNotify, ... 1145: ); Then following call flow won't be done and Guard pages will not be set as not-present in SetAllGuardPages() eventually. MemoryProtectionCpuArchProtocolNotify() => HeapGuardCpuArchProtocolNotify() => SetAllGuardPages() The solution is removing the if(...) statement so that the notify event will always be created and registered. This won't cause unnecessary code execution because, in the notify event handler, the related PCDs like PcdImageProtectionPolicy and PcdDxeNxMemoryProtectionPolicy will be checked again before doing related jobs. Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Core: fill logic hole in MemoryProtectionCpuArchProtocolNotifyJian J Wang2018-11-071-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the end of of MemoryProtectionCpuArchProtocolNotify there's cleanup code to free resource. But at line 978, 994, 1005 the function returns directly. This patch use "goto" to replace "return" to make sure the resource is freed before exit. 1029: CoreCloseEvent (Event); 1030: return; There's another memory leak after calling gBS->LocateHandleBuffer() in the same function: Status = gBS->LocateHandleBuffer ( ByProtocol, &gEfiLoadedImageProtocolGuid, NULL, &NoHandles, &HandleBuffer ); HandleBuffer is allocated in above call but never freed. This patch will also add code to free it. Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/PiSmmIpl: Do not reset SMRAM to UC when CPU driver runsRuiyu Ni2018-11-011-13/+2
| | | | | | | | | | | | | | | | Today's PiSmmIpl implementation initially sets SMRAM to WB to speed up the SMM core/modules loading before SMM CPU driver runs. When SMM CPU driver runs, PiSmmIpl resets the SMRAM to UC. It's done in SmmIplDxeDispatchEventNotify(). COMM_BUFFER_SMM_DISPATCH_RESTART is returned from SMM core that SMM CPU driver is just dispatched. Since now the SMRR is widely used to control the SMRAM cache setting. It's not needed to reset the SMRAM to UC anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com>
* MdeModulePkg/Core: fix an issue of potential NULL pointer accessJian J Wang2018-10-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1286 This issue is introduced by bb685071c2602cf786ea84c69bbebf2158194a38. The *MemorySpaceMap assigned with NULL (line 1710) value might be accessed (line 1726/1730) without any sanity check. Although it won't happen in practice because of line 1722, we still need to add check against NULL to make static code analyzer happy. 1710 *MemorySpaceMap = NULL; .... ... 1722 if (DescriptorCount == *NumberOfDescriptors) { .... ... 1726 Descriptor = *MemorySpaceMap; .... ... 1730 BuildMemoryDescriptor (Descriptor, Entry); Tests: Pass build and boot to shell. Cc: Hao Wu <hao.a.wu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/Core: correct one coding styleJian J Wang2018-10-271-1/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1284 Non-Boolean comparisons should use a compare operator (==, !=, >, < >=, <=) Cc: Dandan Bi <dandan.bi@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* MdeModulePkg/Core: fix an IA32 build failureJian J Wang2018-10-261-5/+5
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1277 The failure is caused by data type conversion between UINTN and UINT64, which is checked in at 63ebde8ef6d4ff497d054ccc010904ecd4441198. Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Core: add freed-memory guard featureJian J Wang2018-10-266-34/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freed-memory guard is used to detect UAF (Use-After-Free) memory issue which is illegal access to memory which has been freed. The principle behind is similar to pool guard feature, that is we'll turn all pool memory allocation to page allocation and mark them to be not-present once they are freed. This also implies that, once a page is allocated and freed, it cannot be re-allocated. This will bring another issue, which is that there's risk that memory space will be used out. To address it, the memory service add logic to put part (at most 64 pages a time) of freed pages back into page pool, so that the memory service can still have memory to allocate, when all memory space have been allocated once. This is called memory promotion. The promoted pages are always from the eldest pages which haven been freed. This feature brings another problem is that memory map descriptors will be increased enormously (200+ -> 2000+). One of change in this patch is to update MergeMemoryMap() in file PropertiesTable.c to allow merge freed pages back into the memory map. Now the number can stay at around 510. Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Core: prevent re-acquire GCD memory lockJian J Wang2018-10-261-25/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This issue is hidden in current code but exposed by introduction of freed-memory guard feature due to the fact that the feature will turn all pool allocation to page allocation. The solution is moving the memory allocation in CoreGetMemorySpaceMap() to be out of the GCD memory map lock. CoreDumpGcdMemorySpaceMap() => CoreGetMemorySpaceMap() => CoreAcquireGcdMemoryLock () * AllocatePool() => InternalAllocatePool() => CoreAllocatePool() => CoreAllocatePoolI() => CoreAllocatePoolPagesI() => CoreAllocatePoolPages() => FindFreePages() => PromoteMemoryResource() => CoreAcquireGcdMemoryLock() ** Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeIpl: support more NX related PCDsJian J Wang2018-09-264-34/+76
| | | | | | | | | | | | | | | | | | | | | | | | BZ#1116: https://bugzilla.tianocore.org/show_bug.cgi?id=1116 Currently IA32_EFER.NXE is only set against PcdSetNxForStack. This confuses developers because following two other PCDs also need NXE to be set, but actually not. PcdDxeNxMemoryProtectionPolicy PcdImageProtectionPolicy This patch solves this issue by adding logic to enable IA32_EFER.NXE if any of those PCDs have anything enabled. Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg: remove PE/COFF header workaround for ELILO on IPFArd Biesheuvel2018-09-245-108/+5
| | | | | | | | | | | | Now that Itanium support has been dropped, we can remove the various occurrences of the ELILO on Itanium PE/COFF header workaround. Link: https://bugzilla.tianocore.org/show_bug.cgi?id=816 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeIpl: disable paging before creating new page tableJian J Wang2018-09-101-0/+10
| | | | | | | | | | | | | | | | | | | | PEI Stack Guard needs to enable paging before DxeIpl. This might cause #GP in the transition from 32-bit PEI to 64-bit DXE due to the code trying to write CR3 register with PML4 page table while the processor is enabled with PAE paging. Simply disabling paging before updating CR3 can solve this conflict. There's no such issue for 64-bit PEI so this change applies only to 32-bit code. Cc: Star Zeng <star.zeng@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: "Ware, Ryan R" <ryan.r.ware@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MdeModulePkg PeiCore: Always use PeiImageRead() function to load PEI imageLiming Gao2018-09-071-84/+1
| | | | | | | | | | | In V2, Remove GetImageReadFunction(), directly use PeiImageRead(). The copy PeiImageReadForShadow function doesn't improve the boot performance. This patch removes this copy logic to simplify the code logic. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Removing ipf which is no longer supported from edk2.Chen A Chen2018-09-065-92/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Remove trailing white spaceStar Zeng2018-09-061-2/+2
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1144 Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* MdeModulePkg PeiCore: Fix VS2012 build failureStar Zeng2018-09-051-0/+2
| | | | | | | | | | | | | | | | | | fwvol.c(1572) : warning C4701: potentially uninitialized local variable 'Status' used The build failure is caused by 0e042d0ad76157ac9bad17bb4e1ff2919ca0d8f4 for https://bugzilla.tianocore.org/show_bug.cgi?id=1131 This patch initializes Status to fix the build failure. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* MdeModulePkg DxeCore: Handle multiple FV images in one FV fileStar Zeng2018-09-031-115/+130
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1131 PI spec and BaseTools support to generate multiple FV images in one FV file. This patch is to update DxeCore to handle the case. Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg PeiCore: Handle multiple FV images in one FV fileStar Zeng2018-09-032-124/+145
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1131 PI spec and BaseTools support to generate multiple FV images in one FV file. This patch is to update PeiCore to handle the case. Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/PiSmmCore: Check valid memory range.Eric Dong2018-08-281-0/+39
| | | | | | | | | | | | Call BS.AllocatePages in DXE driver and call SMM FreePages with the address of the buffer allocated in the DXE driver. SMM FreePages success and add a non-SMRAM range into SMM heap list. This is not an expected behavior. SMM FreePages should return error for this case and not free the pages. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1098 Change-Id: Ie5ffa1ac62c558aa418a8a3d7d0e8158b846e13b Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg PiSmmCore: Remove redundant functionsshenglei2018-08-213-418/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions that are never called have been removed. They are IsImageInsideSmram,FindImageRecord,SmmRemoveImageRecord, SmmMemoryAttributesTableConsistencyCheck,DumpSmmMemoryMapEntry, SmmMemoryMapConsistencyCheckRange,SmmMemoryMapConsistencyCheck, DumpSmmMemoryMap,ClearGuardMapBit,SetGuardMapBit,AdjustMemoryA, AdjustMemoryS,IsHeadGuard and IsTailGuard. FindImageRecord() is called by SmmRemoveImageRecord(); however, nothing calls SmmRemoveImageRecord(). SmmMemoryMapConsistencyCheckRange() is called by SmmMemoryMapConsistencyCheck(); however, nothing calls SmmMemoryMapConsistencyCheck(). https://bugzilla.tianocore.org/show_bug.cgi?id=1062 v2:append the following to the commit message. - FindImageRecord() is called by SmmRemoveImageRecord(); however, nothing calls SmmRemoveImageRecord(). - SmmMemoryMapConsistencyCheckRange() is called by SmmMemoryMapConsistencyCheck(); however, nothing calls SmmMemoryMapConsistencyCheck(). Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg Core/Dxe: Remove redundant functionsshenglei2018-08-213-113/+0
| | | | | | | | | | | | | | | | The functions that are never called have been removed. They are ClearGuardMapBit,SetGuardMapBit,IsHeadGuard, IsTailGuard and CoreEfiNotAvailableYetArg0. https://bugzilla.tianocore.org/show_bug.cgi?id=1062 Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Remove redundant library classes and GUIDsshenglei2018-08-206-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some redundant library classes and GUIDs have been removed in inf, .c and .h files. https://bugzilla.tianocore.org/show_bug.cgi?id=1044 https://bugzilla.tianocore.org/show_bug.cgi?id=1045 https://bugzilla.tianocore.org/show_bug.cgi?id=1047 https://bugzilla.tianocore.org/show_bug.cgi?id=1049 https://bugzilla.tianocore.org/show_bug.cgi?id=1051 https://bugzilla.tianocore.org/show_bug.cgi?id=1052 https://bugzilla.tianocore.org/show_bug.cgi?id=1053 https://bugzilla.tianocore.org/show_bug.cgi?id=1054 https://bugzilla.tianocore.org/show_bug.cgi?id=1055 https://bugzilla.tianocore.org/show_bug.cgi?id=1056 https://bugzilla.tianocore.org/show_bug.cgi?id=1017 https://bugzilla.tianocore.org/show_bug.cgi?id=1035 https://bugzilla.tianocore.org/show_bug.cgi?id=1033 https://bugzilla.tianocore.org/show_bug.cgi?id=1012 https://bugzilla.tianocore.org/show_bug.cgi?id=1011 https://bugzilla.tianocore.org/show_bug.cgi?id=1062 v2: 1. Correct copyright year. 2. Fix alignment issue in AcpiPlatformDxe.inf. 3. Add DevicePathLib which is removed before in I2cHostDxe.inf. 4. Update NvmExpressPei.inf, NvmExpressPei.h, IScsiDxe.inf, IScsiDxe.inf, IScsiDxe.h, DxeMain.inf, DxeMain.h, PiSmmCore.inf and PiSmmCore.h for https://bugzilla.tianocore.org/show_bug.cgi?id=1062. v3: 1. Add https://bugzilla.tianocore.org/show_bug.cgi?id=1062 to the link list. 2. Remove DevicePathLib from I2cHostDxe.inf. 3. Update NvmExpressPei.inf, NvmExpressPei.h, UfsPciHcDxe.inf, UfsPciHcDxe.h, I2cHostDxe.inf, AtaBusDxe.inf, IScsiDxe.inf, IScsiDxe.h, DxeMain.inf, DxeMain.h, PiSmmCore.inf and PiSmmCore.h for https://bugzilla.tianocore.org/show_bug.cgi?id=1062. (Forget to add UfsPciHcDxe.inf, UfsPciHcDxe.h, AtaBusDxe.inf, and I2cHostDxe.inf previously.) Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeCore: Not update RtCode in MemAttrTable after EndOfDxeJiewen Yao2018-07-261-0/+13
| | | | | | | | | | | | | | | | We want to provide precise info in MemAttribTable to both OS and SMM, and SMM only gets the info at EndOfDxe. So we do not update RtCode entry in EndOfDxe. The impact is that if 3rd part OPROM is runtime, it cannot be executed at UEFI runtime phase. Currently, we do not see compatibility issue, because the only runtime OPROM we found before in UNDI, and UEFI OS will not use UNDI interface in OS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeCore: Install UEFI mem attrib table at EndOfDxe.Jiewen Yao2018-07-261-1/+35
| | | | | | | | | So that the SMM can consume it to set page protection for the UEFI runtime page with EFI_MEMORY_RO attribute. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeLoadFunc: Add use case for new Perf macroDandan Bi2018-07-263-1/+7
| | | | | | | | | | | Add an example case for the usage of PERF_EVENT_SIGNAL_BEGIN/PERF_EVENT_SIGNAL_END Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg PeiCore: Not assume PpiDescriptor and Ppi in same rangeStar Zeng2018-07-021-89/+115
| | | | | | | | | | | | | | | Current code assumes PpiDescriptor and Ppi are in same range (heap/stack/hole). This patch removes the assumption. Descriptor needs to be converted first. It is also handled by this patch. Cc: Liming Gao <liming.gao@intel.com> Cc: Qing Huang <qing.huang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/PiSmmCore: Remove SMM Perf entryDandan Bi2018-06-281-4/+0
| | | | | | | | | | | The perf measurement entry in SmmEntryPoint function doesn't have significant meaning. So remove it now. Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg: Clean up source filesLiming Gao2018-06-2870-1368/+1368
| | | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Use new added Perf macrosBi, Dandan2018-06-268-58/+39
| | | | | | | | | | | Replace old Perf macros with the new added ones. Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/Core: remove SMM check for Heap Guard feature detectionJian J Wang2018-06-191-10/+0
| | | | | | | | | | | | | | | CpuDxe driver is updated to be able to access DXE page table in SMM mode, which means Heap Guard can get correct memory paging attributes in what environment. It's not necessary to exclude SMM from detecting Heap Guard feature support. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Remove X86 ASM and S filesLiming Gao2018-06-073-171/+1
| | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg PeiCore: Check error status when processing boot FVMarcin Wojtas2018-06-041-6/+7
| | | | | | | | | | | | Until now the possible errors returned from processing boot firmware volume were not checked, which could cause misbehavior in further booting stages. Add relevant assert. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Jan Dabros <jsd@semihalf.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg PeiCore: FvCount to be checked for the registered for shadow PEIMLiming Gao2018-05-171-1/+1
| | | | | | | | | | The PEIM in all cached FV image may be in registered for shadow status. Current logic CurrentPeimFvCount is not enough. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/PiSmmIpl: fix non-executable SMM RAMJian J Wang2018-04-131-14/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an issue introduced by commit 5b91bf82c67b586b9588cbe4bbffa1588f6b5926 and 0c9f2cb10b7ddec56a3440e77219fd3ab1725e5c This issue will only happen if PcdDxeNxMemoryProtectionPolicy is enabled for reserved memory, which will mark SMM RAM as NX (non- executable) during DXE core initialization. SMM IPL driver will unset the NX attribute for SMM RAM to allow loading and running SMM core/drivers. But above commit will fail the unset operation of the NX attribute due to a fact that SMM RAM has zero cache attribute (MRC code always sets 0 attribute to reserved memory), which will cause GCD internal method ConverToCpuArchAttributes() to return 0 attribute, which is taken as invalid CPU paging attribute and skip the calling of gCpu->SetMemoryAttributes(). The solution is to make use of existing functionality in PiSmmIpl to make sure one cache attribute is set for SMM RAM. For performance consideration, PiSmmIpl will always try to set SMM RAM to write-back. But there's a hole in the code which will fail the setting write-back attribute because of no corresponding cache capabilities. This patch will add necessary cache capabilities before setting corresponding attributes. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/SmmCore: add sanity check for SetMemoryAttributesJian J Wang2018-04-131-12/+18
| | | | | | | | | | | | | | | Heap Guard feature needs enough memory and paging to work. Otherwise calling SetMemoryAttributes to change page attribute will fail. This patch add necessary check of result of calling SetMemoryAttributes. This can help users to debug their problem in enabling this feature. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DxeCore: add sanity check for SetMemoryAttributesJian J Wang2018-04-131-2/+7
| | | | | | | | | | | | | | | Heap Guard feature needs enough memory and paging to work. Otherwise calling SetMemoryAttributes to change page attribute will fail. This patch add necessary check of result of calling SetMemoryAttributes. This can help users to debug their problem in enabling this feature. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Gcd: Suppress incorrect compiler/analyzer warningsStar Zeng2018-04-081-1/+5
| | | | | | | | | | | | | | It is caused by 0c9f2cb10b7ddec56a3440e77219fd3ab1725e5c and false positive. Initialize CpuArchAttributes to suppress incorrect compiler/analyzer warnings. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* MdeModulePkg/Gcd: Filter gCpu->SetMemoryAttributes() callsKinney, Michael D2018-04-051-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an issue with VlvTbltDevicePkg introduced by commit 5b91bf82c67b586b9588cbe4bbffa1588f6b5926. The history is as below. To support heap guard feature, 14dde9e903bb9a719ebb8f3381da72b19509bc36 added support for SetMemorySpaceAttributes() to handle page attributes, but after that, a combination of CPU arch attributes and other attributes was not allowed anymore, for example, UC + RUNTIME. It is a regression. Then 5b91bf82c67b586b9588cbe4bbffa1588f6b5926 was to fix the regression, and we thought 0 CPU arch attributes may be used to clear CPU arch attributes, so 0 CPU arch attributes was allowed to be sent to gCpu->SetMemoryAttributes(). But some implementation of CPU driver may return error for 0 CPU arch attributes. That fails the case that caller just calls SetMemorySpaceAttributes() with none CPU arch attributes (for example, RUNTIME), and the purpose of the case is not to clear CPU arch attributes. This patch filters the call to gCpu->SetMemoryAttributes() if the requested attributes is 0. It also removes the #define INVALID_CPU_ARCH_ATTRIBUTES that is no longer used. Cc: Heyi Guo <heyi.guo@linaro.org> Cc: Yi Li <phoenix.liyi@huawei.com> Cc: Renhao Liang <liangrenhao@huawei.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg/Gcd: Fix bug of attribute conversionHeyi Guo2018-04-021-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | For gDS->SetMemorySpaceAttributes(), when user passes a combined memory attribute including CPU arch attribute and other attributes, like EFI_MEMORY_RUNTIME, ConverToCpuArchAttributes() will return INVALID_CPU_ARCH_ATTRIBUTES and skip setting page/cache attribute for the specified memory space. We don't see any reason to forbid combining CPU arch attributes and non-CPU-arch attributes when calling gDS->SetMemorySpaceAttributes(), so we remove the check code in ConverToCpuArchAttributes(); the remaining code is enough to grab the interested bits for Cpu->SetMemoryAttributes(). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Signed-off-by: Yi Li <phoenix.liyi@huawei.com> Signed-off-by: Renhao Liang <liangrenhao@huawei.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/DxeMain: Fix BSP interrupts reenabled in ExitBootServicesHao Wu2018-03-201-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Within function CoreExitBootServices(), this commit will move the call of: MemoryProtectionExitBootServicesCallback(); before: SaveAndSetDebugTimerInterrupt (FALSE); and gCpu->DisableInterrupt (gCpu); The reason is that, within MemoryProtectionExitBootServicesCallback(), APIs like RaiseTpl and RestoreTpl maybe called. An example will be: DebugLib (using PeiDxeDebugLibReportStatusCode instance) | v ReportStatusCodeLib (using DxeReportStatusCodeLib instance) | v Raise/RestoreTpl The call of Raise/RestoreTpl APIs will re-enable BSP interrupts. Hence, this commit refine the calling sequence to ensure BSP interrupts before leaving CoreExitBootServices(). Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/PiSmmCore: fix #PF caused by freeing read-only memoryJian J Wang2018-03-161-0/+22
| | | | | | | | | | | | | | | | | | | | | SMM core will add a HEADER before each allocated pool memory and clean up this header once it's freed. If a block of allocated pool is marked as read-only after allocation (EfiRuntimeServicesCode type of pool in SMM will always be marked as read-only), #PF exception will be triggered during memory pool freeing. Normally EfiRuntimeServicesCode type of pool should not be freed in the real world. But some test suites will actually do memory free for all types of memory for the purpose of functionality and conformance test. So this issue should be fixed anyway. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/Core: fix bits operation error on a boundary conditionJian J Wang2018-03-161-6/+10
| | | | | | | | | | | | | | | | If given address is on 64K boundary and the requested bit number is 64, all SetBits(), ClearBits() and GetBits() will encounter ASSERT problem in trying to do a 64 bits of shift, which is not allowed by LShift() and RShift(). This patch tries to fix this issue by turning bits operation into whole integer operation in such situation. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/PiSmmCore: fix bits operation error on a boundary conditionJian J Wang2018-03-161-6/+10
| | | | | | | | | | | | | | | | If given address is on 64K boundary and the requested bit number is 64, all SetBits(), ClearBits() and GetBits() will encounter ASSERT problem in trying to do a 64 bits of shift, which is not allowed by LShift() and RShift(). This patch tries to fix this issue by turning bits operation into whole integer operation in such situation. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/Core: allow HeapGuard even before CpuArchProtocol installedJian J Wang2018-03-164-1/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the fact that HeapGuard needs CpuArchProtocol to update page attributes, the feature is normally enabled after CpuArchProtocol is installed. Since there're some drivers are loaded before CpuArchProtocl, they cannot make use HeapGuard feature to detect potential issues. This patch fixes above situation by updating the DXE core to skip the NULL check against global gCpu in the IsMemoryTypeToGuard(), and adding NULL check against gCpu in SetGuardPage() and UnsetGuardPage() to make sure that they can be called but do nothing. This will allow HeapGuard to record all guarded memory without setting the related Guard pages to not- present. Once the CpuArchProtocol is installed, a protocol notify will be called to complete the work of setting Guard pages to not-present. Please note that above changes will cause a #PF in GCD code during cleanup of map entries, which is initiated by CpuDxe driver to update real mtrr and paging attributes back to GCD. During that time, CpuDxe doesn't allow GCD to update memory attributes and then any Guard page cannot be unset. As a result, this will prevent Guarded memory from freeing during memory map cleanup. The solution is to avoid allocating guarded memory as memory map entries in GCD code. It's done by setting global mOnGuarding to TRUE before memory allocation and setting it back to FALSE afterwards in GCD function CoreAllocateGcdMapEntry(). Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
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