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* MdeModulePkg/Ufs :Coverity scan flags multiple issues in edk2-stable202205Sivaparvathi C2022-11-042-13/+24
| | | | | | | | | | | BugZilla ID:https://bugzilla.tianocore.org/show_bug.cgi?id=3989 Added changes to resolve the Coverity Issues in UFS driver Cc: Vasudevan Sambandan <vasudevans@ami.com> Cc: Sundaresan Selvaraj <sundaresans@ami.com> Signed-off-by: Sivaparvathi Chellaiah <sivaparvathic@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/scsi :Coverity scan flags multiple issues in edk2-stable202205Sivaparvathi C2022-11-042-10/+19
| | | | | | | | | Added changes to resolve the SCSI driver Coverity issues. Cc: Vasudevan Sambandan <vasudevans@ami.com> Cc: Sundaresan Selvaraj <sundaresans@ami.com> Signed-off-by: Sivaparvathi chellaiah <sivaparvathic@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/PiSmmCore: SmmEntryPoint underflow (CVE-2021-38578)Miki Demeter2022-11-045-15/+60
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3387 Added use of SafeIntLib to validate values are not causing overflows or underflows in user controlled values when calculating buffer sizes. Signed-off-by: Miki Demeter <miki.demeter@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Update Dxe to handle unaccepted memory typeMin M Xu2022-11-012-17/+52
| | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3937 Unaccepted memory is a kind of new memory type, CoreInitializeGcdServices() and CoreGetMemoryMap() are updated to handle the unaccepted memory type. Ref: microsoft/mu_basecore@97e9c31 Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Min Xu <min.m.xu@intel.com>
* MdePkg: Add UEFI Unaccepted memory definitionMin M Xu2022-11-011-0/+25
| | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3937 Plase refer to: UEFI Spec v2.9 Table 7-5 Memory Type Usage before ExitBootServices() Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Min Xu <min.m.xu@intel.com>
* MdeModulePkg: Add PrePiHob.hMin M Xu2022-11-011-0/+20
| | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3937 BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED is defined for unaccepted memory. But this defitinion has not been officially in the PI spec. Base on the code-first we define BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED at MdeModulePkg/Include/Pi/PrePiHob.h. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Min Xu <min.m.xu@intel.com>
* MdeModulePkg/ScsiDiskDxe: Update proper device name for ScsiDisk driveCheripally Gopi2022-10-313-2/+62
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4100 ScsiDiskDxe driver updates ControllerNameTable with common string "SCSI Disk Device" for all SCSI disks. Due to this, when multiple SCSI disk devices connected, facing difficulty in identifying correct SCSI disk device. As per SCSI spec, standard Inquiry Data is having the fields to know Vendor and Product information. Updated "ControllerNameTable" with Vendor and Product information. So that, device specific name can be retrieved using ComponentName protocol. Cc: Vasudevan Sambandan <vasudevans@ami.com> Cc: Sundaresan Selvaraj <sundaresans@ami.com> Signed-off-by: Cheripally Gopi <gopic@ami.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Fix spelling error in PciSioSerialDxeNate DeSimone2022-10-251-1/+1
| | | | | | | | | | | | gSerialDevTempate should be gSerialDevTemplate Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* Ps2KbdCtrller: Make wait for SUCCESS after BAT non-fatalMatt DeVillier2022-10-251-7/+1
| | | | | | | | | | | | | | Recent model Chromebooks only return ACK, but not BAT_SUCCESS, which causes hanging and failed ps2k init. To mitigate this, make the absence of BAT_SUCCESS reply non-fatal, and reduce the no-reply timeout from 4s to 1s. Tested on google/dracia and purism/librem_14 Acked-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
* MdeModulePkg/XhciDxe: Add boundary check for TRB ring allocationjdzhang2022-10-203-22/+47
| | | | | | | | | | | According the Xhci Spec, TRB Rings may be larger than a Page, however they shall not cross a 64K byte boundary, so add a parameter to indicate whether the memory allocation is for TRB Rings or not. It will ensure the allocation not crossing 64K boundary in UsbHcAllocMemFromBlock if the memory is allocated for TRB Rings. Signed-off-by: jdzhang <jdzhang@kunluntech.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* Fix bug on SRIOV ReservedBusNum when ARI enable.Foster Nong2022-10-143-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a device which support both features SR-IOV/ARI has multi functions, which maybe support 8-255. After enable ARI forwarding in the root port and ARI Capable Hierarchy in the SR-IOV PF0. The device will support and expose multi functions(0-255) with ARI ID routing. In next device loop in below for() code, actually it still be in the same SR-IOV device, and just some PF which is over 8 or higher one(n*8), PciAllocateBusNumber() will allocate bus number(ReservedBusNum - TempReservedBusNum)) for this PF. if reset TempReservedBusNum as 0 in this case,it will allocate wrong bus number for this PF because TempReservedBusNum should be total previous PF's reserved bus numbers. code: for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) { TempReservedBusNum = 0; for (Func = 0; Func <= PCI_MAX_FUNC; Func++) { // // Check to see whether a pci device is present // Status = PciDevicePresent ( PciRootBridgeIo, &Pci, StartBusNumber, Device, Func ); ... Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber); The solution is add a new flag IsAriEnabled to help handle this case. if ARI is enabled, then TempReservedBusNum will not be reset again during all functions(1-255) scan with checking flag IsAriEnabled. Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Fixed extra 1 SR-IOV reserved busFoster Nong2022-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Below code will calculate the reserved bus number for the each PF. Based on the VF routing ID algorithm, PFRid and LastVF in below code already sure that "All VFs and PFs must have distinct Routing IDs". PF will be assigned Routing ID based on secBusNumber, ReservedBusNum will add into SubBusNumber directly. So the SR-IOV device will be assigned bus range as SecBusNumber ~ (SubBusNumber=(SecBusNumber + ReservedBusNum)). Thus "+1" in below code will cause extra 1 bus, and introduce a bus hole. PFRid = EFI_PCI_RID (Bus, Device, Func); LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride; PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1); In SR-IOV spec, there is a note in section 2.1.2: Note: Bus Numbers are a constrained resource. Devices are strongly encouraged to avoid leaving ?holes? in their Bus Number usage to avoid wasting Bus Numbers So the issue can be fixed with below code change. PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus); https://bugzilla.tianocore.org/show_bug.cgi?id=4069 Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/DxeIplPeim : LoongArch DxeIPL implementation.Chao Li2022-10-142-1/+68
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053 Implement LoongArch DxeIPL instance. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Guomin Jiang <guomin.jiang@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/CapsuleRuntimeDxe: Add LoongArch64 architecture.Chao Li2022-10-141-4/+5
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053 Add LoongArch in INF for building CapsuleRuntimeDxe LoongArch64 image. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Guomin Jiang <guomin.jiang@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg/Logo: Add LoongArch64 architecture.Chao Li2022-10-141-1/+2
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053 Add LoongArch64 architecture to the Logo. Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdeModulePkg: Use LockBoxNullLib for LOONGARCH64Chao Li2022-10-141-2/+2
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053 LoongArch doesn't have SMM by now. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg: Handle InitialVFs=0 case for SR-IOVFoster Nong2022-10-081-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per the section 3.3.5 SR-IOV spec v1.1, InitialVFs (0ch). InitialVFs indicates to SR-PCIM the number of VFs that are initially associated with the PF. The minimum value of InitialVFs is 0. Below code is used to calculate SR-IOV reserved bus number, if InitialVFs =0, it maybe calculate the wrong bus number in this case. LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride we can fix it with below code: if (PciIoDevice->InitialVFs == 0) { PciIoDevice->ReservedBusNum = 0; } else { PFRid = EFI_PCI_RID (Bus, Device, Func); LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride; // // Calculate ReservedBusNum for this PF // PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1); // // Calculate ReservedBusNum for this PF // PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1); } https://bugzilla.tianocore.org/show_bug.cgi?id=4069 Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/UefiBootManagerLib: Add Disk Info support for UfsJeff Brasen2022-10-062-1/+4
| | | | | | | Add support for getting disk info from UFS devices. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBufferJeff Brasen via groups.io2022-10-011-2/+62
| | | | | | | | | | | Add support for partial free of non cached buffers. If a request for less than the full size is requested new allocations for the remaining head and tail of the buffer are added to the list. Added verification that Buffer is EFI_PAGE_SIZE aligned. The XHCI driver does this if the page size for the controller is >4KB. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/XhciDxe: Input context update for Evaluate Context commandjdzhang2022-09-271-2/+12
| | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4074 Update XhcEvaluateContext/XhcEvaluateContext64 to properly initialize the input context for Evaluate Context command. Signed-off-by: jdzhang <jdzhang@kunluntech.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/AhciPei: Fix MMIO base assignmentCzajkowski, Maciej2022-09-151-2/+4
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4041 There is a mistake in getting MMIO base using PciDevicePpi that can lead to the data corruption. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Maciej Czajkowski <maciej.czajkowski@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg SmbiosMeasurementDxe: Add Type4 CurrentSpeed to filter tableHeng Luo2022-09-141-1/+2
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4051 The Type4 CurrentSpeed field may be various. So this patch adds it into the filter table. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdeModulePkg: Use configurable PCD for AHCI command retriesBaraneedharan Anbazhagan2022-09-134-2/+11
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4011 AHCI commands are retried internally which prevents platform feature like drive password to process correctly entered password on subsequent attempts. PCD allows the platform to determine the number of retries. Signed-off-by: Baraneedharan Anbazhagan <anbazhagan@hp.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Fix imbalanced debug macrosMichael Kubacki2022-09-096-9/+9
| | | | | | | | | | | | | | | | | | | Updates debug macros in the package that have an imbalanced number of print specifiers to arguments. These changes try to preserve what was likely intended by the author. In cases information was missing due to the bug, the specifier may be removed since it was not previously accurately printing the expected value. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/NvmExpressPei: Use PCI_DEVICE_PPI to manage Nvme deviceChen, Xiao X2022-09-014-247/+483
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4017 This change modifies NvmExpressPei library to allow usage both EDKII_PCI_DEVICE_PPI and EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI to manage Nvme device. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Xiao X Chen <xiao.x.chen@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/DumpDynPcd: Remove unsupported format specifiersKonstantin Aladyshev2022-08-171-14/+14
| | | | | | | | | | | Some print statements use format specifiers like %N/%H/%E/%B that are only supported in the shell print functions. In the ordinary 'Print' function they are just displayed as letters N/H/E/B. Remove these unsupported format specifiers from the 'Print' statements to fix the issue. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Update the SMBIOS version by UPLKasimX Liu2022-08-152-8/+34
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4013 For the SMBIOS version can be update by UPL,we create the gUniversalPayloadSmbios3TableGuid HOB to store the value then updated version. Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: KasimX Liu <kasimx.liu@intel.com>
* MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting pagetableDun Tan2022-08-151-6/+1
| | | | | | | | | | | | Remove clearing CR0.WP when marking the memory used for page table as read-only in the page table itself created by DxeIpl. This page table address is written to Cr3 after these protection steps. Till this, the memory used for page table is always RW. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Enhance bus scan for all root bridge instancesFoster Nong2022-08-121-4/+14
| | | | | | | | | | | | Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=4000 Change flow to bus scan all root bridge instances even when any one root bridge meet bus resource OUT_OF_RESOURCE case. thus platform handler of "EfiPciHostBridgeEndBusAllocation" has an chance to do relative pci bus rebalance to handle this case. Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Move CPU_EXCEPTION_INIT_DATA to UefiCpuPkgLiu, Zhiguang2022-08-091-67/+0
| | | | | | | | | | | | | | | Since the API InitializeSeparateExceptionStacks is simplified and does't use the struct CPU_EXCEPTION_INIT_DATA, CPU_EXCEPTION_INIT_DATA become a inner implementation of CpuExcetionHandlerLib. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Simplify InitializeSeparateExceptionStacksLiu, Zhiguang2022-08-093-14/+20
| | | | | | | | | | | | | | | | Hide the Exception implementation details in CpuExcetionHandlerLib and caller only need to provide buffer Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdeModulePkg/AhciPei: Use PCI_DEVICE_PPI to manage AHCI deviceCzajkowski, Maciej2022-08-055-214/+382
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907 This change modifies AhciPei library to allow usage both EDKII_PCI_DEVICE_PPI and EDKII_PEI_ATA_AHCI_HOST_CONTROLLER_PPI to manage ATA HDD working under AHCI mode. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Maciej Czajkowski <maciej.czajkowski@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg: Add EDKII_PCI_DEVICE_PPI definitionCzajkowski, Maciej2022-08-052-0/+35
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907 This commit introduces EDKII_PCI_DEVICE_PPI. The purpose of this PPI is to provide a way of accessing PCI devices to drvice drivers such as NvmExpressPei or AhciPei. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Maciej Czajkowski <maciej.czajkowski@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/Include: Long debug string is truncated to 104 charCosmo Lai2022-07-234-17/+9
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3986 The EFI_STATUS_CODE_DATA_MAX_SIZE is defined as 200 in MdeModulePkg. After reducing 96byte buffer for variable parameters it is limited to only 104 char debug string. This is a non-necessary limitation. This change sets EFI_STATUS_CODE_DATA_MAX_SIZE to 0x200, and moves MAX_EXTENDED_DATA_SIZE definition to the same header file with value of EFI_STATUS_CODE_DATA_MAX_SIZE + sizeof (EFI_STATUS_CODE_DATA) which is used in ReportStatusCodeLib to support longer debug string. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Cosmo Lai <cosmo.lai@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* MdeModulePkg/SetupBrowserDxe:Follow spec'd way to reconnect driverWalon Li2022-07-222-9/+4
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3952 In UEFI spec, it defines reconnect timing that will be activated upon exiting of the formset or the browser. However, we did't use this kind of way to check reconnect conditioncode. Code only blocks reconnect if page is updated dynamically. That's not matched spec'd way. We should check current formset whether is exiting, then reconnect driver. Signed-off-by: Walon Li <walon.li@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/CoreDxe: Allow DXE Drivers to use untested memoryStacy Howell2022-07-221-0/+14
| | | | | | | | | | | | REF: https://https://bugzilla.tianocore.org/show_bug.cgi?id=3795 Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Updated CoreInternalAllocatePages() to call PromoteMemoryResource() and re-attempt the allocation if unable to convert the specified memory range Signed-off-by: Stacy Howell <stacy.howell@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/XhciDxe: Add access xHCI Extended Capabilities PointerIan Chiu2022-06-274-16/+296
| | | | | | | | | | | | | | | | | | | | | | | Add support process Port Speed field value of PORTSC according to Supported Protocol Capability (define in xHCI spec 1.1) REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3914 The value of Port Speed field in PORTSC bit[10:13] (xHCI spec 1.1 section 5.4.8) should be change to use this value to query thru Protocol Speed ID (PSI) (xHCI spec 1.1 section 7.2.1) in xHCI Supported Protocol Capability and return the value according the Protocol Speed ID (PSIV) Dword. With this mechanism may able to detect more kind of Protocol Speed in USB3 and also compatiable with three kind of speed of USB2. Cc: Jenny Huang <jenny.huang@intel.com> Cc: More Shih <more.shih@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Ian Chiu <Ian.chiu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/XhciDxe: Check return value of XHC_PAGESIZE registerLuo, Heng2022-06-221-2/+8
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954 Report error if reserved bits are not 0 for PageSize Cc: Ray Ni <ray.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* DxeMain: Fix the bug that StackGuard is not enabledRay Ni2022-06-141-0/+8
| | | | | | | | | | | | Commit e7abb94d1 removed InitializeCpuExceptionHandlersEx and updated DxeMain to call InitializeCpuExceptionHandlers for exception setup. But the old behavior that calls *Ex() sets up the stack guard as well. To match the old behavior, the patch calls InitializeSeparateExceptionStacks. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn>
* CpuException: Add InitializeSeparateExceptionStacksRay Ni2022-06-103-38/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Today InitializeCpuExceptionHandlersEx is called from three modules: 1. DxeCore (links to DxeCpuExceptionHandlerLib) DxeCore expects it initializes the IDT entries as well as assigning separate stacks for #DF and #PF. 2. CpuMpPei (links to PeiCpuExceptionHandlerLib) and CpuDxe (links to DxeCpuExceptionHandlerLib) It's called for each thread for only assigning separate stacks for #DF and #PF. The IDT entries initialization is skipped because caller sets InitData->X64.InitDefaultHandlers to FALSE. Additionally, SecPeiCpuExceptionHandlerLib, SmmCpuExceptionHandlerLib also implement such API and the behavior of the API is simply to initialize IDT entries only. Because it mixes the IDT entries initialization and separate stacks assignment for certain exception handlers together, in order to know whether the function call only initializes IDT entries, or assigns stacks, we need to check: 1. value of InitData->X64.InitDefaultHandlers 2. library instance This patch cleans up the code to separate the stack assignment to a new API: InitializeSeparateExceptionStacks(). Only when caller calls the new API, the separate stacks are assigned. With this change, the SecPei and Smm instance can return unsupported which gives caller a very clear status. The old API InitializeCpuExceptionHandlersEx() is removed in this patch. Because no platform module is consuming the old API, the impact is none. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com>
* CpuException: Remove InitializeCpuInterruptHandlersRay Ni2022-06-102-53/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | InitializeCpuExceptionHandlers() expects caller allocates IDT while InitializeCpuInterruptHandlers() allocates 256 IDT entries itself. InitializeCpuExceptionHandlers() fills max 32 IDT entries allocated by caller. If caller allocates 10 entries, the API just fills 10 IDT entries. The inconsistency between the two APIs makes code hard to unerstand and hard to share. Because there is only one caller (CpuDxe) for InitializeCpuInterruptHandler(), this patch updates CpuDxe driver to allocates 256 IDT entries then call InitializeCpuExceptionHandlers(). This is also a backward compatible change. With this change, InitializeCpuInterruptHandlers() is removed completely. And InitializeCpuExceptionHandlers() fills max 32 entries for PEI and SMM instance, max 256 entries for DXE instance. Such behavior matches to the original one. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* MdeModulePkg/UniversalPayload: Align Identifier value with UPL specGua Guo2022-05-271-1/+1
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3933 URL: https://universalpayload.github.io/documentation/ Currently, Identifier value is "UPLD", it needs to have correct value "PLDH" based on Universal Payload Specification spec section 2.12.2 Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Guo Dong <guo.dong@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* MdeModulePkg/FaultTolerantWrite: Consume Variable Flash InfoMichael Kubacki2022-05-198-60/+63
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3479 Adds support to the UEFI variable fault tolerant write (FTW) drivers to receive FTW base and size information dynamically via the Variable Flash Information library. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg/Variable: Consume Variable Flash InfoMichael Kubacki2022-05-1910-34/+56
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3479 Updates VariableRuntimeDxe, VariableSmm, and VariableStandaloneMm to acquire variable flash information from the Variable Flash Information library. Note: This introduces a dependency on VariableFlashInfoLib in these modules. Therefore, a platform building the variable modules must specify an instance of VariableFlashInfoLib in their platform build. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg/VariableFlashInfoLib: Add initial libraryMichael Kubacki2022-05-196-0/+313
| | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3479 Adds a new library class VariableFlashInfoLib that abstracts access to variable flash information. The instance provided first attempts to retrieve information from the Variable Flash Info HOB. If that HOB is not present, it falls back to the PCDs defined in MdeModulePkg. This fall back behavior provides backward compatibility for platforms that only provide PCDs but also allows platforms that need to dynamically provide the information using the Variable Flash Info HOB to do so at runtime. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg: Add Variable Flash Info HOBMichael Kubacki2022-05-192-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3479 Adds a new GUID that is used to identify a HOB that passes variable flash information to UEFI variable drivers in HOB consumption phases such as DXE, Traditional MM, and Standalone MM. This information was previously passed directly with PCDs such as EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase and gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize. However, the Standalone MM variable driver instance does not have direct access to the PCD database. Therefore, this HOB will first be considered as the source for variable flash information and if platforms do not produce the HOB, reading the information from the PCDs directly will be a backup to provide backward compatibility. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg: PiSmmCore: Inspect memory guarded with pool headersKun Qin2022-05-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3488 Current free pool routine from PiSmmCore will inspect memory guard status for target buffer without considering pool headers. This could lead to `IsMemoryGuarded` function to return incorrect results. In that sense, allocating a 0 sized pool could cause an allocated buffer directly points into a guard page, which is legal. However, trying to free this pool will cause the routine changed in this commit to read XP pages, which leads to page fault. This change will inspect memory guarded with pool headers. This can avoid errors when a pool content happens to be on a page boundary. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/PCD: Pcd initialize DXE have assertGua Guo2022-05-091-0/+5
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3917 When PlatformPkg.dsc has multiple SKU IDs but didn't exist delta PCD, System will hang on BuildPcdDxeDataBase. Ideally, if didn't exist delta PCD by different SKU ID, UpdatePcdDatabase () shouldn't return EFI_NOT_FOUND. Signed-off-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/GraphicsConsoleDxe: add modesGerd Hoffmann2022-04-221-1/+4
| | | | | | | | | | | | | | Add modes for a few common display resolutions higher than 800x600, specifically 1024x768, 1280x800 and 1920x1080, so ConSplitterDxe has more options available. The mode list is not use as-is, InitializeGraphicsConsoleTextMode() will check the list and filter out any modes which don't fit to the screen, so this will also work fine for small displays. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* MdeModulePkg/HiiDatabase: Fix Setup numeric default value incorrect issueChen, Lin Z2022-04-082-0/+47
| | | | | | | | | | | | When default/manufacturing flag get removed from numeric varid, it can't get default value from StructurePcd in 'UpdateDefaultSettingInFormPackage' function since there is no EFI_IFR_DEFAULT_OP opcode in IFR file. Add a chance to get numeric default value from StructurePcd in the case that numeric minimum value will be used as default value. Signed-off-by: Chen Lin Z <lin.z.chen@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 18:00:46 +0000