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* MdeModulePkg/MdeModulePkg.dsc: add MM_STANDALONE FTW and variable modulesArd Biesheuvel2019-01-161-0/+9
| | | | | | | | | | | | | For build testing coverage, add the newly introduced MM_STANDALONE versions of the fault tolerant write (FTW) and variable runtime driver to MdeModulePkg.dsc. Note that the resulting binaries will not be able to run, since they rely on dummy implementations of MemoryAllocationLib and HobLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>.
* MdeModulePkg/VarCheckLib: add MM_STANDALONE supportArd Biesheuvel2019-01-161-1/+1
| | | | | | | | | | Add MM_STANDALONE to the list of permitted module types of the VarCheckLib library implementation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>.
* MdeModulePkg/AuthVariableLibNull: add MM_STANDALONE supportArd Biesheuvel2019-01-161-1/+1
| | | | | | | | | | Add MM_STANDALONE to the list of permitted module types of the AuthVariableLibNull library implementation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>.
* MdeModulePkg/MdeModulePkg/dsc: move DxeDebugSupportDxe to x86 only sectionArd Biesheuvel2019-01-161-1/+1
| | | | | | | | | | | MdeModulePkg/Universal/DebugSupportDxe/DebugSupportDxe.inf does not build for AARCH64 since it does not provide the needed PlDebugSupport.h header. So move the module to a x86 only section. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>.
* MdeModulePkg: implement NULL instance of MemoryAllocationLib library classArd Biesheuvel2019-01-163-0/+633
| | | | | | | | | | | In order to permit MM_STANDALONE modules to be built without relying on StandaloneMmPkg, provide a BASE type NULL implementation of MemoryAllocationLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>.
* MdeModulePkg: implement NULL instance of HobLib library classArd Biesheuvel2019-01-163-0/+600
| | | | | | | | | | In order to permit MM_STANDALONE modules to be built without relying on StandaloneMmPkg, provide a BASE type NULL implementation of HobLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>.
* MdeModulePkg/VariableRuntimeDxe: implement standalone MM versionArd Biesheuvel2019-01-162-0/+231
| | | | | | | | | | | Reuse most of the existing code to implement a variable runtime driver that will be able to execute in the context of standalone MM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/VariableRuntimeDxe: factor out boot service accessesArd Biesheuvel2019-01-165-56/+222
| | | | | | | | | | | | | | In preparation of providing a standalone MM based variable runtime driver, move the existing SMM driver to the new MM services table, and factor out some pieces that are specific to the traditional driver, mainly related to the use of UEFI boot services, which are not accessible to standalone MM drivers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/FaultTolerantWriteDxe: implement standalone MM versionArd Biesheuvel2019-01-162-0/+186
| | | | | | | | | | Implement a new version of the fault tolerant write driver that can be used in the context of a standalone MM implementation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/FaultTolerantWriteDxe: factor out boot service accessesArd Biesheuvel2019-01-167-48/+233
| | | | | | | | | | | | | | In preparation of providing a standalone MM based FTW driver, move the existing SMM driver to the new MM services table, and factor out some pieces that are specific to the traditional driver, mainly related to the use of UEFI boot services, which are not accessible to standalone MM drivers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/MdeModulePkg.dsc: add MmServicesTableLib resolutionArd Biesheuvel2019-01-161-0/+1
| | | | | | | | | | | The SMM based FTW and variable drivers are going to depend on MmServicesTableLib after a subsequent patch, so add a resolution for it to MdeModulePkg.dsc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/BootScriptExecuteorDxe: check 64BIT_WAKE_F in FACS.OSPMFlagsEric Dong2019-01-152-4/+4
| | | | | | | | | | | | | | | | | | ((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) In above code, Facs->OspmFlags should be used instead. EFI_ACPI_4_0_OSPM_64BIT_WAKE__F is a bit in OSPM Enabled Firmware Control Structure Flags field, not in Firmware Control Structure Feature Flags. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1430 Cc: Aleksiy <oleksiyy@ami.com> Cc: Jian Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg: fix comments in BaseSortLibJaben Carsey2019-01-101-13/+9
| | | | | | | | | | | The comments are incorrect for the base version of this lib. Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jaben Carsey <jaben.carsey@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/NonDiscoverablePciDevice: Remove the redundant checkDandan Bi2019-01-081-5/+3
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1422 if (Attributes) { if ((Attributes & (~(DEV_SUPPORTED_ATTRIBUTES))) != 0) { return EFI_UNSUPPORTED; } } In above code block, "If ((Attributes & (~(DEV_SUPPORTED_ATTRIBUTES))) != 0)" is TRUE, the Attributes must be not 0. So we can remove the redundant check "if (Attributes)". Cc: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Fix VS2015 IA32 NOOPT build failureHao Wu2019-01-051-4/+4
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1425 This commit will resolve the VS2015 IA32 NOOPT build failure within SdMmcPciHcDxe. More specifically, this commit will use BaseLib API RShiftU64() to perform right-shift operations for UINT64 type operators. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Bi Dandan <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Add SDMMC HC v4 and above Support.Ashish Singhal2019-01-036-83/+366
| | | | | | | | | | | | | | | | | | | | | | Add SDMA, ADMA2 and 26b data length support. If V4 64 bit address mode is supported in capabilities register, program controller to enable V4 host mode and use appropriate SDMA registers supporting 64 bit addresses. If V4 64 bit address mode is supported in capabilities register, program controller to enable V4 host mode and use appropriate ADMA descriptors supporting 64 bit addresses. If host controller version is above V4.0, enable ADMA2 with 26b data length support for better performance. HC 2 register is configured to use 26 bit data lengths and ADMA2 descriptors are configured appropriately. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1359 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg: Remove PcdPeiCoreMaxXXX PCDsStar Zeng2019-01-022-25/+0
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 The codes have been updated to not use PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported. The patch removes them in MdeModulePkg.dec. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/Variable: Update to consume SpeculationBarrierHao Wu2018-12-257-32/+38
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1417 Since BaseLib API AsmLfence() is a x86 arch specific API and should be avoided using in generic codes, this commit replaces the usage of AsmLfence() with arch-generic API SpeculationBarrier(). Please note that speculation execution barriers are intended to be asserted for SMM codes, hence, this commit still preserve an empty implementation of the speculation execution barrier for the DXE codes. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/SmmLockBox: Update to consume SpeculationBarrierHao Wu2018-12-251-6/+6
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1417 Since BaseLib API AsmLfence() is a x86 arch specific API and should be avoided using in generic codes, this commit replaces the usage of AsmLfence() with arch-generic API SpeculationBarrier(). Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/FaultTolerantWrite: Update to consume SpeculationBarrierHao Wu2018-12-251-4/+4
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1417 Since BaseLib API AsmLfence() is a x86 arch specific API and should be avoided using in generic codes, this commit replaces the usage of AsmLfence() with arch-generic API SpeculationBarrier(). Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg: Delete UefiPxeBcDxe in MdeModulePkg.Siyuan Fu2018-12-2415-7905/+0
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1278 This patch is to delete the UefiPxeBcDxe driver in MdeModulePkg. The driver will not be maintained and can't co-work with the dual-stack UefiPxeBcDxe in NetworkPkg. People should use below NetworkPkg drivers instead: NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf Which is actively maintained with more bug fixes and new feature support. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg: Delete IScsiDxe in MdeModulePkg.Siyuan Fu2018-12-2433-11846/+0
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1278 This patch is to delete the IScsiDxe driver in MdeModulePkg. The driver will not be maintained and can't co-work with the dual-stack IScsiDxe in NetworkPkg. People should use below NetworkPkg drivers instead: NetworkPkg/IScsiDxe/IScsiDxe.inf Which is actively maintained with more bug fixes and new feature support. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg: Delete Tcp4Dxe in MdeModulePkg.Siyuan Fu2018-12-2423-12847/+0
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1278 This patch is to delete the Tcp4Dxe driver in MdeModulePkg. The driver will not be maintained and can't co-work with the dual-stack TcpDxe in NetworkPkg. People should use below NetworkPkg drivers instead: NetworkPkg/TcpDxe/TcpDxe.inf Which is actively maintained with more bug fixes and new feature support. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/Dxe/Page: take MAX_ALLOC_ADDRESS into accountArd Biesheuvel2018-12-201-26/+26
| | | | | | | | | | | Take MAX_ALLOC_ADDRESS into account in the implementation of the page allocation routines, so that they will only return memory that is addressable by the CPU at boot time, even if more memory is available in the GCD memory map. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/Dxe/Gcd: disregard memory above MAX_ALLOC_ADDRESSArd Biesheuvel2018-12-201-4/+4
| | | | | | | | | | | | | Update the GCD memory map initialization code so it disregards memory that is not addressable by the CPU at boot time. This only affects the first memory descriptor that is added, other memory descriptors are permitted that describe memory ranges that may be accessible to the CPU itself only when executing under the OS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxPpiSupportedStar Zeng2018-12-195-199/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update code to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxPpiSupported in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxFvSupportedStar Zeng2018-12-194-24/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update PeiCore to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxFvSupported in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxPeimPerFvStar Zeng2018-12-194-108/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update code to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxPeimPerFv in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* MdeModulePkg/PciBus: Fix system hang when no PCI Option ROM existsRuiyu Ni2018-12-171-4/+6
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1394 When there is no PCI option ROM exists, today's logic still creates virtual BAR for option ROM using Length = 0, Alignment = (-1). It causes the final MEM32 alignment requirement is as big as 0xFFFFFFFF_FFFFFFFF. The patch fixes this issue by only creating virtual BAR for option ROM when there is PCI option ROM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chiu Chasel <chasel.chiu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* MdeModulePkg/NonDiscoverablePciDeviceDxe: add missing validationVladimir Olovyannikov2018-12-171-1/+49
| | | | | | | | | | UEFI SCT crashed and failed in NonDiscoverablePciDeviceDxe becase required checks were not performed. Perform parameters validation in NonDiscoverablePciDeviceDxe. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
* MdeModulePkg/FileExplorerLib: avoid packed struct for program dataArd Biesheuvel2018-12-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Struct packing is only necessary for data structures whose in-memory representation is covered by the PI or UEFI specs, and may deviate from the ordinary C rules for alignment. So in case of FileExplorerLib, this applies to the device path struct only, and other structures used to carry program data should not be packed, or we may end up with alignment faults on architectures such as ARM, which don't permit load/store double or multiple instructions to access memory locations that are not 32-bit aligned. E.g., the following call in FileExplorerLibConstructor() InitializeListHead (&gFileExplorerPrivate.FsOptionMenu->Head); which is emitted as follows for 32-bit ARM/Thumb2 by Clang-5.0 3de0: b510 push {r4, lr} 3de2: 4604 mov r4, r0 ... 3de8: e9c4 4400 strd r4, r4, [r4] 3dec: bd10 pop {r4, pc} will perform a double-word store on the first argument, passed in register r0, assuming that the pointer type of the argument is enough to guarantee that the value is suitably aligned. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/PciBus: Shadow option ROM after BARs are programmedRuiyu Ni2018-12-104-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1376 Today's implementation reuses the 32bit MMIO resource requested by all PCI devices MMIO BARs when shadowing the option ROM. Take a simple example, a system has only one PCI device. It requires 8MB 32bit MMIO and contains a 4MB option ROM. Today's implementation only requests 8MB (max of 4M and 8M) 32bit MMIO from PciHostBridgeResourceAllocation protocol. Let's assume the MMIO range [3GB, 3GB+8MB) is allocated. The 3GB base address is firstly programmed to the option ROM BAR for option ROM shadow. Then the option ROM decoding is turned off and 3GB base address is programmed to the 32bit MMIO BAR. It doesn't cause issues when the device doesn't request too much MMIO. But when the device contains a 64bit MMIO BAR which requests 4GB MMIO and a 4MB option ROM. Let's assume [3GB, 3GB+8MB) 32bit MMIO range is allocated for the option ROM. When the option ROM is being shadowed, 64bit MMIO BAR is programmed to value 0, which means [0, 4GB) MMIO is given to the 64bit BAR. The range overlaps with the option ROM range which may cause the device malfunction (e.g.: option ROM cannot be read out) when the device has two separate decoders: one for MMIO BAR, the other for option ROM. The patch requests dedicated MEM32 resource for Option ROMs and moves the Option ROM shadow logic after all MMIO BARs are programmed. The MMIO BAR setting to 0 when shadowing Option ROM is also skipped because the MMIO BAR already contains the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg: Correct PCD name in MdeModulePkg.uniLiming Gao2018-12-031-2/+2
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1363 New PCD PcdVpdBaseAddress64 is added in MdeModulePkg.dec. Its string token in MdeModulePkg.uni should match to its name. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Bi Dandan <dandan.bi@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Bi Dandan <dandan.bi@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/BaseSortLib: Enable for all module typesJeff Brasen2018-11-291-2/+2
| | | | | | | | | | Expose BaseSortLib for use in SEC and PEI phases. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg PCD: Add DynamicEx PcdVpdBaseAddress64 for non SPI platformLiming Gao2018-11-278-4/+54
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1356 Current PcdVpdBaseAddress is 32bit static Pcd. NON SPI platform needs to configure it as Dynamic PCD. Emulator platform (such as NT32) may set its value to 64bit address. To meet with this usage, 64bit DynamicEx PcdVpdBaseAddress64 is introduced. If its value is not zero, it will be used. If its value is zero, static PcdVpdBaseAddress will be used. When NON SPI platform enables VPD PCD, they need to set PcdVpdBaseAddress64. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Dandan Bi <dandan.bi@intel.com>
* MdeModulePkg/LockboxNullLib: clean up INF file.Jiewen Yao2018-11-261-1/+1
| | | | | | | | | Remove unused module type restriction for NULL instance. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Variable: add debug logs in VariableServiceSetVariableVijayenthiran Subramaniam2018-11-231-0/+30
| | | | | | | | | | | | | | Print debug messages if size of the VariableName plus DataSize exceeds Max(Auth|Voltaile)VariableSize bytes. The messages will be useful if any platform specific value of Max(Auth|Voltaile)VariableSize PCDs have to be changed. Cc: Star Zeng <star.zeng@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/DisplayEngine: Remove useless NULL ptr check for NewPosDandan Bi2018-11-211-1/+2
| | | | | | | | | | | | | | | | | | | In function UiDisplayMenu, the NewPos ptr which used to point to the highlight menu entry. It will always point to the menu entry which need to be highlighted or the gMenuOption menu if the highlight menu is not found. So we can remove the NULL ptr check for NewPos in this function. And add the ASSERT code to avoid if any false positive reports of NULL pointer dereference issue raised from static analysis. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequencyMarcin Wojtas2018-11-207-22/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SdMmc host controllers are run by clocks with different frequency than it is reflected in Capabilities Register 1. It is allowed by SDHCI specification ver. 4.2 - if BaseClkFreq field value of the Capability Register 1 is zero, the clock frequency must be obtained via another method. Because the bitfield is only 8 bits wide, a maximum value that could be obtained from hardware is 255MHz. In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient to be used for setting the clock speed in SdMmcHcClockSupply function. This patch adds new UINT32 array ('BaseClkFreq[]') to SD_MMC_HC_PRIVATE_DATA structure for specifying the input clock speed for each slot of the host controller. All routines that are used for clock configuration are updated accordingly. This patch also adds new IN OUT BaseClockFreq field in the Capability callback of the SdMmcOverride, protocol which allows to update BaseClkFreq value. The patch reuses original commit from edk2-platforms: 20f6f144d3a8 ("Marvell/Drivers: XenonDxe: Allow overriding base clock frequency") Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverrideTomasz Michalec2018-11-203-4/+46
| | | | | | | | | | | | | Some SD Host Controlers need to do additional operations after clock frequency switch. This patch add new callback type to NotifyPhase of the SdMmcOverride protocol. It is called after SdMmcHcClockSupply. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocolTomasz Michalec2018-11-205-60/+181
| | | | | | | | | | | | | | | Some SD Host Controllers use different values in Host Control 2 Register to select UHS Mode. This patch adds a new UhsSignaling type routine to the NotifyPhase of the SdMmcOverride protocol. UHS signaling configuration is moved to a common, default routine (SdMmcHcUhsSignaling). After it is executed, the protocol producer can override the values if needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhaseMarcin Wojtas2018-11-202-5/+11
| | | | | | | | | | | | | In order to ensure bigger flexibility in the NotifyPhase routine of the SdMmcOverride protocol, enable using an optional phase-specific data. This will allow to exchange more information between the protocol producer driver and SdMmcPciHcDxe in the newly added callbacks. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg: Remove PcdIdentifyMappingPageTablePtrShenglei Zhang2018-11-192-10/+0
| | | | | | | | | | | | | | | | | | | PcdIdentifyMappingPageTablePtr was used to share page table buffer between modules. Buf after some changes on 2015/07/17, it was useless and could be removed. https://bugzilla.tianocore.org/show_bug.cgi?id=1304 v2: 1.Remove PcdIdentifyMappingPageTablePtr in MdeModulePkg.uni. 2.Update the commit message. Cc: Star Zeng <star.zeng@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/SdDxe: Fix potential NULL pointer accessJeff Brasen2018-11-191-2/+3
| | | | | | | | | | SdReadWrite can be called with a NULL Token for synchronous operations. Add guard for DEBUG print to only print event pointer with Token is not NULL. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/NvmExpressPei: Refine data buffer & len check in PassThruHao Wu2018-11-131-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1142 The fix is similar to commit ebb6c7633bca47fcd5b460a67e18e4a717ea91cc. We found that a similar fix should be applied to the NVMe PEI driver as well. Hence, this one is for the PEI counterpart driver. According to the the NVM Express spec Revision 1.1, for some commands (like Get/Set Feature Command, Figure 89 & 90 of the spec), the Memory Buffer maybe optional although the command opcode indicates there is a data transfer between host & controller (Get/Set Feature Command, Figure 38 of the spec). Hence, this commit refine the checks for the 'TransferLength' and 'TransferBuffer' field of the EDKII_PEI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET structure to address this issue. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* Revert "MdeModulePkg/DisplayEngine: Remove useless NULL ptr check for NewPos"Liming Gao2018-11-111-2/+1
| | | | | | | | | | | | This reverts commit 8cd4e734ccdfbc961c72aeaa8dbd3f5154171f9b. It is not a real bug fix. It should not be pushed after Hard Feature Freeze for edk2-stable201811 tag. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Bi Dandan <dandan.bi@intel.com>
* MdeModulePkg/DisplayEngine: Remove useless NULL ptr check for NewPosDandan Bi2018-11-081-1/+2
| | | | | | | | | | | | | | | | | | | In function UiDisplayMenu, the NewPos ptr which used to point to the highlight menu entry. It will always point to the menu entry which need to be highlighted or the gMenuOption menu if the highlight menu is not found. So we can remove the NULL ptr check for NewPos in this function. And add the ASSERT code to avoid if any false positive reports of NULL pointer dereference issue raised from static analysis. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/Core: fix ineffective guard page issueJian J Wang2018-11-071-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1295 This issue originates from following patch which allows to enable paging if PcdImageProtectionPolicy and PcdDxeNxMemoryProtectionPolicy (in addition to PcdSetNxForStack) are set to enable related features. 5267926134d17e86672b84fd57b438f05ffa68e1 Due to above change, PcdImageProtectionPolicy will be set to 0 by default in many platforms, which, in turn, cause following code in MdeModulePkg\Core\Dxe\Misc\MemoryProtection.c fail the creation of notify event of CpuArchProtocol. 1138: if (mImageProtectionPolicy != 0 || PcdGet64 (PcdDxeNxMemoryProtectionPolicy) != 0) { 1139: Status = CoreCreateEvent ( ... 1142: MemoryProtectionCpuArchProtocolNotify, ... 1145: ); Then following call flow won't be done and Guard pages will not be set as not-present in SetAllGuardPages() eventually. MemoryProtectionCpuArchProtocolNotify() => HeapGuardCpuArchProtocolNotify() => SetAllGuardPages() The solution is removing the if(...) statement so that the notify event will always be created and registered. This won't cause unnecessary code execution because, in the notify event handler, the related PCDs like PcdImageProtectionPolicy and PcdDxeNxMemoryProtectionPolicy will be checked again before doing related jobs. Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/Core: fill logic hole in MemoryProtectionCpuArchProtocolNotifyJian J Wang2018-11-071-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the end of of MemoryProtectionCpuArchProtocolNotify there's cleanup code to free resource. But at line 978, 994, 1005 the function returns directly. This patch use "goto" to replace "return" to make sure the resource is freed before exit. 1029: CoreCloseEvent (Event); 1030: return; There's another memory leak after calling gBS->LocateHandleBuffer() in the same function: Status = gBS->LocateHandleBuffer ( ByProtocol, &gEfiLoadedImageProtocolGuid, NULL, &NoHandles, &HandleBuffer ); HandleBuffer is allocated in above call but never freed. This patch will also add code to free it. Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* Revert "XhciDxe: Use common buffer for AsyncInterruptTransfer"Star Zeng2018-11-073-63/+103
| | | | | | | | | | | | There is concern at the thread https://lists.01.org/pipermail/edk2-devel/2018-November/031951.html. And the time point is a little sensitive as it is near edk2-stable201811. This reverts commit 777920997152a2e68f664241f6080b64ff21edd6. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
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