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* MdePkg: Update DBG2 and SPCR header with NVIDIA 16550 SubtypeAshish Singhal2021-06-012-0/+6
| | | | | | | | | | Add macros for NVIDIA 16550 UART specific debug port subtype in both DBG2 as well as SPCR header file. Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sunny Wang <sunny.wang@arm.com>
* MdePkg: Add new 16550-compatible Serial Port Subtypes to DBG2Marcin Wojtas2021-06-012-0/+6
| | | | | | | | | | | | | | | The Microsoft Debug Port Table 2 (DBG2) specification revision May 31, 2017 adds support for 16550-compatible Serial Port Subtype with parameters defined in Generic Address Structure (GAS) [1] Reflect that in the EDK2 headers. [1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sunny Wang <sunny.wang@arm.com>
* MdePkg: Update IndustryStandard/SmBios.h with processor status dataRebecca Cran2021-02-081-0/+13
| | | | | | | | | Add a bitfield that describes the structure of the byte in the Status field of the SMBIOS Type 4 Processor Information table. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/Tpm2Acpi.h: Add Start Method Specific Parameters for ARM SMCNhi Pham2021-01-251-0/+13
| | | | | | | | | | | Add Start Method Specific Parameters for ARM SMC Start Method described in the TCG ACPI Specification version 1.2, revision 8. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: AEST Table definitionMarc Moisson-Franckhauser2021-01-081-0/+357
| | | | | | | | | | | | | | Bugzilla: 3049 (https://bugzilla.tianocore.org/show_bug.cgi?id=3049) Add definition for the Arm Error Source Table (AEST) described in the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, dated 28 September 2020. (https://developer.arm.com/documentation/den0085/0101/) Signed-off-by: Marc Moisson-Franckhauser <marc.moisson-franckhauser@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Define structures for Resizable BAR CapabilityLuo, Heng2021-01-041-5/+25
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3138 Define structures for Resizable BAR Capability in MdePkg/Include/IndustryStandard/PciExpress21.h, Change ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c to use new structures. Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/include: Add DMAR SATC Table DefinitionSheng Wei2020-12-151-3/+31
| | | | | | | | | | | | | | | | | | | SoC Integrated Address Translation Cache (SATC) reporting structure is one of the Remapping Structure, which is imported since Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture Specification v3.2. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3109 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: Kowalewski Robert <robert.kowalewski@intel.com> Cc: Feng Roger <roger.feng@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE17 field FirmwareVersionRebecca Cran2020-12-101-1/+1
| | | | | | | | "FirmwareVersion" was misspelled "FirwareVersion". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE4 field ProcessorManufacturerRebecca Cran2020-12-101-1/+1
| | | | | | | | | | In SmBios.h, the SMBIOS_TABLE_TYPE4 field "ProcessorManufacture" should be "ProcessorManufacturer". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix typos in SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS structRebecca Cran2020-12-101-11/+11
| | | | | | | | Fix typos of "Processor64BitCapable", "ProcessorEnhancedVirtualization", and Processor128BitCapable. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Fix CXL 1.1 structure layout issuesMichael D Kinney2020-11-171-3/+93
| | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3074 * Fix offset of LinkLayerControlAndStatus in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerAckTimerControl in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerDefeature in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Add CXL_11_SIZE_ASSERT() macro to verify the size of a register layout structure at compile time and use it to verify the sizes of the CXL 1.1 register structures. * Add CXL_11_OFFSET_ASSERT() macro to verify the offset of fields in a register layout structure at compiler time and use it to verify the offset of fields in CXL 1.1 register structures. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ashraf Javeed <ashraf.javeed@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ashraf Javeed <ashraf.javeed@intel.com>
* MdePkg: Definitions for Extended Interrupt FlagsSami Mujawar2020-11-031-0/+11
| | | | | | | | | | | Add Interrupt Vector Flag definitions for Extended Interrupt Descriptor, and macros to test the flags. Ref: ACPI specification 6.4.3.6 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Fix SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS to be UINT16Rebecca Cran2020-10-301-11/+11
| | | | | | | | | The ProcessorCharacteristics is a UINT16 field, so the PROCESSOR_CHARACTERISTIC_FLAGS bitfield should be UINT16 too. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Update SmBios.h to add SMBIOS 3.4.0 ARM64 SoC ID fieldRebecca Cran2020-10-301-1/+2
| | | | | | | | | | SMBIOS 3.4.0 defines bit 9 of the Type 4 table Processor Characteristics field to be the ARM64 SoC ID support. Add it to the PROCESSOR_CHARACTERISTIC_FLAGS struct bitfield. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Fix wrong spelling in http11.hAbner Chang2020-10-281-4/+4
| | | | | | | | | | | | | | | | | BZ #3019, https://bugzilla.tianocore.org/show_bug.cgi?id=3019 Fix wrong spelling of CHUNK_TRNASFER_* in HTTP11.h. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Add HTTP definitionsAbner Chang2020-10-161-1/+5
| | | | | | | | | | | | | | | | BZ #2915, https://bugzilla.tianocore.org/show_bug.cgi?id=2915 Add HTTP chunk transfer definitions. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".Wang, Sanyo2020-10-101-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2352 SMBIOS 3.4 spec adds new memory device types (DDR5, LPDDR5) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sanyo Wang <sanyo.wang@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* MdePkg: Correcting EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT definitionPaul2020-08-301-1/+1
| | | | | | | | | | | | | In Acpi10.h, EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT is defined as 0x10, but should be 0x02 per the ACPI Specification. REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2937 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Paul G <paul.grimes@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Add missing definition of SMBIOS type 42h in SmBios.hAbner Chang2020-08-251-0/+9
| | | | | | | | | Add host interface Protocol Type Data Format structure in SmBios.h BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2328 Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include/IndustryStandard: Main CXL headerJaveed, Ashraf2020-07-271-0/+22
| | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611 Introducing the Cxl.h as the main header file to support all versions of Compute Express Link Specification register definitions. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include/IndustryStandard: CXL 1.1 RegistersJaveed, Ashraf2020-07-272-4/+571
| | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611 Register definitions from chapter 7 of Compute Express Link Specification Revision 1.1 are ported into the new Cxl11.h. The CXL Flex Bus registers are based on the PCIe Extended Capability DVSEC structure header, led to the inclusion of upgraded Pci.h. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Include Acpi header fileWasim Khan2020-06-191-0/+2
| | | | | | | | | | ACPI memory mapped configuration space access (MCFG) table requires defination of EFI_ACPI_DESCRIPTION_HEADER. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg/Include: RISC-V definitions.Abner Chang2020-05-071-0/+12
| | | | | | | | | | | | | | | | Add RISC-V processor related definitions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg: Add AML FieldList OpCode definitionsPierre Gondois2020-04-171-0/+8
| | | | | | | | | | | | | | | | | | | | | The ACPI specification, version 6.3, January 2019, defines the Named Objects Encoding for FieldElements in section '20.2.5.2 Named Objects Encoding'. FieldElements can be one of the following: NamedField | ReservedField | AccessField | ExtendedAccessField | ConnectField Some of these keywords are starting with an opcode, allowing to identify their type. E.g.: ReservedField := 0x00 PkgLength This patch adds these FieldElement opcodes definitions to the list of AML Opcode definitions. Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* MdePkg/UefiScsiLib: Set FUA bit for synchronous SCSI Write operationsZurcher, Christopher J2020-04-151-1/+7
| | | | | | | | | | | | | | The FUA (Force Unit Access) bit forces data to be written directly to disk instead of the write cache. This prevents data from being lost if a shutdown or reset is requested immediately after a SCSI write operation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Christopher J Zurcher <christopher.j.zurcher@intel.com>
* MdePkg/Include: Add RISC-V related definitions EDK2 CI.Abner Chang2020-04-031-0/+7
| | | | | | | | | | | | | | | | HTTP/PXE boot RISC-V related definitions for EDK2 CI. BZ:2562: https://bugzilla.tianocore.org/show_bug.cgi?id=2562 Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
* MdePkg/PciExpress40.h: DVSEC definition missingJaveed, Ashraf2020-03-191-0/+28
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598 All registers definition of DVSEC are defined as per the PCI Express Base Specification 4.0 chapter 7.9.6. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Remove FIT table industry standard header file.Siyuan Fu2020-02-141-76/+0
| | | | | | | | | | | | | | Commit c7c964b and dd01704 add header file for FIT table and update MpInitLib to support FIT based microcode shadow operation. There are comments that FIT is Intel specific specification instead of industry standard, which should not be placed in EDK2 MdePkg and UefiCpuPkg. This patch removes the header file added by c7c964b. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add PCCT table signature definitionKrzysztof Koch2020-02-136-1/+36
| | | | | | | | | | | | | | | The Platform Communications Channel Table (PCCT) was defined in: ACPI Specification Version 5.0, Errata A - Published Nov. 13, 2013. Starting from the Acpi50.h header file, there are definitions describing the table but a macro with the table's signature is missing. This patch adds the definition of Platform Communications Channel Table's signature to the relevant ACPI header files. Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg: Add PCI Express 5.0 Header FileFelix Polyudov2020-02-121-0/+136
| | | | | | | | The header includes Physical Layer PCI Express Extended Capability definitions based on section 7.7.6 of PCI Express Base Specification 5.0. Signed-off-by: Felix Polyudov <felixp@ami.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/SmBios.h: Add two additional DWORD for smbios 3.3.0 type17Matthew Carlson2020-02-111-0/+5
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2482 Refer to DSP0134_3.3.0.pdf, there are two additional DWORD added for type 17. One is "Extended Speed", the other is "Extended Configured Memory Speed". The lack of these field may cause strange error in some operating systems. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/IndustryStandard: Fix various typosAntoine Coeur2020-02-1019-65/+65
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-24-philmd@redhat.com>
* MdePkg: Add header file for Firmware Interface Table specification.Siyuan Fu2020-01-101-0/+76
| | | | | | | | | | | | | | | | This patch add FirmwareInterfaceTable.h for the Firmware Interface Table BIOS specification. This is to remove future edk2 dependency on edk2-platforms repo. The file content comes from edk2-platforms\Silicon\Intel\IntelSiliconPkg\Include\IndustryStandard BZ link: https://tianocore.acgmultimedia.com/show_bug.cgi?id=2449 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Tcg: Add new definition in TCG PFP spec.Jiewen Yao2019-12-201-9/+173
| | | | | | | | | | | The latest TCG PFP specification (TCG PC Client Platform Firmware Profile Specification, Revision 1.05) added new data structure. For example, the SPDM device measurement. This patch adds the new content. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg PciExpress21: PCI_REG_PCIE_DEVICE_CONTROL2 struct has 17 bitsDaniel Pawel Banaszek2019-12-191-1/+1
| | | | | | | | | Device Control 2 Structure have an issue. LtrMechanism - there is 2 bits instead of 1. Signed-off-by: Daniel Pawel Banaszek <daniel.pawel.banaszek@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/Spdm: fix Nonce structure error.Jiewen Yao2019-12-191-5/+5
| | | | | | | | | | Align to SPDM 1.0.0 specification. Fix Nonce data structure error. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include: Add DCC and BCM2835 SPCR UART typesPete Batard2019-12-121-0/+10
| | | | | | | | | | | | | | | | As per the Microsoft Debug Port Table 2 (DBG2) documentation, that can be found online, we are missing 2 serial interface types for Arm DCC and Bcm2835 (the latter being used with the Raspberry Pi). These same types are present in DebugPort2Table.h so add them to SerialPortConsoleRedirectionTable.h too. Note that we followed the same idiosyncrasies as DebugPort2Table for naming these new macros. Signed-off-by: Pete Batard <pete@akeo.ie> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 Update Intel Persistent Memory stringGao, Zhichao2019-11-141-0/+4
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Memory Device (Type 17): - SMBIOSCR00179: update the string for Intel persistent memory Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 Add value HBM and Die for type 17Gao, Zhichao2019-11-141-2/+5
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Memory Device (Type 17): - SMBIOSCR00178: add new memory device type value (HBM) and new form factor value (Die) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 add support for CXL FlexbusGao, Zhichao2019-11-141-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Various: - SMBIOSCR00183: add support for CXL Flexbus Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 add PCI gen4 values for type 9Gao, Zhichao2019-11-141-2/+8
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 System Slots (Type 9): - SMBIOSCR00184: add PCI Express Gen 4 values Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/Include: Add DMTF SPDM definition.Jiewen Yao2019-11-111-0/+320
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2303 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Yun Lou <yun.lou@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Liming Gao <liming.gao@intel.com> Reviewed by: Ray Ni <ray.ni@intel.com>
* MdePkg: Add AML OpCode definition for ExternalOpPierre Gondois2019-11-041-0/+2
| | | | | | | | | | | | | The ACPI specification, version 6.3, January 2019, defines the Named Object Encoding for ExternalOp in section '20.2.5.2 Named Objects Encoding'. This patch adds the definition for ExternalOp to the list of Primary Opcode definitions. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/Include: Update to support SmBios 3.3.0Abner Chang2019-10-171-3/+73
| | | | | | | | | | | | | | | Update SmBios.h to support SMBIOS 3.3.0 spec. Bugzilla link, https://bugzilla.tianocore.org/show_bug.cgi?id=2202 Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdePkg/Include: correct Lasa in Tpm2Acpi.Jiewen Yao2019-10-111-1/+1
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=978 Correct Lasa according to TCG ACPI spec. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Implement SCSI commands for Security Protocol In/OutZurcher, Christopher J2019-09-291-17/+31
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1546 This patch implements the Security Protocol In and Security Protocol Out commands in UefiScsiLib to prepare support for the Storage Security Command Protocol. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Christopher J Zurcher <christopher.j.zurcher@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/PciExpress21.h: Fix the PCI industry standard register definesJaveed, Ashraf2019-07-311-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007 The following two PCI Capability Structure registers are updated as per the PCI Base Specification Revision 4:- (1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the PCI features like - LN system CLS (LnSystemCLS), 10b Tag completer/requester register fields (TenBitTagCompleterSupported, TenBitTagRequesterSupported), Emergency power reduction support and initialization requirement (EmergencyPowerReductionSupported, EmergencyPowerReductionInitializationRequired), and FRS support (FrsSupported ). (2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the - Emergency power reduction request enabling (EmergencyPowerReductionRequest), and also the 10b Extended Tag enabling (TenBitTagRequesterEnable). The following two are defined as per the PCI Express Base Specification Revision 2.1:- (1) Defined macro definitions for all the ranges of Maximum Payload Sizes and Maximum Read Request Sizes register fields (2) Defined macro definitions for all the ranges of Completion Timeout value. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add Generic Initiator Affinity Structure definitions to SRATKrzysztof Koch2019-06-211-1/+10
| | | | | | | | | | | | | | | | Add Generic Initiator Affinity Structure to the list of recognised System Resource Affinity Table (SRAT) structure types. Add definitions for Device Handle Types inside the Generic Initiator Affinity Structure. References: - ACPI 6.3 January 2019, Table 5-78 Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add ACPI 6.3 header fileKrzysztof Koch2019-05-152-1/+2948
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch includes the following ACPI 6.3 updates: 1. Reserve CRAT and CDIT table names in ACPI 6.3 header. - ACPI 6.3 January 2019, Table 5-30 - Mantis ID 1883 (https://mantis.uefi.org/mantis/view.php?id=1883) 2. Add new processor structure flags in PPTT. - ACPI 6.3 January 2019, Section 5.2.29 - Mantis ID 1870 (https://mantis.uefi.org/mantis/view.php?id=1870) - Mantis ID 1934 (https://mantis.uefi.org/mantis/view.php?id=1934) 3. Add SPE support to MADT. - ACPI 6.3 January 2019, Table 5-60 - Mantis ID 1934 (https://mantis.uefi.org/mantis/view.php?id=1934) 4. Add 'Hot-plug Capable' flag to APIC. - ACPI 6.3 January 2019, Table 5-44, Table 5-47 & Table 5-58 - Mantis ID 1948 (https://mantis.uefi.org/mantis/view.php?id=1948) 5. Add CNTHV timer to GTDT. - ACPI 6.3 January 2019, Section 5.2.24 - Mantis ID 1851 (https://mantis.uefi.org/mantis/view.php?id=1851) 6. Add 'Trigger Order' to Platform Communication Channel Identification Structure. - ACPI 6.3 January 2019, Section 5.2.28 - Mantis ID 1867 (https://mantis.uefi.org/mantis/view.php?id=1867) 7. Add Generic Initiator Affinity Structure to SRAT. - ACPI 6.3 January 2019, Section 5.2.16.6 - Mantis ID 1904 (https://mantis.uefi.org/mantis/view.php?id=1904) 8. Add 'HMAT Enhancements'. - ACPI 6.3 January 2019, Section 5.2.27 - Mantis ID 1914 (https://mantis.uefi.org/mantis/view.php?id=1914) - Mantis ID 1959 (https://mantis.uefi.org/mantis/view.php?id=1959) 9. Fix generic address structure definition to include all address space ID keywords. - ACPI 6.3 January 2019, Table 5-25 - Mantis ID 1965 (https://mantis.uefi.org/mantis/view.php?id=1965) 10. Make Acpi63.h the latest ACPI definition. Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg: Removed IPF related codeShenglei Zhang2019-04-282-4205/+0
| | | | | | | | | | | | | | | | A previous commit(3cb0a311cb7e747d7be5c5076d0fff76ad256d2b) didn't clean all IPF contents. So this change removes the rest contents. https://bugzilla.tianocore.org/show_bug.cgi?id=1560 v2: Withdraw the removal of Mps.h. It is written in Mps.h that MPS only was included to support Itanium-based platform power on. But we found MPS is not so relevant to Itanium architecture. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 22:07:03 +0000