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* MdePkg: Implement RISC-V Cache Management OperationsDhaval2023-12-192-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Sunil V L <sunilvl@...> Reviewed-by: Jingyu Li <jingyu.li01@...>
* MdePkg: Rename Cache Management Function To Clarify Fence Based OpDhaval2023-12-191-2/+2
| | | | | | | | | | | | | | | | | | | | There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Move RISC-V Cache Management Declarations Into BaseLibDhaval Sharma2023-12-191-0/+20
| | | | | | | | | | | | | | | The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Improve wording of manageability debug level commentRebecca Cran2023-12-111-2/+2
| | | | | | | | Improve the wording of the comment explaining the DEBUG_MANAGEABILITY debug level. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add UEFI v2.10 ISA memory type definitionManickamX Srinivasan2023-12-091-0/+15
| | | | | | | | | | | | New memory type as defined in UEFI standard v2.10 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: T V Krishnamoorthy <krishnamoorthy.t.v@intel.com> Signed-off-by: ManickamX Srinivasan <manickamx.srinivasan@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Define the DevicePath argument from LoadImage as optionalManickamX Srinivasan2023-12-081-1/+1
| | | | | | | | | | | | | Update the EFI LoadImage API in accordance with the UEFI v2.10 specification. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: T V Krishnamoorthy <krishnamoorthy.t.v@intel.com> Signed-off-by: ManickamX Srinivasan <manickamx.srinivasan@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg:Add NVME Sanitize command support to Nvme.hTina Chen2023-12-051-11/+110
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4591 1. Refer NVME spec 2.0c chapter 5.24, add Sanitize Command related definition. 2. Refer NVME spec 2.0c chapter 5.16, add Get Log Page Command related definition for Sanitize status support. Cc: Ray Ni <ray.ni@intel.com> Cc: Xiao X Chen <xiao.x.chen@intel.com> Cc: Arthur Chen <arthur.g.chen@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Tina Chen <tina.chen@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: Fix CRC16-ANSI calculationPedro Falcato2023-12-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4609 The current CalculateCrc16Ansi implementation does the following: 1) Invert the passed checksum 2) Calculate the new checksum by going through data and using the lookup table 3) Invert it back again This emulated my design for CalculateCrc32c, where 0 is passed as the initial checksum, and it inverts in the end. However, CRC16 does not invert the checksum on input and output. So this is incorrect. Fix the problem by not inverting input checksums nor output checksums. Callers should now pass CRC16ANSI_INIT as the initial value instead of "0". This is a breaking change. This problem was found out-of-list when older ext4 filesystems (that use crc16 checksums) failed to mount with "corruption". Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Tdx.h: Add TDVMCALL_STATUS_RETRYCeping Sun2023-11-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4572 TDVMCALL_STATUS_RETRY is defined in GHCI spec section 2.4.1. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.0 https://cdrdv2.intel.com/v1/dl/getContent/726790 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
* MdePkg: IndustryStandard: Add DLL CharacteristicsJoey Vagedes2023-11-061-1/+16
| | | | | | | | | | | | | | | | Add the bit masks for DLL Characteristics, used within the optional header of a PE, to the PeImage.h header file. Update the Visual Studio, Microsoft Portable Executable and Common Object File Format Specification, and the PE/COFF Specification to the latest version. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Joey Vagedes <joeyvagedes@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg ACPI65: Add 0x0B/PRM to Generic Address StructureJinlong Xu2023-10-311-0/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4567 ACPI_Spec_6_5_Aug29 Table 5.1, add 0x0B/Platform Runtime Mechanism (PRM) in Address Space ID of Generic Address Structure (GAS) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Jinlong Xu <jinlong.xu@intel.com> Message-Id: <20231020111348.2921-1-jinlong.xu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: MADT: Add TRBE interrupt to GICCSami Mujawar2023-10-301-0/+1
| | | | | | | | | | | | | | The ASWG ECR 2303 introduces a new field 'TRBE interrupt' to GICC structure in ACPI 6.5. The Trace Buffer Extension (TRBE) interrupt is a Processor Private interrupt (PPI) and is used to specify a platform-specific interrupt to signal TRBE events. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: MADT: Add Online capable flag in GICCSami Mujawar2023-10-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Bugzilla: 3706 'Code First - MADT GICC new flags' On ARM systems physical CPU hotplug is not supported. All CPUs are considered present and this is true throughout the system uptime. The ECR 2285 introduces a new 'online-capable' flag in the GICC structure flags in ACPI 6.5, to signal firmware policy (CPU is not enabled but it can be enabled and onlined). This enables OSPM to support virtual CPU hotplug (on virtual platforms for instance). This ECR also updates the MADT table revision to 6 to reflect the ACPI 6.5 changes. Therefore, update the MADT table revision to match the value as specified in ACPI 6.5. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg/Include: Definitions of IPMI Get System Interface CapabilitiesAbner Chang2023-10-261-0/+8
| | | | | | | | | | | | Define the structure for IPMI Get System Interface Capabilities command (0x57) Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Nickle Wang <nicklew@nvidia.com>
* MdePkg: Add Cxl20.h into IndustryStandardChris Li2023-10-262-1/+464
| | | | | | | | | | | | | 1) Add CXL 2.0 header file to comply with CXL 2.0 specification 2) CXL 2.0 header will embed Cxl11.h 3) Updated Cxl.h to point to 2.0 header file Signed-off-by: Chris Li <chrisli@os.amperecomputing.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Yao, Jiewen <jiewen.yao@intel.com> Cc: Nong, Foster <foster.nong@intel.com> Cc: Kinney, Michael D <michael.d.kinney@intel.com>
* MdePkg/Pldm.h: Add define for the PLDM response flagKonstantin Aladyshev2023-10-251-0/+1
| | | | | | | | | The PLDM protocol uses Request bit to help differentiate between PLDM request and response messages. Currently the Pldm.h header only have a flag for the request message. Add a flag for the response message as well. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
* MdePkg/Mctp.h: Correct typo in structure member nameKonstantin Aladyshev2023-10-251-1/+1
| | | | | | | | Correct MCTP_TRANSPORT_HEADER structure field 'SourceEndpointIdId' to 'SourceEndpointId'. Signed-off-by: Abner Chang <abner.chang@amd.com> Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
* UefiPayloadPkg: Add FIT supportBrucex.Wang2023-09-261-3/+3
| | | | | | | | | | | | | | Provide Fit format for UniversalPayload, developer can use argument "--Fit" to build UniversalPayload.fit Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
* MdePkg/BaseFdtLib: Add Fdt function.Brucex.Wang2023-09-261-0/+34
| | | | | | | | | | | | | | Add FdtGetName() and FdtNodeDepth() function. Cc: Benny Lin <benny.lin@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Benny Lin <benny.lin@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
* RedfishPkg/RedfishRestExDxe: return HTTP status code to caller.Nickle Wang2023-09-191-1/+2
| | | | | | | | | | | | | | | | Return unsupported HTTP status code to caller so caller can handle HTTP error status code. Current implementation only return EFI error to caller. Without knowing the HTTP status code, caller has trouble to handle HTTP request failure. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Reviewed-by: Igor Kulchytskyy <igork@ami.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Acked-by: Mike Maslenkin <mike.maslenkin@gmail.com>
* MdePkg/SmBios.h: Add New Intel Processor familyAvinash Bhargava2023-09-081-0/+1
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4547 Add New Intel Processor family for SMBIOS Type 4 Hex value - 16h Name - Intel(R) Processor Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Benny Lin <benny.lin@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Avinash Bhargava <avinash.bhargava@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Rng: Add GetRngGuid() to RngLibPierre Gondois2023-09-081-0/+17
| | | | | | | | | | | | | The EFI_RNG_PROTOCOL can use the RngLib. The RngLib has multiple implementations, some of them are unsafe (e.g. BaseRngLibTimerLib). To allow the RngDxe to detect when such implementation is used, add a GetRngGuid() function to the RngLib. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
* MdePkg/Rng: Add GUID to describe Arm Rndr Rng algorithmsPierre Gondois2023-09-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4441 The EFI_RNG_PROTOCOL can rely on the RngLib. The RngLib has multiple implementations, some of them are unsafe (e.g. BaseRngLibTimerLib). To allow the RngDxe to detect when such implementation is used, a GetRngGuid() function is added in a following patch. Prepare GetRngGuid() return values and add a gEfiRngAlgorithmArmRndr to describe a Rng algorithm accessed through Arm's RNDR instruction. [1] states that the implementation of this algorithm should be compliant to NIST SP900-80. The compliance is not guaranteed. [1] Arm Architecture Reference Manual Armv8, for A-profile architecture sK12.1 'Properties of the generated random number' Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
* MdePkg: Add ProcessorUpgradeSocket definitions from SMBIOS 3.7.0Eduardo Cuevas Farfan2023-08-311-3/+11
| | | | | | | | | | | | | | | | This patch adds below definitions from SMBIOS 3.7.0 into Smbios.h - ProcessorUpgradeSocketAM5 - ProcessorUpgradeSocketSP5 - ProcessorUpgradeSocketSP6 - ProcessorUpgradeSocketBGA883 - ProcessorUpgradeSocketBGA1190 - ProcessorUpgradeSocketBGA4129 - ProcessorUpgradeSocketLGA4710 - ProcessorUpgradeSocketLGA7529 Signed-off-by: Eduardo Cuevas Farfan <eduardo.cuevas.farfan@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MedPkg/Include: Add PCI_EXPRESS_EXTENDED_CAPABILITY_DVSEC_IDFoster Nong2023-08-091-0/+2
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4515 Add PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID 0x0023 in PciExpress40.h Signed-off-by: Foster Nong <foster.nong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add missing status codesNate DeSimone2023-08-072-0/+12
| | | | | | | | | | | | | | | | | REF: https://uefi.org/specs/UEFI/2.10/Apx_D_Status_Codes.html Upon review it has been found that MdePkg is missing two status code definitions: 1. EFI_IP_ADDRESS_CONFLICT - Added in UEFI Spec v2.5 2. EFI_WARN_RESET_REQUIRED - Added in UEFI Spec v2.6 These missing status codes have been added. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* MdePkg/Include/IndustryStandard: Remove VS20xx workaroundMichael D Kinney2023-07-241-5/+0
| | | | | | | | | | | | | | | | | | | | | Remove workaround for the redefinition of the type RUNTIME_FUNCTION that is generated when building with VS20xx tool chains and using windows include files. The correct location for this fix is in the EmulatorPkg in the WinInclude.h file that addresses all the name collisions between edk2 types and windows types. The commit that added the workaround is: https://github.com/tianocore/edk2/commit/ff52068d9261b9391d75b83a2a4e40e040f3b6eb Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg/Register: RISC-V: Add satp mode bits shift definitionTuan Phan2023-07-151-3/+4
| | | | | | | | | | The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: RISC-V: Support getting satp register valueTuan Phan2023-07-151-0/+5
| | | | | | | | Add an API to retrieve satp register value. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Adds AMD SMRAM save state mapAbdul Lateef Attar2023-07-031-0/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds an SMM SMRAM save-state map for AMD processors. SMRAM save state maps for the AMD processor family are now supported. Save state map structure is added based on AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2. The AMD legacy save state map for 32-bit architecture is defined. The AMD64 save state map for 64-bit architecture is defined.  Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck, because structures defined in this file are derived from Intel/SmramSaveStateMap.h. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: PiStatusCode: Add TPM subclass definition to MdePkgKun Qin2023-06-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966 This change introduces a new peripheral subclass definition from PI specification v1.8. The new subclass definition will cover system reboot events under the status reports from Trusted Platform Modules (TPMs). These definition could provide helpful datapoints to OEMs to analyze system security state and healthiness, as well as avoid definition collision with other existing peripheral subclass definitions. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: PiStatusCode: Add new Host Software class Error Code to MdePkgKun Qin2023-06-231-20/+21
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794 This change introduces a new error code definitions under Host Software class according to PI specification v1.8. The new error code definition will cover system reboot events under the conditions of inconsistent memory map from one boot to another. These error codes could provide helpful datapoints to OEMs to investigate and prevent system failures in general. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bitTuan Phan2023-06-151-1/+0
| | | | | | | | | The timer compare register is 64-bit so simplifying the delay function. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg ACPI65: Update MADT Revision pre ACPI Spec 6.5Aryeh Chen2023-06-061-1/+1
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4474 ACPI_Spec_6_5_Aug29 Table 5.19 page 128 that MADT Revision field is 6. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Aryeh Chen <aryeh.chen@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Aryeh Chen <aryeh.chen@intel.com>
* MdePkg/PeImage.h: add bits from BaseTools versionGerd Hoffmann2023-06-011-0/+31
| | | | | | | | | | The BaseTools and MdePkg versions of PeImage.h diverged over time, add some missing bits to the MdePkg header file in preparation for removing the BaseTools version. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: don't set visibility to hiddenGerd Hoffmann2023-06-011-14/+0
| | | | | | | | | Not needed any more on modern toolchains, they are better in not creating a GOT without this trick. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: BaseRiscVSbiLib: make more useful to consumersAndrei Warkentin2023-05-171-4/+38
| | | | | | | | | | | Add a few more definitions and make SbiCall and TranslateError usable (not static) by library users. Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/IndustryStandard: Add SMBIOS anchor string & length defines.Giri Mudusuru2023-05-121-2/+20
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3805 Add SMBIOS spec defined anchor strings & length defines. - '_SM_' chapter 5.2.1 SMBIOS 2.1 (32-bit) Entry Point - '_SM3_' chapter 5.2.2 SMBIOS 3.0 (64-bit) Entry Point Changes from v1 to v2: - Replace non-ASCII characters Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Signed-off-by: Giri Mudusuru <girim@apple.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Add IPMI Interface Capabilities definitionsTinh Nguyen2023-05-121-0/+46
| | | | | | | | | | | | | This adds more definitions for the IPMI Get System Interface Capabilities command. Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Add definitions for IPMI SSIFTinh Nguyen2023-05-121-0/+98
| | | | | | | | | | | | | | | BZ#: 4434 - Add IPMI SSIF definitions. Specification reference: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add NULL library of TraceHubDebugSysTLibGua Guo2023-05-111-0/+81
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library is NULL library of TraceHubDebugSysTLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add MipiSysTLib libraryGua Guo2023-05-111-0/+66
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library provides functions consuming MIPI SYS-T submodule. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove VS2008-VS2013 remnantsRebecca Cran2023-05-052-12/+4
| | | | | | | | | | | Since Visual Studio versions older than VS2015 are no longer supported, remove mention of them from MdePkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Tested-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Support FDT library.Benny Lin2023-05-051-0/+401
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4392 Add FDT support in EDK2 by submodule 3rd party libfdt (https://github.com/devicetree-org/pylibfdt/tree/main/libfdt) and refer to LibcLib implementation by Pedro. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Benny Lin <benny.lin@intel.com> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add DEBUG_MANAGEABILITY print error levelAbner Chang2023-04-211-20/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bug #4414 Add DEBUG_MANAGEABILITY print error lever to output debug message of detailed manageability related module information, such as - RedfishPkg: - HTTP header/request/response - JSON plain text - Refish resource - Redfish Host interface information - Redfish credential information - Platform configuration to Redfish mapping - etc. - ManageabilityPKg - Protocol payload of MCTP/PLDM/IPMI - Payload of transport interface transfers - IPMI BLOB transfer - etc. - RedfishClinetPkg - Redfish feature driver dispatcher - Redfish BIOS attributes - Platform configuration (HII) to Redfish property information - Redfish C structure information - etc. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
* MdePkg/Include: Add DMTF PLDM SMBIOS definitionsAbner Chang2023-04-201-0/+183
| | | | | | | | | | | | | | | | | | | | BZ #4396 This change adds definitions for DMTF PLDM SMBIOS Transfer specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0246_1.0.1.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Add DMTF PLDM Base definitionsAbner Chang2023-04-201-0/+82
| | | | | | | | | | | | | | | | | | | BZ #4396 This change adds definitions for DMTF PLDM base specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0240_1.1.0.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add new JedecJep106Lib to fetch JEDEC JEP106 manufacturerRebecca Cran2023-04-121-0/+29
| | | | | | | | | Add a new library, JedecJep106Lib which provides a service to return the JEDEC JEP106 manufacturer string given the code and continuation bytes values. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/PeCoffLib: Capture DLL characteristics fields in image contextArd Biesheuvel2023-04-072-1/+18
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4405 When loading a PE/COFF image, capture the DLL characteristics fields of the header into our image context structure so we can refer to them when mapping the image. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Base.h: Introduce various alignment-related macrosMarvin Häuser2023-04-011-1/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | ALIGNOF: Determining the alignment requirement of data types is crucial to ensure safe memory accesses when parsing untrusted data. IS_POW2: Determining whether a value is a power of two is important to verify whether untrusted values are valid alignment values. IS_ALIGNED: In combination with ALIGNOF data offsets can be verified. A more general version of the IS_ALIGNED macro previously defined by several modules. ADDRESS_IS_ALIGNED: Variant of IS_ALIGNED for pointers and addresses. Replaces module-specific definitions throughout the code base. ALIGN_VALUE_ADDEND: The addend to align up can be used to directly determine the required offset for data alignment. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Marvin Häuser <mhaeuser@posteo.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-11 08:46:54 +0000