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* MdePkg/SmBios.h: SMBIOS 3.3.0 Update Intel Persistent Memory stringGao, Zhichao2019-11-141-0/+4
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Memory Device (Type 17): - SMBIOSCR00179: update the string for Intel persistent memory Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 Add value HBM and Die for type 17Gao, Zhichao2019-11-141-2/+5
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Memory Device (Type 17): - SMBIOSCR00178: add new memory device type value (HBM) and new form factor value (Die) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 add support for CXL FlexbusGao, Zhichao2019-11-141-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Various: - SMBIOSCR00183: add support for CXL Flexbus Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 add PCI gen4 values for type 9Gao, Zhichao2019-11-141-2/+8
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 System Slots (Type 9): - SMBIOSCR00184: add PCI Express Gen 4 values Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/Include: Add DMTF SPDM definition.Jiewen Yao2019-11-111-0/+320
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2303 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Yun Lou <yun.lou@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Liming Gao <liming.gao@intel.com> Reviewed by: Ray Ni <ray.ni@intel.com>
* MdePkg-UefiSpec.h: Add UEFI 2.8 new memory attributesHuang, Qing2019-11-041-0/+20
| | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2309 Add EFI_MEMORY_SP and EFI_MEMORY_CPU_CRYPTO definition into UEFI specification header file. Signed-off-by: Qing Huang <qing.huang@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add AML OpCode definition for ExternalOpPierre Gondois2019-11-041-0/+2
| | | | | | | | | | | | | The ACPI specification, version 6.3, January 2019, defines the Named Object Encoding for ExternalOp in section '20.2.5.2 Named Objects Encoding'. This patch adds the definition for ExternalOp to the list of Primary Opcode definitions. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/Include/Protocol/Tls.h: Add the data type of EfiTlsVerifyHost ↵Wu, Jiaxin2019-11-021-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | (CVE-2019-14553) REF: https://bugzilla.tianocore.org/show_bug.cgi?id=960 CVE: CVE-2019-14553 In the patch, we add the new data type named "EfiTlsVerifyHost" and the EFI_TLS_VERIFY_HOST_FLAG for the TLS protocol consumer (HTTP) to enable the host name check so as to avoid the potential Man-In-The-Middle attack. Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Long Qin <qin.long@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20190927034441.3096-2-Jiaxin.wu@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Sivaraman Nainar <sivaramann@amiindia.co.in> Cc: Xiaoyu Lu <xiaoyux.lu@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg Base.h: Add definition for CLANG9 tool chainLiming Gao2019-10-243-6/+6
| | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1603 CLANG9 tool chain defines __clang__ macro only, doesn't define __GNUC__ macro. But, it uses some same definitions with GCC. So, update base definition for CLANG9 tool chain. Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Update to support SmBios 3.3.0Abner Chang2019-10-171-3/+73
| | | | | | | | | | | | | | | Update SmBios.h to support SMBIOS 3.3.0 spec. Bugzilla link, https://bugzilla.tianocore.org/show_bug.cgi?id=2202 Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdePkg/Include: correct Lasa in Tpm2Acpi.Jiewen Yao2019-10-111-1/+1
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=978 Correct Lasa according to TCG ACPI spec. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Implement SCSI commands for Security Protocol In/OutZurcher, Christopher J2019-09-292-18/+160
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1546 This patch implements the Security Protocol In and Security Protocol Out commands in UefiScsiLib to prepare support for the Storage Security Command Protocol. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Christopher J Zurcher <christopher.j.zurcher@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg Base.h: Define STATIC_ASSERT macro as empty for EBC archLiming Gao2019-09-251-1/+3
| | | | | | | | | | | | EBC compiler doesn't support C11 static_assert macro. So, define STATIC_ASSERT as empty to pass EBC arch build. STATIC_ASSERT macro is introduced @204ae9da230ecbf0910c21acac7aa5d5e8cbb8d0 Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: UefiLib: Add a function to check if a language is supportedTom Zhao2019-09-171-0/+17
| | | | | | | | | | | Add a function that checks if a target language is in the supported languages list. Add some calls to this function where appropriate in UefiLib.c Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Zhao <tzhao@solarflare.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Drop VERIFY_SIZE_OF in favour of STATIC_ASSERTVitaly Cheptsov via Groups.Io2019-09-171-13/+0
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2048 New STATIC_ASSERT macro supersedes VERIFY_SIZE_OF as being more functional. Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Use STATIC_ASSERT macroVitaly Cheptsov via Groups.Io2019-09-171-39/+40
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2048 Use new STATIC_ASSERT macro instead of VERIFY_SIZE_OF. Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add STATIC_ASSERT macroVitaly Cheptsov via Groups.Io2019-09-111-0/+14
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2048 Provide a macro for compile time assertions. Equivalent to C11 static_assert macro from assert.h. Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg/BluetoothLeConfig.h: Add type EfiBluetoothSmpPeerAddressListRay Ni2019-09-101-1/+3
| | | | | | | | | | | | To support auto-connection, EFI_BLUETOOTH_LE_SMP_DATA_TYPE needs to add a new data type EfiBluetoothSmpPeerAddressList which associates with a list of Bluetooth per address connected before. This new data type was added in UEFI spec 2.7b. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add MmAccess and MmControl definition.Marc W Chen2019-08-132-0/+245
| | | | | | | | | | | EFI MmAccess and MmControl PPIs are defined in the PI 1.5 specification. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2023 Signed-off-by: Marc W Chen <marc.w.chen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/Ni, Ray2019-08-0932-0/+53560
| | | | | | | | | | | | | | | | | | | | | | The patch moves all files under UefiCpuPkg/Include/Register/ to MdePkg/Include/Register using following detailed approaches: 1. Move UefiCpuPkg/Include/Register/Amd/ to MdePkg/Include/Register/Amd folder. 2. Move remaining in UefiCpuPkg/Include/Register/ to MdePkg/Include/Register/Intel folder. 3. Create wrapper header files under UefiCpuPkg/Include/Register/ to include the accordingly files in MdePkg/Include/Register/Intel. This is to avoid build break because code in other repos like edk2-platform includes the file from UefiCpuPkg. The wrapper header files will be removed after all consumers code is updated. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* MdePkg/Cpuid.h: Move Cpuid.h from UefiCpuPkg to MdePkgNi, Ray2019-08-091-0/+3997
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MdeModulePkg/DxeIpl needs to get CPUID output for CPU 5-level paging capability detection. In order to use the macros/structures defined in UefiCpuPkg/Include/Register/Cpuid.h, the patch adds Intel/Cpuid.h to MdePkg/Include/Register/ directory and updates Cpuid.h in UefiCpuPkg to include the new one in MdePkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* MdePkg/X64/ProcessorBind.h: Fix EmulatorPkg X64 XCODE5Michael D Kinney2019-08-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=2046 Make sure all libs that should be dynamically linked are dynamically linked when XCODE5 compiler is used. A previous change introduced the following pragma: #pragma GCC visibility push (hidden) When the EmulatorPkg is built using XCODE5 toolchain for X64, this pragma is included and it generates a linker error when building the Unix Host module. This change uses !defined(__APPLE__) to prevent the use of this pragma when building EmulatorPkg/Unix/Host. Cc: Liming Gao <liming.gao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg: Add PI 1.5 SmramMemoryReserve HOB fileChen, Marc W2019-07-311-0/+45
| | | | | | | | | | | This is a special GUID extension Hob to describe SMRAM memory regions Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2020 Signed-off-by: Marc W Chen <marc.w.chen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/PciExpress21.h: Fix the PCI industry standard register definesJaveed, Ashraf2019-07-311-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007 The following two PCI Capability Structure registers are updated as per the PCI Base Specification Revision 4:- (1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the PCI features like - LN system CLS (LnSystemCLS), 10b Tag completer/requester register fields (TenBitTagCompleterSupported, TenBitTagRequesterSupported), Emergency power reduction support and initialization requirement (EmergencyPowerReductionSupported, EmergencyPowerReductionInitializationRequired), and FRS support (FrsSupported ). (2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the - Emergency power reduction request enabling (EmergencyPowerReductionRequest), and also the 10b Extended Tag enabling (TenBitTagRequesterEnable). The following two are defined as per the PCI Express Base Specification Revision 2.1:- (1) Defined macro definitions for all the ranges of Maximum Payload Sizes and Maximum Read Request Sizes register fields (2) Defined macro definitions for all the ranges of Completion Timeout value. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: re-specify Base64Decode(), and add temporary stub implLaszlo Ersek2019-07-161-22/+85
| | | | | | | | | | | | | | | | | | | Rewrite Base64Decode() from scratch, due to reasons listed in the second reference below. As first step, redo the interface contract, and replace the current implementation with a stub that asserts FALSE, then fails. Cc: Liming Gao <liming.gao@intel.com> Cc: Marvin Häuser <mhaeuser@outlook.de> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1891 Ref: http://mid.mail-archive.com/c495bd0b-ea4d-7206-8a4f-a7149760d19a@redhat.com Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add new MM MP Protocol definition.Eric Dong2019-07-162-0/+349
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1937 EFI MM MP Protocol is defined in the PI 1.5 specification. The MM MP protocol provides a set of functions to allow execution of procedures on processors that have entered MM. This protocol has the following properties: 1. The caller can invoke execution of a procedure on a processor, other than the caller, that has also entered MM. Supports blocking and non-blocking modes of operation. 2. The caller can invoke a procedure on multiple processors. Supports blocking and non-blocking modes of operation. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level pagingRay Ni2019-07-121-1/+2
| | | | | | | | | | | | | | | | | 5-level paging is documented in white paper: https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf Commit f8113e25001e715390127f23e2197252cbd6d1a2 changed Cpuid.h already. This patch updates IA32_CR4 structure to include LA57 field. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> (cherry picked from commit 7c5010c7f88b790f4524c4a5311819e3af5e2752)
* Revert "MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging"Ray Ni2019-07-121-2/+1
| | | | | | | | | | | | | | This reverts commit 7c5010c7f88b790f4524c4a5311819e3af5e2752. Commit 7c5010c7f8 MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging technically breaks the EDKII development process documented in https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process and Maintainers.txt in EDKII repo root directory. The voilation is commit 7c5010c7f8 doesn't have a Reviewed-by or Acked-by from MdePkg maintainers. Signed-off-by: Ray Ni <ray.ni@intel.com>
* MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level pagingRay Ni2019-07-101-1/+2
| | | | | | | | | | | | | | | 5-level paging is documented in white paper: https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf Commit f8113e25001e715390127f23e2197252cbd6d1a2 changed Cpuid.h already. This patch updates IA32_CR4 structure to include LA57 field. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* Revert "MdePkg/Protocol/Hash: introduce GUID for SM3"Laszlo Ersek2019-07-041-5/+0
| | | | | | | | | | | | | | | | This reverts commit 49c1e683c452f68c7315454280d81449f7d94d2b. The reason is that said commit had not been reviewed by MdePkg maintainers, before it was pushed. Cc: Imran Desai <imran.desai@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1781 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* MdePkg/Protocol/Hash: introduce GUID for SM3Imran Desai2019-07-031-0/+5
| | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1781 EDK2 Support for SM3 digest algorithm is needed to enable TPM with SM3 PCR banks. This digest algorithm is part of the China Crypto algorithm suite. This integration has dependency on the openssl_1_1_1b integration into edk2. This patch adds GUID for SM3 digest algorithm. Signed-off-by: Imran Desai <imran.desai@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: jiewen.yao@intel.com
* MdePkg: Add Generic Initiator Affinity Structure definitions to SRATKrzysztof Koch2019-06-211-1/+10
| | | | | | | | | | | | | | | | Add Generic Initiator Affinity Structure to the list of recognised System Resource Affinity Table (SRAT) structure types. Add definitions for Device Handle Types inside the Generic Initiator Affinity Structure. References: - ACPI 6.3 January 2019, Table 5-78 Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add ACPI 6.3 header fileKrzysztof Koch2019-05-152-1/+2948
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch includes the following ACPI 6.3 updates: 1. Reserve CRAT and CDIT table names in ACPI 6.3 header. - ACPI 6.3 January 2019, Table 5-30 - Mantis ID 1883 (https://mantis.uefi.org/mantis/view.php?id=1883) 2. Add new processor structure flags in PPTT. - ACPI 6.3 January 2019, Section 5.2.29 - Mantis ID 1870 (https://mantis.uefi.org/mantis/view.php?id=1870) - Mantis ID 1934 (https://mantis.uefi.org/mantis/view.php?id=1934) 3. Add SPE support to MADT. - ACPI 6.3 January 2019, Table 5-60 - Mantis ID 1934 (https://mantis.uefi.org/mantis/view.php?id=1934) 4. Add 'Hot-plug Capable' flag to APIC. - ACPI 6.3 January 2019, Table 5-44, Table 5-47 & Table 5-58 - Mantis ID 1948 (https://mantis.uefi.org/mantis/view.php?id=1948) 5. Add CNTHV timer to GTDT. - ACPI 6.3 January 2019, Section 5.2.24 - Mantis ID 1851 (https://mantis.uefi.org/mantis/view.php?id=1851) 6. Add 'Trigger Order' to Platform Communication Channel Identification Structure. - ACPI 6.3 January 2019, Section 5.2.28 - Mantis ID 1867 (https://mantis.uefi.org/mantis/view.php?id=1867) 7. Add Generic Initiator Affinity Structure to SRAT. - ACPI 6.3 January 2019, Section 5.2.16.6 - Mantis ID 1904 (https://mantis.uefi.org/mantis/view.php?id=1904) 8. Add 'HMAT Enhancements'. - ACPI 6.3 January 2019, Section 5.2.27 - Mantis ID 1914 (https://mantis.uefi.org/mantis/view.php?id=1914) - Mantis ID 1959 (https://mantis.uefi.org/mantis/view.php?id=1959) 9. Fix generic address structure definition to include all address space ID keywords. - ACPI 6.3 January 2019, Table 5-25 - Mantis ID 1965 (https://mantis.uefi.org/mantis/view.php?id=1965) 10. Make Acpi63.h the latest ACPI definition. Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg: Removed IPF related codeShenglei Zhang2019-04-289-5512/+0
| | | | | | | | | | | | | | | | A previous commit(3cb0a311cb7e747d7be5c5076d0fff76ad256d2b) didn't clean all IPF contents. So this change removes the rest contents. https://bugzilla.tianocore.org/show_bug.cgi?id=1560 v2: Withdraw the removal of Mps.h. It is written in Mps.h that MPS only was included to support Itanium-based platform power on. But we found MPS is not so relevant to Itanium architecture. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/PeiServicesLib.h: Change comments of PeiServicesResetSystem2Zhichao Gao2019-04-281-4/+2
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460 Refer to Uefi spec 2.8, the ResetData is valid while ResetStatus is EFI_SUCCESS regardless of the ResetType is EfiResetPlatformSpecific or not. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/PiPeiCis.h: Change comments of EFI_PEI_RESET2_SYSTEMZhichao Gao2019-04-281-4/+2
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460 Refer to Uefi spec 2.8, the ResetData is valid while ResetStatus is EFI_SUCCESS regardless of the ResetType is EfiResetPlatformSpecific or not. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/UefiSpec.h: Change comments of EFI_RESET_SYSTEMZhichao Gao2019-04-281-5/+2
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460 Refer to Uefi spec 2.8, the ResetData is valid while ResetStatus is EFI_SUCCESS regardless of the ResetType is EfiResetPlatformSpecific or not. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/PiFirmwareFile: fix undefined behavior in FFS_FILE_SIZELaszlo Ersek2019-04-241-2/+9
| | | | | | | | | | | | | | Accessing "EFI_FFS_FILE_HEADER.Size", which is of type UINT8[3], through a (UINT32*), is undefined behavior. Fix it by accessing the array elements individually. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1710 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* MdePkg/PiFirmwareFile: fix undefined behavior in SECTION_SIZELaszlo Ersek2019-04-241-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | RH covscan justifiedly reports that accessing "EFI_COMMON_SECTION_HEADER.Size", which is of type UINT8[3], through a (UINT32*), is undefined behavior: > Error: OVERRUN (CWE-119): > edk2-89910a39dcfd/OvmfPkg/Sec/SecMain.c:178: overrun-local: Overrunning > array of 3 bytes at byte offset 3 by dereferencing pointer > "(UINT32 *)((EFI_COMMON_SECTION_HEADER *)(UINTN)Section)->Size". > # 176| Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress; > # 177| > # 178|-> Size = SECTION_SIZE (Section); > # 179| if (Size < sizeof (*Section)) { > # 180| return EFI_VOLUME_CORRUPTED; Fix this by accessing the array elements individually. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1710 Issue: scan-1007.txt Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* MdePkg/PiFirmwareFile: express IS_SECTION2 in terms of SECTION_SIZELaszlo Ersek2019-04-241-3/+3
| | | | | | | | | | | | | | | The IS_SECTION2() function-like macro duplicates the SECTION_SIZE() calculation, just to compare the computed size against 0xFFFFFF. Invoke SECTION_SIZE() instead; only preserve the comparison. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1710 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* MdePkg/UefiBaseType.h: treat EBC as a non-native machine typeArd Biesheuvel2019-04-141-3/+3
| | | | | | | | | | | Instead of classifying EBC as a supported machine type and have special handling in DXE core for loading EBC images, make it a foreign type and rely on the EDK2 PE/COFF image emulator protocol to claim the image when the DXE core finds that it cannot be supported natively. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdePkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-09515-3622/+515
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/DebugLib.h: Add new APIs for DebugLibBret Barkelew2019-04-021-1/+51
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs DebugVPrint and DebugBPrint prototype definition in the DebugLib header file. These APIs would expose a print routine with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Add Shadow Stack Support for X86.Yao, Jiewen2019-02-281-0/+2
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 This patch adds SSP - shadow stack pointer to JumpBuffer. It will be used for the platform that enabled CET/ShadowStack. We add gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask to control the global enable/disable. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/Include: Add Nasm.incYao, Jiewen2019-02-282-0/+56
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 This is to add CET related instruction in Nasm because CET instruction is not supported yet. See https://www.nasm.us/xdoc/2.14.02/html/nasmdocb.html Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/StatusCodeDataTypeId.h: Add new definition per PI1.7 SpecDandan Bi2019-02-191-1/+21
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1398 According to PI1.7 Spec, add the new definition EFI_RETURN_STATUS_EXTENDED_DATA in StatusCodeDataTypeId.h Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg: Support EFI_PEI_CORE_FV_LOCATION_PPIChasel, Chiu2019-02-151-0/+48
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524 Add EFI_PEI_CORE_FV_LOCATION_PPI definition basing on PI spec 1.7, Section 6.3.9. This PPI can support the secnario that PEI Foundation not in BFV. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg: Change function parameter typeShenglei Zhang2019-02-141-4/+4
| | | | | | | | | | | | | | | Change type of parameter Opcode from UINT16 to UINTN in EFI_S3_SAVE_STATE_WRITE and EFI_S3_SAVE_STATE_INSERT. According to PI 1.6(Errata A), the type of Opcode in EFI_S3_SAVE_STATE_WRITE and EFI_S3_SAVE_STATE_INSERT should be UINTN not UINT16. https://bugzilla.tianocore.org/show_bug.cgi?id=1517 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Fix coding style issuesBi, Dandan2019-02-021-8/+8
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1478 Fix issues that reported by Edk2 coding style check tool(ECC) that: in Comment, <@param SystemTable> does NOT consistent with parameter name MmSystemTable. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Add Base64Encode() and Base64Decode()Mike Turner2019-02-021-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce public functions Base64Encode and Base64Decode. https://bugzilla.tianocore.org/show_bug.cgi?id=1370 v2:1.Remove some white space. 2.Add unit test with test vectors in RFC 4648. https://github.com/shenglei10/edk2/tree/encode_test https://github.com/shenglei10/edk2/tree/decode_test v3:1.Align white space. 2.Update comments of Base64Encode and Base64Decode. 3.Change the use of macro RETURN_DEVICE_ERROR to RETURN_INVALID_PARAMETER in string.c. v4:Change parameters' names. v5:1.Update usage of variables. 2.Remove debug message in Base64Decode(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-02 13:30:20 +0000