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* MdePkg/BaseLib: RISC-V: Add few more helper functionsSunil V L2023-02-165-4/+129
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/UnitTestHostBaseLib: Remove HOST_APPLICATION limitationLiu, Zhiguang2022-12-141-3/+6
| | | | | | | | | | | Remove HOST_APPLICATION limitation for UnitTestHostBaseLib, so that this library can be used as BaseLib by Emulator. Also, add some missing files Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg/BaseLib: Fix out-of-bounds reads in SafeStringPedro Falcato2022-11-071-4/+21
| | | | | | | | | | | | | | | | | | There was a OOB access in *StrHexTo* functions, when passed strings like "XDEADBEEF". OpenCore folks established an ASAN-equipped project to fuzz Ext4Dxe, which was able to catch these (mostly harmless) issues. Cc: Vitaly Cheptsov <vit9696@protonmail.com> Cc: Marvin H?user <mhaeuser@posteo.de> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@Intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture.Chao Li2022-10-1411-1/+339
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053 Add LoongArch LOONGARCH64 BaseLib functions. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: Add CRC16-ANSI and CRC32c implementationsPedro Falcato2022-06-131-0/+144
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3871 Add the CRC16-ANSI and CRC32C implementations previously found at Features/Ext4Pkg/Ext4Dxe/Crc{16,32c}.c to BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove RVCT supportRebecca Cran2022-05-132-19/+0
| | | | | | | | RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg: Introduce basic Tdx functions in BaseLibMin Xu2022-04-025-0/+380
| | | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Introduce basic Tdx functions in BaseLib: - TdCall () - TdVmCall () - TdIsEnabled () Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* MdePkg: Replace Opcode with the corresponding instructions.Jason2022-03-0136-150/+91
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: Apply uncrustify changesMichael Kubacki2021-12-07166-1912/+1543
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Change OPTIONAL keyword usage styleMichael D Kinney2021-12-0718-91/+88
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3760 Update all use of ', OPTIONAL' to ' OPTIONAL,' for function params. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Reproduce builds across source format changesMichael D Kinney2021-11-081-1/+1
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3688 * Use DEBUG_LINE_NUMBER instead of __LINE__. * Use DEBUG_EXPRESSION_STRING instead of #Expression. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Add QuickSort function on BaseLibIanX Kuo2021-10-133-1/+119
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675 Add QuickSort function into BaseLib Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: IanX Kuo <ianx.kuo@intel.com>
* MdePkg/BaseLib: Add MemoryFence implementation for RiscV64Abner Chang2021-07-212-1/+24
| | | | | | | | | | | Cc: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix AsmReadSs() with GCC toolchainSatoshi Tanda2021-06-042-2/+2
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3405 AsmReadSs() in Ia32/GccInlinePriv.c and X64/GccInlinePriv.c return the DS segment selector value instead of SS. Signed-off-by: Satoshi Tanda <tanda.sat@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/BaseLib: add support for RMPADJUST instructionTom Lendacky2021-05-292-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The RMPADJUST instruction will be used by the SEV-SNP guest to modify the RMP permissions for a guest page. See AMD APM volume 3 for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-9-brijesh.singh@amd.com>
* MdePkg/BaseLib: add support for PVALIDATE instructionBrijesh Singh2021-05-292-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The PVALIDATE instruction validates or rescinds validation of a guest page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS bits OF, ZF, AF, PF and SF are set based on this return code. If the instruction completed succesfully, the rFLAGS bit CF indicates if the contents of the RMP entry were changed or not. For more information about the instruction see AMD APM volume 3. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-8-brijesh.singh@amd.com>
* MdePkg: Fix AsmReadMsr64() and AsmWriteMsr64() with GCC toolchainTakuto Naito2021-04-141-4/+3
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3325 1. AsmReadMsr64() in X64/GccInlinePriv.c AsmReadMsr64 can return uninitialized value if FilterBeforeMsrRead returns False. This causes build error with the CLANG toolchain. 2. AsmWriteMsr64() in X64/GccInlinePriv.c In the case that FilterBeforeMsrWrite changes Value and returns True, The original Value, not the changed Value, is written to the MSR. This behavior is different from the one of AsmWriteMsr64() in X64/WriteMsr64.c for the MSFT toolchain. Signed-off-by: Takuto Naito <naitaku@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Baseib: Filter/trace MSR access for IA32/X64Dandan Bi2021-04-087-43/+129
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/BaseLib: Add support for the XSETBV instructionJiaxin Wu2021-04-063-1/+71
| | | | | | | | | | | | | | | | | | | | | | | *v2: refine the coding format. https://bugzilla.tianocore.org/show_bug.cgi?id=3284 This patch is to support XSETBV instruction so as to support Extended Control Register(XCR) write. Extended Control Register(XCR) read has already been supported by below commit to support XGETBV instruction: 9b3ca509abd4e45439bbdfe2c2fa8780c950320a Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: use CpuPause() in CpuDeadLoop()Ankur Arora2021-03-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CpuPause() might allow the CPU to go into a lower power state state while we spin. On X86, CpuPause() executes a PAUSE instruction which the Intel and AMD specs describe as follows: Intel: "PAUSE: An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-wait loop greatly reduces the processor?s power consumption." AMD: "PAUSE: Improves the performance of spin loops, by providing a hint to the processor that the current code is in a spin loop. The processor may use this to optimize power consumption while in the spin loop. Architecturally, this instruction behaves like a NOP instruction." On RISC-V and ARM64, CpuPause() executes a NOP, which is no worse than the tight loop we have. Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix invalid memory access in AArch64 SetJump/LongJumpJan Bobek2020-10-132-8/+8
| | | | | | | | | | | | | | | | | Correct the memory offsets used in REG_ONE/REG_PAIR macros to synchronize them with definition of the BASE_LIBRARY_JUMP_BUFFER structure on AArch64. The REG_ONE macro declares only a single 64-bit register be read/written; however, the subsequent offset is 16 bytes larger, creating an unused memory gap in the middle of the structure and causing SetJump/LongJump functions to read/write 8 bytes of memory past the end of the jump buffer struct. Signed-off-by: Jan Bobek <jbobek@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove code wrapped by DISABLE_NEW_DEPRECATED_INTERFACESZhang, Shenglei2020-10-131-626/+0
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2777 Code wrapped by DISABLE_NEW_DEPRECATED_INTERFACES is deprecated. So remove it. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix spelling mistake for occurredMichael D Kinney2020-08-191-1/+1
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2361 Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Guomin Jiang <guomin.jiang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Add support for the VMGEXIT instructionTom Lendacky2020-08-163-0/+72
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 VMGEXIT is a new instruction used for Hypervisor/Guest communication when running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE) to occur, resulting in a #VMEXIT with an exit code value of 0x403. Since SEV-ES is only supported in X64, provide the necessary X64 support to execute the VMGEXIT instruction, which is coded as "rep vmmcall". For IA32, since "vmmcall" is not supported in NASM 32-bit mode and VMGEXIT should never be called, provide a stub implementation that is identical to CpuBreakpoint(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/BaseLib: Add support for the XGETBV instructionTom Lendacky2020-08-163-0/+67
| | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a CPUID instruction requires the current value of the XCR0 register. In order to retrieve that value, the XGETBV instruction needs to be executed. Provide the necessary support to execute the XGETBV instruction. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* BaseLib:Fix RISC-V Supervisor mode (S-Mode) trap handler reentry issue.Abner Chang2020-08-121-7/+38
| | | | | | | | | | | | | | | | | | | | | | While RISC-V hart is trapped into S-Mode, the S-Mode interrupt CSR (SIE) is disabled by RISC-V hart. However the (SIE) is enabled again by RestoreTPL, this causes the second S-Mode trap is triggered by the machine mode (M-Mode)timer interrupt redirection. The SRET instruction clear Supervisor Previous Privilege (SPP) to zero (User mode) in the second S-Mode interrupt according to the RISC-V spec. Above brings hart to the user mode (U-Mode) when execute SRET in the nested S-Mode interrupt handler because SPP is set to User Mode in the second interrupt. Afterward, system runs in U-Mode and any accesses to S-Mode CSR causes the invalid instruction exception. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/UnitTestHostBaseLib: Add missing servicesMichael D Kinney2020-07-281-0/+34
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2862 Add ReadMmx()/WriteMmx() services Add MemoryFence() service Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/BaseLib: Add BaseLib instance for host based unit testsMichael D Kinney2020-07-155-0/+3411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2800 Add a new version of BaseLib that is safe for use from host based unit test applications. Host based unit test applications may need to provide implementations of some BaseLib functions that provide simple emulation to exercise the code under test. The structure UNIT_TEST_HOST_BASE_LIB is filled in with services that provide default emulation for BaseLib APIs that would normally generate exceptions in a host based unit test application. This structure allows an individual unit test to replace the default emulation of a BaseLib service with an alternate version that is required by a specific unit test. A global variable of type UNIT_TEST_HOST_BASE_LIB is provided through the new UnitTestHostBaseLib library class. Normally cmocka would be used to mock services the code under test calls. However, the BaseLib is used by the Unit Test Framework itself, so using a mocked interface is not possible. The use of a structure to provide hooks for unit test is not expected to be a common feature. It should only be required for libraries that are used by both the Unit Test Framework and the code under test where the code under test requires a different behavior than the Unit Test Framework. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Break out IA32/X64 GCC inline privileged functionsMichael D Kinney2020-07-155-2420/+2409
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2800 Break out the IA32/X64 GCC inline functions that can not be used in a unit test host application into their own source file. This does not make any changes to the BaseLib library instance. This is in preparation for a new BaseLib instances that is safe to use with host-based unit test applications. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Fix SafeString performing assertions on runtime checksVitaly Cheptsov2020-05-221-112/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2054 Runtime checks returned via status return code should not work as assertions to permit parsing not trusted data with SafeString interfaces. Replace ASSERT() with a DEBUG_VERBOSE message. Cc: Andrew Fish <afish@apple.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Brian J. Johnson <brian.johnson@hpe.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Marvin Häuser <mhaeuser@outlook.de> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Vincent Zimmer <vincent.zimmer@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: BaseLib for RISCV64 architectureAbner Chang2020-05-0712-1/+348
| | | | | | | | | | | | | | | | Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseLib: Base64Decode(): don't declare variables in nested blocksLaszlo Ersek2019-07-171-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EDK II C Coding Standards Specification (v2.20) strongly discourages variable declarations in nested block scope: 5 Source Files 5.4 Code File Structure 5.4.1 Scoping Rules 5.4.1.1 Scope > Block (local) Scope > > [...] > > Data declarations may follow the opening brace of a compound statement, > regardless of nesting depth, and before any code generating statements > have been entered. Other than at the outermost block of a function body, > this type of declaration is strongly discouraged. Hoist such variable declarations in Base64Decode() to the outermost function scope. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Fixes: 35e242b698cdc6205e99a6d6a188bf27fecf9fb4 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1980 Reported-by: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com>
* MdePkg/BaseLib: rewrite Base64Decode()Laszlo Ersek2019-07-161-2/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite Base64Decode() from scratch, due to reasons listed in the second reference below. Implement Base64Decode() according to the specification added in the previous patch. The decoder scans the input buffer once, it has no inner loop(s), and it spills each output byte as soon as the output byte is complete. The intent is to only strengthen the checks (sanity and input) relative to the previous implementation, hence the MAX_ADDRESS checks are reinstated. Cc: Liming Gao <liming.gao@intel.com> Cc: Marvin Häuser <mhaeuser@outlook.de> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1891 Ref: http://mid.mail-archive.com/c495bd0b-ea4d-7206-8a4f-a7149760d19a@redhat.com Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Tested-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> [lersek@redhat.com: add last para to commit msg per talks w/ Marvin & Phil]
* MdePkg/BaseLib: re-specify Base64Decode(), and add temporary stub implLaszlo Ersek2019-07-161-198/+87
| | | | | | | | | | | | | | | | | | | Rewrite Base64Decode() from scratch, due to reasons listed in the second reference below. As first step, redo the interface contract, and replace the current implementation with a stub that asserts FALSE, then fails. Cc: Liming Gao <liming.gao@intel.com> Cc: Marvin Häuser <mhaeuser@outlook.de> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1891 Ref: http://mid.mail-archive.com/c495bd0b-ea4d-7206-8a4f-a7149760d19a@redhat.com Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Use PcdSpeculationBarrierTypeMichael D Kinney2019-04-302-2/+7
| | | | | | | | | | | Use PcdSpeculationBarrierType in the x86 implementation of SpeculationBarrier() to select between AsmLfence(), AsmCpuid(), and no operation. Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Brian J. Johnson <brian.johnson@hpe.com>
* MdePkg/BaseLib: Remove support of INTEL tool chainShenglei Zhang2019-04-241-187/+7
| | | | | | | | | | | | | As Intel tool chain will be removed, support of INTEL tool chain should be removed first. https://bugzilla.tianocore.org/show_bug.cgi?id=1666 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> (cherry picked from commit dd611bfeaac249cebb6c12ffdcbbf510f8ed1980)
* MdePkg/BaseLib: Remove LongJump.c and SetJump.cShenglei Zhang2019-04-153-171/+2
| | | | | | | | | | | | MdePkg BaseLib still uses the inline X86 assembly code in C code files.For now, inline SetJump/LongJump() can be removed. https://bugzilla.tianocore.org/show_bug.cgi?id=1163 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-09374-2616/+374
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Remove .S files for IA32 and X64 archShenglei Zhang2019-04-0339-2412/+0
| | | | | | | | | | | | .nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Add Shadow Stack Support for X86.Yao, Jiewen2019-02-287-7/+150
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 This patch adds SSP - shadow stack pointer to JumpBuffer. It will be used for the platform that enabled CET/ShadowStack. We add gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask to control the global enable/disable. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/BaseLib: Change a variable type in a bitwise operationShenglei Zhang2019-02-191-1/+1
| | | | | | | | | | | | | Change the type of variable Chr from CHAR8 to UINT32 in a bitwise operation, to make the two variables in the operation have the same size. https://bugzilla.tianocore.org/show_bug.cgi?id=1527 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: implement SpeculationBarrier() for ARM and AArch64Ard Biesheuvel2019-02-126-32/+160
| | | | | | | | | | | | Replace the dummy C implementation of SpeculationBarrier() with implementations consisting of the recommended DSB SY + ISB sequence, as recommended by ARM in the whitepaper "Cache Speculation Side-channels" version 2.4, dated October 2018. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* MdePkg/BaseLib: Add Base64Encode() and Base64Decode()Mike Turner2019-02-021-0/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce public functions Base64Encode and Base64Decode. https://bugzilla.tianocore.org/show_bug.cgi?id=1370 v2:1.Remove some white space. 2.Add unit test with test vectors in RFC 4648. https://github.com/shenglei10/edk2/tree/encode_test https://github.com/shenglei10/edk2/tree/decode_test v3:1.Align white space. 2.Update comments of Base64Encode and Base64Decode. 3.Change the use of macro RETURN_DEVICE_ERROR to RETURN_INVALID_PARAMETER in string.c. v4:Change parameters' names. v5:1.Update usage of variables. 2.Remove debug message in Base64Decode(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Remove definitions of two functionsShenglei Zhang2019-01-311-43/+1
| | | | | | | | | | | | | | InternalCharToUpper and InternalBaseLibAsciiToUpper are internal functions and now we will introduce public functions that have the same effects. So I remove their definitions in BaseLibInternals.h. https://bugzilla.tianocore.org/show_bug.cgi?id=1369 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/BaseLib: Introduce CharToUpper and AsciiCharToUpper publiclyMike Turner2019-01-312-14/+14
| | | | | | | | | | | | | | Introduce two public functions CharToUpper and AsciiCharToUpper. They have the same functions as InternalCharToUpper and InternalBaseLibAsciiToUpper.Considering the internal functions will be removed,so directly I change their function names to the public ones'. https://bugzilla.tianocore.org/show_bug.cgi?id=1369 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/BaseLib: Introduce new SpeculationBarrier APIHao Wu2018-12-254-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1417 X86 specific BaseLib API AsmLfence() was introduced to address the Spectre Variant 1 (CVE-2017-5753) issue. The purpose of this API is to insert barriers to stop speculative execution. However, the API is highly architecture (X86) specific, and thus should be avoided using across generic code. To address this issue, this patch will add a new BaseLib API called SpeculationBarrier(). Different architectures will have different implementations for this API. For IA32 and x64, the implementation of SpeculationBarrier() will directly call AsmLfence(). For ARM and AARCH64, this patch will add a temporary empty implementation as a placeholder. We hope experts in ARM can help to contribute the actual implementation. For EBC, similar to the ARM and AARCH64 cases, a temporary empty implementation is added. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg-BaseLib: Fix PathCleanUpDirectories() issue with "\\..\\.."Jim.Dailey@dell.com2018-10-241-7/+7
| | | | | | | | | | | Replace multiple, consecutive "\" characters prior to other processing involving "\" characters. This fixes an issue where "\\..\\..", "//..//..", and similar input paths are not cleaned properly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jim Dailey <jim_dailey@dell.com> Reviewed-by: Ruiyu Ni <Ruiyu.ni@Intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: AsciiStrToUnicodeStr(S) not handle EASCII properlyHao Wu2018-10-232-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1262 Current implementation of BaseLib APIs: AsciiStrToUnicodeStr() AsciiStrToUnicodeStrS() AsciiStrnToUnicodeStrS() do not handle EASCII properly. More specifically, if the value of ASCII character is larger than 0x7F, then the converted Unicode character will have all '1's in the higher 8 bits. An example: 0xC9 => 0xFFC9 (current implementations) and it should be: 0xC9 => 0x00C9 This commit will address this issue. Cc: Bin.Lain <bin_601@mail2000.com.tw> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg-BaseLib: Fix PathCleanUpDirectories() error involving "\..\.."Jim.Dailey@dell.com2018-10-121-1/+4
| | | | | | | | | | | | | | | | | | | MdePkg-BaseLib: Fix PathCleanUpDirectories() error involving "\..\.." The loop that removes "xxxx\..\" errs when multiple "\.." sequences are in the path. Before this change the code would modify a path like "FS0:\efi\tools\..\.." to "FS0:\efi\\.." and then to "FS0:\efi\", but the correct path is "FS0:\". You can test the effect of this change in the shell by setting the current directory to something like FS0:\efi\boot and then executing the command "ls ..\..". Before the change you will see the files in the FS0:\efi directory; after the change, you will see the files in the root directory of FS0:. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jim Dailey <jim_dailey@dell.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdePkg/BaseLib: Add new AsmLfence APIHao Wu2018-09-303-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1193 This commit will add a new BaseLib API AsmLfence(). This API will perform a serializing operation on all load-from-memory instructions that were issued prior to the call of this function. Please note that this API is only available on IA-32 and x64. The purpose of adding this API is to mitigate of the [CVE-2017-5753] Bounds Check Bypass issue when untrusted data are being processed within SMM. More details can be referred at the 'Bounds check bypass mitigation' section at the below link: https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
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