summaryrefslogtreecommitdiffstats
path: root/MdePkg/Library
Commit message (Collapse)AuthorAgeFilesLines
* MdePkg/DxeRngLib: Add missing GUID declaration in infPierre Gondois2023-10-041-0/+1
| | | | | | | | | | | | Add missing GUID declaration in DxeRngLib.inf. Fixes: bd1f0eecc1df ("MdePkg/DxeRngLib: Request raw algorithm instead of default") Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Leif Lindholm <quic_llindhol@quicinc.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/BaseLib: fix typo in Arm SetJumpLeif Lindholm2023-10-031-1/+1
| | | | | | | | | | RO -> R0 Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: ensure ARM LongJump never returns 0Leif Lindholm2023-10-022-0/+4
| | | | | | | | | | | The ARM implementation of InternalLongJump always returned the value Value - but it is not supposed to ever return 0. Add the test to prevent that, and return 1 if Value is 0 - as is already present in AArch64. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: correct register sizes in AArch64 SetJump/LongJumpLeif Lindholm2023-10-022-8/+8
| | | | | | | | | | | | | | | | Both in SetJump and in InternalLongJump, 32-bit w register views were used for the UINTN return value. In SetJump, this did not cause errors; it was only counterintuitive. But in InternalLongJump, it meant the top 32 bits of Value were stripped off. Change all of these to use the 64-bit x register views. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reanimated-by: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg/BaseLib: use normal register init in ARM SetJump implementationsLeif Lindholm2023-10-022-2/+2
| | | | | | | | | | | | | There may be architectures on which there are benefits to eor r0, r0(, r0) but ARM was never one of them. Change to more readable mov r0, #0 instead. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: add ASSERT in ARM* SetJump implementationsLeif Lindholm2023-10-022-0/+16
| | | | | | | | | | | | | The SetJump comment header states that: If JumpBuffer is NULL, then ASSERT(). However, this was not currently done. Add a call to InternalAssertJumpBuffer. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: fix comments in ARM* SetJump/LongJump implementationsLeif Lindholm2023-10-024-8/+4
| | | | | | | | | | | | | | Drop redundant comment about IPF (clearly copied across from now deleted code). Also change "Instead is resumes execution" -> "Instead it resumes execution" Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* UefiPayloadPkg: Add FIT supportBrucex.Wang2023-09-261-4/+4
| | | | | | | | | | | | | | Provide Fit format for UniversalPayload, developer can use argument "--Fit" to build UniversalPayload.fit Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
* MdePkg/BaseFdtLib: Add Fdt function.Brucex.Wang2023-09-261-0/+40
| | | | | | | | | | | | | | Add FdtGetName() and FdtNodeDepth() function. Cc: Benny Lin <benny.lin@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Benny Lin <benny.lin@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
* RISCV: Fix InternalLongJump to return correct valueAndrei Warkentin2023-09-211-5/+2
| | | | | | | | | | | | | | | InternalLongJump was not returning the 2nd parameter passed to LongJmp (Value) as the return value from SetJmp. Seen with code compiled with -Os, where an LongJmp (Buffer, -1) somehow translated to SetJmp returning 0... Cc: Yong Li <yong.li@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg/Library/TdxLib: Remove unnecessary comparisonMichael Kubacki2023-09-081-1/+1
| | | | | | | | | | | | | | | | | Removes the comparison since unsigned values are always greater than or equal to 0. See the following CodeQL query for more info: /cpp/cpp-unsigned-comparison-zero/ Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Rebecca Cran <rebecca@bsdio.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* MdePkg/Rng: Add GetRngGuid() to RngLibPierre Gondois2023-09-086-0/+151
| | | | | | | | | | | | | The EFI_RNG_PROTOCOL can use the RngLib. The RngLib has multiple implementations, some of them are unsafe (e.g. BaseRngLibTimerLib). To allow the RngDxe to detect when such implementation is used, add a GetRngGuid() function to the RngLib. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
* MdePkg/DxeRngLib: Request raw algorithm instead of defaultPierre Gondois2023-09-081-1/+7
| | | | | | | | | | | | | | | | The DxeRngLib tries to generate a random number using the 3 NIST SP 800-90 compliant DRBG algorithms, i.e. 256-bits CTR, HASH and HMAC. If none of the call is successful, the fallback option is the default RNG algorithm of the EFI_RNG_PROTOCOL. This default algorithm might be an unsafe implementation. Try requesting the Raw algorithm before requesting the default one. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
* MdePkg: Add deprecated warning to BaseRngLibTimerPierre Gondois2023-09-082-0/+23
| | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4504 To keep the MdePkg self-contained and avoid dependencies on GUIDs defined in other packages, the BaseRngLibTimer was moved to the MdePkg. Add a constructor to warn and request to use the MdeModulePkg implementation. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
* MdePkg/Library/BaseRngLib: Fix include guardMichael Kubacki2023-09-081-0/+1
| | | | | | | | | | | | | The include guard is incomplete and does not define the macro. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Rebecca Cran <rebecca@bsdio.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add new status codes to PrintLibNate DeSimone2023-08-071-3/+7
| | | | | | | | | | | | | | | | PrintLib does not correctly decode the follow status codes: 1. EFI_IP_ADDRESS_CONFLICT 2. EFI_HTTP_ERROR 3. EFI_WARN_FILE_SYSTEM 4. EFI_WARN_RESET_REQUIRED These missing status codes have been added. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* MdePkg/BaseLib: RISC-V: Support getting satp register valueTuan Phan2023-07-151-0/+8
| | | | | | | | Add an API to retrieve satp register value. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Code optimization to SMM InternalAllocateAlignedPagesduntan2023-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is code optimization to InternalAllocateAlignedPages of SmmMemoryAllocationLib which can reduce free memory fragments. Also it can reduce one pre-allocation page. Let's take a simple example: The expected pages size is 8KB, Alignment value is 8KB. In original InternalAllocateAlignedPages(), the first step is to allocate 4 pages and then find the first 8KB-aligned address in allocated 4 pages. If the upper limit address of allocated 4 pages is already 8KB aligned, then the allocated 4 pages contains two 8KB-aligned 8KB ranges. The lower 2 pages will be selected and removed from free pages. Then the higher 2 pages will be free. Since the whole memory allocation is from high address to low address, then the higher 2 pages cann't be merged with other free pages, causing the free memory fragments. However, when only allocate 3(2+2-1) pages, we can avoid the free memory fragments in specific case. Also 3 pages must contain a 8KB-aligned 8KB range, which meets the requirement. If the upper limit address of allocated 3 pages is 8KB-aligned, then the higher 2 pages range of allocated 3 pages is 8KB-aligned and will be selected and removed from free pages. The remaining lower one page of allocated 3 pages will be free and merged with left lower free memory. This can reduce free memory fragments in smm. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64Yong Li2023-06-062-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 and below the commit for ARM and AArch64 implementation https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Evan Chai <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Signed-off-by: Yong Li <yong.li@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: add SBI-based SerialPortLib for RISC-VAndrei Warkentin2023-05-177-0/+765
| | | | | | | | | | | | | | | | | | | | | | These are implementations of SerialPortLib using SBI console services. - BaseSerialPortLibRiscVSbiLib is appropriate for SEC/PEI (XIP) environments - BaseSerialPortLibRiscVSbiLibRam is appropriate for PrePI/DXE environments Tested with: - Qemu RiscVVirt (non-DBCN case, backed by UART) - TinyEMU + RiscVVirt (non-DBCN case, HTIF) - TinyEMU + RiscVVirt (DBCN case, HTIF) Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: BaseRiscVSbiLib: make more useful to consumersAndrei Warkentin2023-05-171-2/+1
| | | | | | | | | | | Add a few more definitions and make SbiCall and TranslateError usable (not static) by library users. Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add NULL library of TraceHubDebugSysTLibGua Guo2023-05-112-0/+105
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library is NULL library of TraceHubDebugSysTLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add MipiSysTLib libraryGua Guo2023-05-117-0/+1423
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library provides functions consuming MIPI SYS-T submodule. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add mipisyst submoduleGua Guo2023-05-111-0/+0
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library provides functions consuming MIPI SYS-T submodule. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kubacki <mikuback@linux.microsoft.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseSynchronizationLib: Fix LoongArch64 synchronization functionsDongyan Qian2023-05-052-19/+13
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4432 There is a return value bug: The sc.w/sc.d instruction will destroy the reg_t0, use reg_t1 to avoid context reg_t0 being corrupted. Adjust Check that ptr align is UINT16. Optimize function SyncIncrement and SyncDecrement. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Reviewed-by: Chao Li <lichao@loongson.cn>
* MdePkg/BasePeCoffLib: Deal with broken debug directoriesArd Biesheuvel2023-05-051-0/+15
| | | | | | | | | | | | | | | | | | | | | | | Older versions of GenFw put the wrong value in the debug directory size field in the PE/COFF header: instead of putting the combined size of all the entries, it puts the size of the only entry it creates, but adds the size of the NB10 payload that the entry points to. This confuses the loader now that we started using additional debug directory entries to describe DLL characteristics. GenFw was fixed in commit 60e85a39fe49071, but the binaries that were generated with it still need to be supported. So let's detect this condition, and check whether the size of the debug directory is consistent with the NB10 payload: if we should expect additional directory entries where we observe the NB10 payload, the size field is clearly wrong, and we can break from the loop. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4425 Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: Support FDT library.Benny Lin2023-05-0511-0/+812
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4392 Add FDT support in EDK2 by submodule 3rd party libfdt (https://github.com/devicetree-org/pylibfdt/tree/main/libfdt) and refer to LibcLib implementation by Pedro. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Benny Lin <benny.lin@intel.com> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* Tianocore: Support FDT library.Benny Lin2023-05-051-0/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4392 Add FDT support in EDK2 by submodule 3rd party libfdt (https://github.com/devicetree-org/pylibfdt/tree/main/libfdt) Add submodule libfdt and update ReadMe for the license. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Benny Lin <benny.lin@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add new JedecJep106Lib to fetch JEDEC JEP106 manufacturerRebecca Cran2023-04-122-0/+1864
| | | | | | | | | Add a new library, JedecJep106Lib which provides a service to return the JEDEC JEP106 manufacturer string given the code and continuation bytes values. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Library/BaseLib: HOST_APPLICATION IA32/X64 onlyMichael D Kinney2023-04-101-1/+1
| | | | | | | | | | | | | | Update BaseLib host-based unit test INF file to only list VALID_ARCHITECTURES of IA32 and X64 to align with all other host-based unit test INF files. The UnitTestFrameworkPkg only provides build support of host-based unit tests to OS applications for IA32 and X64. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* MdePkg/PeCoffLib: Capture DLL characteristics fields in image contextArd Biesheuvel2023-04-071-11/+35
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4405 When loading a PE/COFF image, capture the DLL characteristics fields of the header into our image context structure so we can refer to them when mapping the image. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix conditionally uninitialized variablesMichael Kubacki2023-04-031-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes CodeQL alerts for CWE-457: https://cwe.mitre.org/data/definitions/457.html Note that this change affects the actual return value from the following functions. The functions documented that if an integer overflow occurred, MAX_UINTN would be returned. They were implemented to actually return an undefined value from the stack. This change makes the function follow its description. However, this is technically different than what callers may have previously expected. MdePkg/Library/BaseLib/String.c: - StrDecimalToUintn() - StrDecimalToUint64() - StrHexToUintn() - StrHexToUint64() - AsciiStrDecimalToUintn() - AsciiStrDecimalToUint64() - AsciiStrHexToUintn() - AsciiStrHexToUint64() Cc: Erich McMillan <emcmillan@microsoft.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Co-authored-by: Erich McMillan <emcmillan@microsoft.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseRngLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-2/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseSynchronizationLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+5
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseMemoryLibOptDxe AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-305-0/+9
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-308-0/+10
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make LongJump() BTI compatibleArd Biesheuvel2023-03-301-2/+1
| | | | | | | | | | | | | | | | | | Currently, the AArch64 implementation of LongJump() avoids using the RET instruction to perform the jump, even though the target address is held in the link register X30, as the nature of a long jump implies that the ordinary return address prediction machinery will not be able to make a correct prediction. However, LongJump() is rarely used, and the return stack will be out of sync in any case, so this optimization has little value in practice, and given that indirect calls other than function returns require a BTI landing pad at the call site, this optimization is not compatible with BTI. So let's just use RET instead. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseIoLibIntrinsic AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+8
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseCpuLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-0/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg: Update code to be more C11 compliant by using __func__Rebecca Cran2023-03-175-18/+18
| | | | | | | | | | | | | | | | | | __FUNCTION__ is a pre-standard extension that gcc and Visual C++ among others support, while __func__ was standardized in C99. Since it's more standard, replace __FUNCTION__ with __func__ throughout MdePkg. Visual Studio versions before VS 2015 don't support __func__ and so will fail to compile. A workaround is to define __func__ as __FUNCTION__ : #define __func__ __FUNCTION__ Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix InvalidateInstructionCacheRangeTuan Phan2023-03-161-1/+6
| | | | | | | | When the range instruction cache invalidating not supported, the whole instruction cache should be invalidated instead. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Move API and implementation from UefiCpuLib to CpuLibYu Pu2023-03-104-0/+206
| | | | | | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib. Change-Id: Ic26f4c2614ed6bd9840f817d50e47ac1de4bd013 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: BaseCpuLib: Fix RISCV CpuSleep symbol name.Andrei Warkentin2023-03-081-2/+2
| | | | | | | | | | | CpuSleep, not _CpuSleep. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: BaseLib: don't log in RISCV InternalSwitchStackAndrei Warkentin2023-03-081-8/+0
| | | | | | | | | | | | | | InternalSwitchStack may be called with a TPL high enough for a DebugLib implementation to assert. Other arch implementations don't log either. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: BasePeCoffLib: Allow AArch64 and x64 images in ImageFormatSupportedAndrei Warkentin2023-03-081-1/+9
| | | | | | | | | | | | | ARM64 and X64 may allow such foreign images to be used when driver implementing EDKII_PECOFF_IMAGE_EMULATOR_PROTOCOL is present. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: Add BaseRiscVSbiLib Library for RISC-VSunil V L2023-02-163-0/+299
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This library is required to make SBI ecalls from the S-mode EDK2. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: RISC-V: Add few more helper functionsSunil V L2023-02-165-4/+129
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Added Call for AfterReadyToBoot EventRobert Phelps2023-02-152-0/+15
| | | | | | | | | | | In the function EfiSignalEventReadyToBoot, Code was added to also create, signal, and close the AfterReadyToBoot event. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Robert Phelps <robert@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/UnitTestHostBaseLib: Remove HOST_APPLICATION limitationLiu, Zhiguang2022-12-141-3/+6
| | | | | | | | | | | Remove HOST_APPLICATION limitation for UnitTestHostBaseLib, so that this library can be used as BaseLib by Emulator. Also, add some missing files Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg/BaseCpuLib: Remove assembly for CpuFlushTlbLiu, Zhiguang2022-12-145-97/+5
| | | | | | | | | | | | For different compilers, both IA32 and X64 can use Ia32/CpuFlushTlbGcc.c, which is C code (no inline assembly code). To simplify, remove other assemly file for CpuFlushTlb, and rename Ia32/CpuFlushTlbGcc.c to X86CpuFlushTlb.c. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 14:48:20 +0000