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* Refactor SetMemWrapper to reduce binary sizeAshraf Ali2024-09-1121-246/+392
| | | | | | | | | | | | Moved SetMemN API to a separate file to eliminate unnecessary inclusion of InternalMemSetMem64 and InternalMemSetMem32 APIs in driver binary. When the compiler linking the Object files it may not remove all the unused from NASM OBJs. This change is to reorganize the C files to minimize the impact of the NASM behavior resulting is code size reduction. Signed-off-by: Ashraf Ali <ashraf.ali.s@intel.com>
* MdePkg/BaseLib: Add NULL version Tdx functions for other architecturesCeping Sun2024-09-091-0/+5
| | | | | | | | | | | | | | Currently, the NULL version Tdx functions are only built for Ia32. In BaseLib, the others architectures also need such NULL version Tdx functions. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
* MdePkg: Fix a buffer overread.John Baldwin2024-09-031-1/+2
| | | | | | | | | | | | | | DevPathToTextUsbWWID allocates a separate copy of the SerialNumber string to append a null terminator if the original string is not null terminated. However, by using AllocateCopyPool, it tries to copy 'Length + 1' words from the existing string containing 'Length' characters into the target string. Split the copy out to only copy 'Length' characters instead. This was reported by GCC's -Wstringop-overread when compiling a copy of this routine included in a library on FreeBSD. Signed-off-by: John Baldwin <jhb@FreeBSD.org>
* MdePkg: Remove duplicate source from BaseMemoryLib INF filesAshraf Ali2024-08-315-116/+13
| | | | Signed-off-by: Ashraf Ali <ashraf.ali.s@intel.com>
* MdePkg: Rename the LoongArch CSR 0x20 registerChao Li2024-08-301-12/+12
| | | | | | | | | | | | | Added a new name for CSR 0x20 because LoongArch SPEC has adjustd the CSR 0x20 register name. Ref: LoongArch Reference Manual Vol 1, Seciton 7.1. https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* MdePkg:BaseArmTrngLibNull: Assert causing FVP stallingPrachotan Reddy Bathi2024-08-291-1/+1
| | | | | | | | FVP Base Revc doesn't support Trng. ASSERT (FALSE) is causing the boot to stall. Replacing ASSERT with ERROR log. Signed-off-by: Prachotan Reddy Bathi <Prachotan.Bathi@arm.com>
* MdePkg: Fix build error after enable FDT support.Linus Liu2024-08-281-2/+5
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Disable some compiling warnings caused by submodule code. Those can be removed later once issues fixed by submodule owner. Signed-off-by: Linus Liu <linus.liu@intel.com>
* MdePkg/BaseFdtLib: Add FdtNodeOffsetByCompatible()Nhi Pham2024-08-281-0/+20
| | | | | | | This adds FdtNodeOffsetByCompatible() to support finding the offset of the first node with a given 'compatible' value after an offset. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
* MdePkg/BaseLib: Add CRC16 CCITT False Implementation.kuqin122024-08-061-0/+69
| | | | | | | | | | | | | | This change is added to incorporate basic implementation for CRC16-CCITT-FALSE algorithm. This function is useful for providing CRC16 value used in other data structures that requires CRC16 value that complies with JEDEC SPD requirements, i.e. BDAT table. The lookup table is inherited from `https://crccalc.com/` and the result values are also compared against this site. Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
* MdePkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-014-31/+31
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in MdePkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg/BaseRngLib: Prefer ArmReadIdAA64Isar0Reg() over ArmReadIdIsar0()Pierre Gondois2024-08-015-82/+2
| | | | | | | | | | | | | | | A ArmReadIdAA64Isar0Reg() function was recently added to BaseLib. Use it instead of its ArmReadIdIsar0() equivalent, which was private to the BaseRngLib library. This also allows to avoid the confusion between the following registers: - ID_ISAR0_EL1: allows to probe for Divide instructions, Debug instructions, ... - ID_AA64ISAR0_EL1: AARCH64 specific register allowing to probe for AESE, RNDR, ... instructions Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()Pierre Gondois2024-08-013-0/+62
| | | | | | | | | | | | | | To enable AARCH64 native instruction support for Openssl, some interfaces must be implemented. OPENSSL_cpuid_setup() allows to probe the supported features of the platform. Add ArmReadIdAA64Isar0Reg() to read the AA64Isar0, containing Arm64 instruction capabilities. A similar ArmReadIdAA64Isar0() function is available in the ArmPkg, but the CryptoPkg where OPENSSL_cpuid_setup will reside cannot rely on the ArmPkg. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg()Pierre Gondois2024-08-013-1/+63
| | | | | | | | | | | | | To enable AARCH64 native instruction support for Openssl, some interfaces must be implemented. OPENSSL_rdtsc() requests an access to a counter to get some non-trusted entropy. Add ArmReadCntPctReg() to read system count. A similar ArmReadCntPct() function is available in the ArmPkg, but the CryptoPkg where OPENSSL_rdtsc will reside cannot rely on the ArmPkg. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
* MdePkg/BaseLib: Optimize LOONGARCH64 csr usageDongyan Qian2024-07-172-9/+7
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4812 When the Select is out of support, use method break exception instead of method return -1, avoid unknown errors caused by untimely detection. Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* MdePkg/UefiDebugLibDebugPortProtocol: ExitBootServicesCallback() staticMichael Kubacki2024-07-161-2/+3
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3083 Since this is a library, make the function ExitBootServicesCallback() STATIC to prevent the likelihood that it collides with other symbols. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg/Library: Add RISCV64 support to BaseRngLibDhaval2024-07-153-0/+304
| | | | | | | | | | | | | | | The ratified RISC-V crypto scalar extensions provide entropy bits via the seed CSR, as exposed by the Zkr extension. The Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR. Guarded by a RISCV64 Feature PCD, 64-bit random numbers can be accumulated from the `seed` CSR. This driver is based on the driver in the Linux kernel. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Co-authored-by: Tim Wawrzynczak <tim@rivosinc.com>
* MdePkg/StandaloneMmServicesTableLib: Support MM_CORE_STANDALONEJiaxin Wu2024-07-051-1/+1
| | | | | | Support the module type for MM_CORE_STANDALONE Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* MdePkg/BaseLib: Fix an instruction write width error in LoongArch64Dongyan Qian2024-06-261-1/+1
| | | | | | | | | | | | Cpucfg fetch is a 32-bit register, and AsmCpucfg's function declaration is a 32-bit address storage operation in BaseLib.h, So, fix it by replacing stptr.d with stptr.w instrcution. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4797 Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Chao Li <lichao@loongson.cn>
* MdePkg/X86UnitTestHost: set rdrand cpuid bitGerd Hoffmann2024-06-141-1/+10
| | | | | | | Set the rdrand feature bit when faking cpuid for host test cases. Needed to make the CryptoPkg test cases work. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg/BaseRngLib: Add a smoketest for RDRAND and check CPUIDPedro Falcato2024-06-131-8/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RDRAND has notoriously been broken many times over its lifespan. Add a smoketest to RDRAND, in order to better sniff out potential security concerns. Also add a proper CPUID test in order to support older CPUs which may not have it; it was previously being tested but then promptly ignored. Testing algorithm inspired by linux's arch/x86/kernel/cpu/rdrand.c :x86_init_rdrand() per commit 049f9ae9.. Many thanks to Jason Donenfeld for relicensing his linux RDRAND detection code to MIT and the public domain. >On Tue, Nov 22, 2022 at 2:21 PM Jason A. Donenfeld <Jason@zx2c4.com> wrote: <..> > I (re)wrote that function in Linux. I hereby relicense it as MIT, and > also place it into public domain. Do with it what you will now. > > Jason BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4163 Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jason A. Donenfeld <Jason@zx2c4.com>
* MdePkg/BaseLib: Let CpuDeadLoop() be breakable in debuggerRay Ni2024-06-121-2/+4
| | | | | | | | | | | | | | | | | | | Starting from certain version of Visual Studio C compiler (I don’t have the exact version. I am using VS2019), CpuDeadLoop is optimized quite well by compiler. The compiler does not generate instructions that jump out of the loop when the "Index" is non-zero. It becomes harder/impossible for developers to break out of the dead-loop in debugger. The new version of CpuDeadLoop() compares a volatile global to a volatile local. This forces 2 reads and a comparison on every loop iteration. The local variable can be set to 1 to exit the loop without modifying the global variable. Using VS2019 with max opt enabled, The dead-loop can be exit by setting Index to 1 in a debugger. Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseRngLib AARCH64: Remove overzealous ASSERT()Ard Biesheuvel2024-05-241-1/+0
| | | | | | | | | | | | | | | | | | | | | | BaseRngLib on AARCH64 will discover whether or not RNDR instructions are supported, by inspecting the ISAR0 identification register, and setting a global boolean accordingly. This boolean is used in subsequent execution to decide whether or not to issue the instruction. The same discovery code also ASSERT()s that RNDR instructions are implemented, which is unnecessary, and breaks execution on systems that incorporate the library but don't implement the instruction (or fail to expose it to the exception level that the firmware executes at). So drop the ASSERT(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix AARCH64 compilation errorShun Cheng Liu2024-05-152-0/+2
| | | | | | | | | | | | | Declare InternalAssertJumpBuffer as EXTERN Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Shun Cheng Liu <adam.liu@tw.synaptics.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com>
* MdePkg/BaseLib: Add a new VMGEXIT instruction invocation for SVSMTom Lendacky2024-04-173-0/+135
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The SVSM specification relies on a specific register calling convention to hold the parameters that are associated with the SVSM request. The SVSM is invoked by requesting the hypervisor to run the VMPL0 VMSA of the guest using the GHCB MSR Protocol or a GHCB NAE event. Create a new version of the VMGEXIT instruction that will adhere to this calling convention and load the SVSM function arguments into the proper register before invoking the VMGEXIT instruction. On return, perform the atomic exchange on the SVSM call pending value as specified in the SVSM specification. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
* MdePkg: Update the comments of GetInformation functionQingyu2024-04-151-1/+4
| | | | | | | | | | | | | Refer to Uefi spec 2.10 section 11.11.2, add a new retval EFI_NOT_FOUND to EFI_ADAPTER_INFORMATION_PROTOCOL.GetInformation(). Reference: [mantis #1866] - GetInfo() of Adapter Information Protocol should have a provision for IHV to return no data. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Qingyu <qingyu.shang@intel.com> Signed-off-by: Gahan Saraiya <gahan.saraiya@intel.com>
* MdePkg/BaseLib: Update TDVMCALL_EXPOSE_REGS_MASKCeping Sun2024-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4696 Refer to the [GHCI] spec, TDVF should clear the BIT5 for RBP in the mask. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.5 https://cdrdv2.intel.com/v1/dl/getContent/726792 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Isaku Yamahata <isaku.yamahata@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add EFI_UNSUPPORTED return for some Runtime Service functionsSuqiang Ren2024-02-091-3/+40
| | | | | | | | | | | | | | | | | According to UEFI Spec 2.10 page 206, if any EFI_RUNTIME_SERVICES* calls are not supported for use by the OS at runtime, an EFI_RT_PROPERTIES_TABLE configuration table should be published describing which runtime services are supported at runtime. So need to add EFI_UNSUPPORTED return for some Runtime Service functions. REF: UEFI spec 2.10 section 8 Services ? Runtime Services Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add a new library named PeiServicesTablePointerLibKs0Chao Li2024-02-063-0/+144
| | | | | | | | | | | | | | | | | | Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides setting and getting the PEI service table pointer through the CSR KS0 register. The idea of this library is derived from ArmPkg/Library/PeiServicesTablePointerLib/ BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add IOCSR operation for LoongArchChao Li2024-02-062-0/+121
| | | | | | | | | | | | | | | Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8, IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR registers of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add CSR operation for LoongArchChao Li2024-02-063-0/+505
| | | | | | | | | | | | | | | Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them to operate the CSR register of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add read stable counter operation for LoongArchChao Li2024-02-062-0/+25
| | | | | | | | | | | | | Add LoongArch gets stable counter ASM function. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch Cpucfg functionChao Li2024-02-062-0/+27
| | | | | | | | | | | | | | | | Add LoongArch AsmCpucfg function and Cpucfg definitions. Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of EccCheck. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 local interrupt function set into BaseLibChao Li2024-02-062-10/+34
| | | | | | | | | | | | | | | Adding LoongArch local interrupt function set, which is used to control the opening or closing of the local interrupt when the global interrupt is enabled. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 exception function set into BaseLibChao Li2024-02-062-0/+42
| | | | | | | | | | | | | | Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 FPU function set into BaseCpuLibChao Li2024-02-064-2/+90
| | | | | | | | | | | | | | Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and DisableFloatingPointUnits functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Library/BaseCpuLibNull: Add missing X86 specific servicesMichael D Kinney2024-01-273-15/+69
| | | | | | | | | | | | | | | | * Add InitializeFloatingPointUnits() to x86 specific file * Add GetCpuFamilyModel() to x86 specific file * Add GetCpuSteppingId() to x86 specific file * Move StandardSignatureIsAuthenticAMD() to x86 specific file. * Add CpuLib library class include to all C files. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Qing Huang <qing.huang@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/BaseFdtLib: Rename standard functionsJeff Brasen2024-01-242-25/+7
| | | | | | | | | | | Rename the standard functions in the LibFdtSupport to remove conflicts with other libraries that define them. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Library/BaseCpuLibNull: Add StandardSignatureIsAuthenticAMD()devel@edk2.groups.io2024-01-231-0/+15
| | | | | | | | | | | | CpuLib.h exposes StandardSignatureIsAuthenticAMD() API and we require stub function in its BaseCpuLibNull library instance to avoid potential link issue. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Qing Huang <qing.huang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Library/BaseIoLibIntrinsic: Fix TD MMIO read type castZhiquan Li2024-01-201-3/+3
| | | | | | | | | | | Currently the types of casting mismatch with TD MMIO read 1, 2 and 4 bytes, that might introduce potential issues. So fix the types as conventional MmioRead[8|16|32] does. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiquan Li <zhiquan1.li@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: Fix boot DxeCore hang on riscv platform王洋2024-01-113-7/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | For scene of HandOffToDxeCore()->SwitchStack(DxeCoreEntryPoint)-> InternalSwitchStack()->LongJump(),Variable HobList.Raw will be passed (from *Context1 to register a0) to DxeMain() in parameter *HobStart. However, meanwhile the function LongJump() overrides register a0 with a1 (-1) due to commit (ea628f28e5 "RISCV: Fix InternalLongJump to return correct value"), then cause hang. Replacing calling LongJump() with new InternalSwitchStackAsm() to pass addres data in register s0 to register a0 could fix this issue (just like the solution in MdePkg/Library/BaseLib/AArch64/SwitchStack.S) Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Cc: Bamvor Jian ZHANG <zhangjian@bosc.ac.cn> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ran Wang <wangran@bosc.ac.cn> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg/BaseLib: RISC-V: Add function to update stimecmp registerSunil V L2024-01-111-0/+7
| | | | | | | | | | | | | | stimecmp is a CSR supported only when Sstc extension is supported by the platform. This register can be used to set the timer interrupt directly in S-mode instead of going via SBI call. Add a function to update this register. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: Utilize Cache Management Operations Implementation For RISC-VDhaval Sharma2023-12-192-28/+153
| | | | | | | | | | | | | | | | Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Implement RISC-V Cache Management OperationsDhaval2023-12-192-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Sunil V L <sunilvl@...> Reviewed-by: Jingyu Li <jingyu.li01@...>
* MdePkg: Rename Cache Management Function To Clarify Fence Based OpDhaval2023-12-192-6/+6
| | | | | | | | | | | | | | | | | | | | There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Move RISC-V Cache Management Declarations Into BaseLibDhaval Sharma2023-12-191-20/+0
| | | | | | | | | | | | | | | The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg:simplify Fifo API in BaseIoLibIntrinsicDun Tan2023-12-114-259/+222
| | | | | | | | | | | | | | | | | | Simplify IoRead/WriteFifo implement by repeatedly calling IoRead/Write in the C code. This can avoid calling assembly code to use string I/O instructions. With this change Ia32/IoFifo.nasm and X64/IoFifo.nasm can be removed. Then the source files for IA32 and X64 are the same. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Change IoLibFifo.c to IoLibFifoCc.cDun Tan2023-12-112-2/+2
| | | | | | | | | | | | | | | | Change IoLibFifo.c to IoLibFifoCc.c since the file is for Tdx and SEV in BaseIoLibIntrinsicSev. It's also to distinguish with a new incoming IoLibFifo.c for BaseIoLibIntrinsic. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* BaseStackCheckLib: Fix STACK FAULT messageJake Garver2023-12-061-1/+2
| | | | | | | | __builtin_return_address returns a pointer, not a string. Fix the STACK FAULT message in BaseStackCheckLib appropriately. Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix CRC16-ANSI calculationPedro Falcato2023-12-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4609 The current CalculateCrc16Ansi implementation does the following: 1) Invert the passed checksum 2) Calculate the new checksum by going through data and using the lookup table 3) Invert it back again This emulated my design for CalculateCrc32c, where 0 is passed as the initial checksum, and it inverts in the end. However, CRC16 does not invert the checksum on input and output. So this is incorrect. Fix the problem by not inverting input checksums nor output checksums. Callers should now pass CRC16ANSI_INIT as the initial value instead of "0". This is a breaking change. This problem was found out-of-list when older ext4 filesystems (that use crc16 checksums) failed to mount with "corruption". Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: Update TdVmcall to always output the value in R11Ceping Sun2023-11-091-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4572 According to section 3.2 of the [GHCI] spec, if the return status of MapGPA is "TDG.VP.VMCALL_RETRY", TD must retry this operation for the pages in the region starting at the GPA specified in R11. Currently, TDVF has not handled the retry results and always clears the R11 on unsuccessful return status. For this, the TdVmcall needs to output the value of R11 on unsuccessful return status to handle the retry results of MapGPA. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.0 https://cdrdv2.intel.com/v1/dl/getContent/726790 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:32:51 +0000