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* MdePkg: Add ProcessorUpgradeSocket definitions from SMBIOS 3.7.0Eduardo Cuevas Farfan2023-08-311-3/+11
| | | | | | | | | | | | | | | | This patch adds below definitions from SMBIOS 3.7.0 into Smbios.h - ProcessorUpgradeSocketAM5 - ProcessorUpgradeSocketSP5 - ProcessorUpgradeSocketSP6 - ProcessorUpgradeSocketBGA883 - ProcessorUpgradeSocketBGA1190 - ProcessorUpgradeSocketBGA4129 - ProcessorUpgradeSocketLGA4710 - ProcessorUpgradeSocketLGA7529 Signed-off-by: Eduardo Cuevas Farfan <eduardo.cuevas.farfan@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MedPkg/Include: Add PCI_EXPRESS_EXTENDED_CAPABILITY_DVSEC_IDFoster Nong2023-08-091-0/+2
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4515 Add PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID 0x0023 in PciExpress40.h Signed-off-by: Foster Nong <foster.nong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add new status codes to PrintLibNate DeSimone2023-08-071-3/+7
| | | | | | | | | | | | | | | | PrintLib does not correctly decode the follow status codes: 1. EFI_IP_ADDRESS_CONFLICT 2. EFI_HTTP_ERROR 3. EFI_WARN_FILE_SYSTEM 4. EFI_WARN_RESET_REQUIRED These missing status codes have been added. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* MdePkg: Add missing status codesNate DeSimone2023-08-072-0/+12
| | | | | | | | | | | | | | | | | REF: https://uefi.org/specs/UEFI/2.10/Apx_D_Status_Codes.html Upon review it has been found that MdePkg is missing two status code definitions: 1. EFI_IP_ADDRESS_CONFLICT - Added in UEFI Spec v2.5 2. EFI_WARN_RESET_REQUIRED - Added in UEFI Spec v2.6 These missing status codes have been added. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* MdePkg/Include/IndustryStandard: Remove VS20xx workaroundMichael D Kinney2023-07-241-5/+0
| | | | | | | | | | | | | | | | | | | | | Remove workaround for the redefinition of the type RUNTIME_FUNCTION that is generated when building with VS20xx tool chains and using windows include files. The correct location for this fix is in the EmulatorPkg in the WinInclude.h file that addresses all the name collisions between edk2 types and windows types. The commit that added the workaround is: https://github.com/tianocore/edk2/commit/ff52068d9261b9391d75b83a2a4e40e040f3b6eb Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg/Register: RISC-V: Add satp mode bits shift definitionTuan Phan2023-07-151-3/+4
| | | | | | | | | | The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: RISC-V: Support getting satp register valueTuan Phan2023-07-152-0/+13
| | | | | | | | Add an API to retrieve satp register value. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Adds AMD SMRAM save state mapAbdul Lateef Attar2023-07-032-1/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds an SMM SMRAM save-state map for AMD processors. SMRAM save state maps for the AMD processor family are now supported. Save state map structure is added based on AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2. The AMD legacy save state map for 32-bit architecture is defined. The AMD64 save state map for 64-bit architecture is defined.  Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck, because structures defined in this file are derived from Intel/SmramSaveStateMap.h. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: PiStatusCode: Add TPM subclass definition to MdePkgKun Qin2023-06-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966 This change introduces a new peripheral subclass definition from PI specification v1.8. The new subclass definition will cover system reboot events under the status reports from Trusted Platform Modules (TPMs). These definition could provide helpful datapoints to OEMs to analyze system security state and healthiness, as well as avoid definition collision with other existing peripheral subclass definitions. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: PiStatusCode: Add new Host Software class Error Code to MdePkgKun Qin2023-06-231-20/+21
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794 This change introduces a new error code definitions under Host Software class according to PI specification v1.8. The new error code definition will cover system reboot events under the conditions of inconsistent memory map from one boot to another. These error codes could provide helpful datapoints to OEMs to investigate and prevent system failures in general. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Code optimization to SMM InternalAllocateAlignedPagesduntan2023-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is code optimization to InternalAllocateAlignedPages of SmmMemoryAllocationLib which can reduce free memory fragments. Also it can reduce one pre-allocation page. Let's take a simple example: The expected pages size is 8KB, Alignment value is 8KB. In original InternalAllocateAlignedPages(), the first step is to allocate 4 pages and then find the first 8KB-aligned address in allocated 4 pages. If the upper limit address of allocated 4 pages is already 8KB aligned, then the allocated 4 pages contains two 8KB-aligned 8KB ranges. The lower 2 pages will be selected and removed from free pages. Then the higher 2 pages will be free. Since the whole memory allocation is from high address to low address, then the higher 2 pages cann't be merged with other free pages, causing the free memory fragments. However, when only allocate 3(2+2-1) pages, we can avoid the free memory fragments in specific case. Also 3 pages must contain a 8KB-aligned 8KB range, which meets the requirement. If the upper limit address of allocated 3 pages is 8KB-aligned, then the higher 2 pages range of allocated 3 pages is 8KB-aligned and will be selected and removed from free pages. The remaining lower one page of allocated 3 pages will be free and merged with left lower free memory. This can reduce free memory fragments in smm. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bitTuan Phan2023-06-151-1/+0
| | | | | | | | | The timer compare register is 64-bit so simplifying the delay function. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64Yong Li2023-06-062-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 and below the commit for ARM and AArch64 implementation https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Evan Chai <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Signed-off-by: Yong Li <yong.li@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg ACPI65: Update MADT Revision pre ACPI Spec 6.5Aryeh Chen2023-06-061-1/+1
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4474 ACPI_Spec_6_5_Aug29 Table 5.19 page 128 that MADT Revision field is 6. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Aryeh Chen <aryeh.chen@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Aryeh Chen <aryeh.chen@intel.com>
* MdePkg/PeImage.h: add bits from BaseTools versionGerd Hoffmann2023-06-011-0/+31
| | | | | | | | | | The BaseTools and MdePkg versions of PeImage.h diverged over time, add some missing bits to the MdePkg header file in preparation for removing the BaseTools version. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: don't set visibility to hiddenGerd Hoffmann2023-06-011-14/+0
| | | | | | | | | Not needed any more on modern toolchains, they are better in not creating a GOT without this trick. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: add SBI-based SerialPortLib for RISC-VAndrei Warkentin2023-05-178-0/+767
| | | | | | | | | | | | | | | | | | | | | | These are implementations of SerialPortLib using SBI console services. - BaseSerialPortLibRiscVSbiLib is appropriate for SEC/PEI (XIP) environments - BaseSerialPortLibRiscVSbiLibRam is appropriate for PrePI/DXE environments Tested with: - Qemu RiscVVirt (non-DBCN case, backed by UART) - TinyEMU + RiscVVirt (non-DBCN case, HTIF) - TinyEMU + RiscVVirt (DBCN case, HTIF) Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: BaseRiscVSbiLib: make more useful to consumersAndrei Warkentin2023-05-172-6/+39
| | | | | | | | | | | Add a few more definitions and make SbiCall and TranslateError usable (not static) by library users. Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/IndustryStandard: Add SMBIOS anchor string & length defines.Giri Mudusuru2023-05-121-2/+20
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3805 Add SMBIOS spec defined anchor strings & length defines. - '_SM_' chapter 5.2.1 SMBIOS 2.1 (32-bit) Entry Point - '_SM3_' chapter 5.2.2 SMBIOS 3.0 (64-bit) Entry Point Changes from v1 to v2: - Replace non-ASCII characters Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Signed-off-by: Giri Mudusuru <girim@apple.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Add IPMI Interface Capabilities definitionsTinh Nguyen2023-05-121-0/+46
| | | | | | | | | | | | | This adds more definitions for the IPMI Get System Interface Capabilities command. Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add new PCDs for IPMI SSIFTinh Nguyen2023-05-121-0/+27
| | | | | | | | | | | | | | | | | BZ#: 4434 - Add IPMI SSIF definitions. This change adds new PCDs for IPMI SSIF. Specification reference: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Add definitions for IPMI SSIFTinh Nguyen2023-05-121-0/+98
| | | | | | | | | | | | | | | BZ#: 4434 - Add IPMI SSIF definitions. Specification reference: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add NULL library of TraceHubDebugSysTLibGua Guo2023-05-114-0/+187
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library is NULL library of TraceHubDebugSysTLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add MipiSysTLib libraryGua Guo2023-05-1111-3/+1508
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library provides functions consuming MIPI SYS-T submodule. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add mipisyst submoduleGua Guo2023-05-111-0/+0
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library provides functions consuming MIPI SYS-T submodule. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kubacki <mikuback@linux.microsoft.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add more HobLib/PeiServicesLib gmock supportGua Guo2023-05-107-0/+472
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4443 Add Google Mock Library for HobLib Add Google Mock Library for PeiServicesLib Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Chris Johnson <chris.n.johnson@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* BaseSynchronizationLib: Fix LoongArch64 synchronization functionsDongyan Qian2023-05-052-19/+13
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4432 There is a return value bug: The sc.w/sc.d instruction will destroy the reg_t0, use reg_t1 to avoid context reg_t0 being corrupted. Adjust Check that ptr align is UINT16. Optimize function SyncIncrement and SyncDecrement. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Reviewed-by: Chao Li <lichao@loongson.cn>
* MdePkg: Remove VS2008-VS2013 remnantsRebecca Cran2023-05-052-12/+4
| | | | | | | | | | | Since Visual Studio versions older than VS2015 are no longer supported, remove mention of them from MdePkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Tested-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BasePeCoffLib: Deal with broken debug directoriesArd Biesheuvel2023-05-051-0/+15
| | | | | | | | | | | | | | | | | | | | | | | Older versions of GenFw put the wrong value in the debug directory size field in the PE/COFF header: instead of putting the combined size of all the entries, it puts the size of the only entry it creates, but adds the size of the NB10 payload that the entry points to. This confuses the loader now that we started using additional debug directory entries to describe DLL characteristics. GenFw was fixed in commit 60e85a39fe49071, but the binaries that were generated with it still need to be supported. So let's detect this condition, and check whether the size of the debug directory is consistent with the NB10 payload: if we should expect additional directory entries where we observe the NB10 payload, the size field is clearly wrong, and we can break from the loop. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4425 Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: Support FDT library.Benny Lin2023-05-0515-1/+1232
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4392 Add FDT support in EDK2 by submodule 3rd party libfdt (https://github.com/devicetree-org/pylibfdt/tree/main/libfdt) and refer to LibcLib implementation by Pedro. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Benny Lin <benny.lin@intel.com> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* Tianocore: Support FDT library.Benny Lin2023-05-051-0/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4392 Add FDT support in EDK2 by submodule 3rd party libfdt (https://github.com/devicetree-org/pylibfdt/tree/main/libfdt) Add submodule libfdt and update ReadMe for the license. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Benny Lin <benny.lin@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add DEBUG_MANAGEABILITY print error levelAbner Chang2023-04-212-20/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bug #4414 Add DEBUG_MANAGEABILITY print error lever to output debug message of detailed manageability related module information, such as - RedfishPkg: - HTTP header/request/response - JSON plain text - Refish resource - Redfish Host interface information - Redfish credential information - Platform configuration to Redfish mapping - etc. - ManageabilityPKg - Protocol payload of MCTP/PLDM/IPMI - Payload of transport interface transfers - IPMI BLOB transfer - etc. - RedfishClinetPkg - Redfish feature driver dispatcher - Redfish BIOS attributes - Platform configuration (HII) to Redfish property information - Redfish C structure information - etc. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
* MdePkg/Include: Add DMTF PLDM SMBIOS definitionsAbner Chang2023-04-201-0/+183
| | | | | | | | | | | | | | | | | | | | BZ #4396 This change adds definitions for DMTF PLDM SMBIOS Transfer specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0246_1.0.1.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Add DMTF PLDM Base definitionsAbner Chang2023-04-201-0/+82
| | | | | | | | | | | | | | | | | | | BZ #4396 This change adds definitions for DMTF PLDM base specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0240_1.1.0.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add new JedecJep106Lib to fetch JEDEC JEP106 manufacturerRebecca Cran2023-04-125-0/+1898
| | | | | | | | | Add a new library, JedecJep106Lib which provides a service to return the JEDEC JEP106 manufacturer string given the code and continuation bytes values. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Library/BaseLib: HOST_APPLICATION IA32/X64 onlyMichael D Kinney2023-04-101-1/+1
| | | | | | | | | | | | | | Update BaseLib host-based unit test INF file to only list VALID_ARCHITECTURES of IA32 and X64 to align with all other host-based unit test INF files. The UnitTestFrameworkPkg only provides build support of host-based unit tests to OS applications for IA32 and X64. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* MdePkg: Add gmock examplesChris Johnson2023-04-108-0/+202
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4389 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chris Johnson <chris.n.johnson@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/PeCoffLib: Capture DLL characteristics fields in image contextArd Biesheuvel2023-04-073-12/+53
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4405 When loading a PE/COFF image, capture the DLL characteristics fields of the header into our image context structure so we can refer to them when mapping the image. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix conditionally uninitialized variablesMichael Kubacki2023-04-031-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes CodeQL alerts for CWE-457: https://cwe.mitre.org/data/definitions/457.html Note that this change affects the actual return value from the following functions. The functions documented that if an integer overflow occurred, MAX_UINTN would be returned. They were implemented to actually return an undefined value from the stack. This change makes the function follow its description. However, this is technically different than what callers may have previously expected. MdePkg/Library/BaseLib/String.c: - StrDecimalToUintn() - StrDecimalToUint64() - StrHexToUintn() - StrHexToUint64() - AsciiStrDecimalToUintn() - AsciiStrDecimalToUint64() - AsciiStrHexToUintn() - AsciiStrHexToUint64() Cc: Erich McMillan <emcmillan@microsoft.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Co-authored-by: Erich McMillan <emcmillan@microsoft.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/Base.h: Introduce various alignment-related macrosMarvin Häuser2023-04-011-1/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | ALIGNOF: Determining the alignment requirement of data types is crucial to ensure safe memory accesses when parsing untrusted data. IS_POW2: Determining whether a value is a power of two is important to verify whether untrusted values are valid alignment values. IS_ALIGNED: In combination with ALIGNOF data offsets can be verified. A more general version of the IS_ALIGNED macro previously defined by several modules. ADDRESS_IS_ALIGNED: Variant of IS_ALIGNED for pointers and addresses. Replaces module-specific definitions throughout the code base. ALIGN_VALUE_ADDEND: The addend to align up can be used to directly determine the required offset for data alignment. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Marvin Häuser <mhaeuser@posteo.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add TME-MK related CPUID and MSR definitionsRay Ni2023-04-012-3/+112
| | | | | | | | | | | | | | | TME (Total Memory Encryption) is the capability to encrypt the entirety of physical memory of a system. TME-MK (Total Memory Encryption-Multi-Key) builds on TME and adds support for multiple encryption keys. The patch adds some necessary CPUID/MSR definitions for TME-MK. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Update MemoryAttributesTable to v2.10Ard Biesheuvel2023-03-301-2/+6
| | | | | | | | | | | | | | | | UEFI v2.10 introduces a new flag to the memory attributes table to inform the OS whether or not runtime services code regions were emitted by the compiler with guard instructions for forward edge control flow integrity enforcement. So update our definition accordingly. Link: https://uefi.org/specs/UEFI/2.10/04_EFI_System_Table.html#efi-memory-attributes-table Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseRngLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-2/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseSynchronizationLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+5
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseMemoryLibOptDxe AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-305-0/+9
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-308-0/+10
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make LongJump() BTI compatibleArd Biesheuvel2023-03-301-2/+1
| | | | | | | | | | | | | | | | | | Currently, the AArch64 implementation of LongJump() avoids using the RET instruction to perform the jump, even though the target address is held in the link register X30, as the nature of a long jump implies that the ordinary return address prediction machinery will not be able to make a correct prediction. However, LongJump() is rarely used, and the return stack will be out of sync in any case, so this optimization has little value in practice, and given that indirect calls other than function returns require a BTI landing pad at the call site, this optimization is not compatible with BTI. So let's just use RET instead. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseIoLibIntrinsic AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+8
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseCpuLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-0/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/ProcessorBind AARCH64: Add asm macro to emit GNU BTI noteArd Biesheuvel2023-03-301-0/+34
| | | | | | | | | | Implement a CPP macro that can be called from .S files to emit the .note section carrying the annotation that informs the linker that the object file is compatible with BTI control flow integrity checks. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 02:09:20 +0000