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* UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bitTuan Phan2023-06-151-1/+0
| | | | | | | | | The timer compare register is 64-bit so simplifying the delay function. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64Yong Li2023-06-062-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 and below the commit for ARM and AArch64 implementation https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Evan Chai <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Signed-off-by: Yong Li <yong.li@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg ACPI65: Update MADT Revision pre ACPI Spec 6.5Aryeh Chen2023-06-061-1/+1
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4474 ACPI_Spec_6_5_Aug29 Table 5.19 page 128 that MADT Revision field is 6. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Aryeh Chen <aryeh.chen@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Aryeh Chen <aryeh.chen@intel.com>
* MdePkg/PeImage.h: add bits from BaseTools versionGerd Hoffmann2023-06-011-0/+31
| | | | | | | | | | The BaseTools and MdePkg versions of PeImage.h diverged over time, add some missing bits to the MdePkg header file in preparation for removing the BaseTools version. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: don't set visibility to hiddenGerd Hoffmann2023-06-011-14/+0
| | | | | | | | | Not needed any more on modern toolchains, they are better in not creating a GOT without this trick. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: add SBI-based SerialPortLib for RISC-VAndrei Warkentin2023-05-178-0/+767
| | | | | | | | | | | | | | | | | | | | | | These are implementations of SerialPortLib using SBI console services. - BaseSerialPortLibRiscVSbiLib is appropriate for SEC/PEI (XIP) environments - BaseSerialPortLibRiscVSbiLibRam is appropriate for PrePI/DXE environments Tested with: - Qemu RiscVVirt (non-DBCN case, backed by UART) - TinyEMU + RiscVVirt (non-DBCN case, HTIF) - TinyEMU + RiscVVirt (DBCN case, HTIF) Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: BaseRiscVSbiLib: make more useful to consumersAndrei Warkentin2023-05-172-6/+39
| | | | | | | | | | | Add a few more definitions and make SbiCall and TranslateError usable (not static) by library users. Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/IndustryStandard: Add SMBIOS anchor string & length defines.Giri Mudusuru2023-05-121-2/+20
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3805 Add SMBIOS spec defined anchor strings & length defines. - '_SM_' chapter 5.2.1 SMBIOS 2.1 (32-bit) Entry Point - '_SM3_' chapter 5.2.2 SMBIOS 3.0 (64-bit) Entry Point Changes from v1 to v2: - Replace non-ASCII characters Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Signed-off-by: Giri Mudusuru <girim@apple.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Add IPMI Interface Capabilities definitionsTinh Nguyen2023-05-121-0/+46
| | | | | | | | | | | | | This adds more definitions for the IPMI Get System Interface Capabilities command. Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add new PCDs for IPMI SSIFTinh Nguyen2023-05-121-0/+27
| | | | | | | | | | | | | | | | | BZ#: 4434 - Add IPMI SSIF definitions. This change adds new PCDs for IPMI SSIF. Specification reference: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Add definitions for IPMI SSIFTinh Nguyen2023-05-121-0/+98
| | | | | | | | | | | | | | | BZ#: 4434 - Add IPMI SSIF definitions. Specification reference: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add NULL library of TraceHubDebugSysTLibGua Guo2023-05-114-0/+187
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library is NULL library of TraceHubDebugSysTLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add MipiSysTLib libraryGua Guo2023-05-1111-3/+1508
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library provides functions consuming MIPI SYS-T submodule. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: K N Karthik <karthik.k.n@intel.com> Reviewed-by: Chan Laura <laura.chan@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add mipisyst submoduleGua Guo2023-05-111-0/+0
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144 This Library provides functions consuming MIPI SYS-T submodule. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Guo Gua <gua.guo@intel.com> Cc: Chan Laura <laura.chan@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: K N Karthik <karthik.k.n@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Signed-off-by: Guo Gua <gua.guo@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kubacki <mikuback@linux.microsoft.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add more HobLib/PeiServicesLib gmock supportGua Guo2023-05-107-0/+472
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4443 Add Google Mock Library for HobLib Add Google Mock Library for PeiServicesLib Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Chris Johnson <chris.n.johnson@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* BaseSynchronizationLib: Fix LoongArch64 synchronization functionsDongyan Qian2023-05-052-19/+13
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4432 There is a return value bug: The sc.w/sc.d instruction will destroy the reg_t0, use reg_t1 to avoid context reg_t0 being corrupted. Adjust Check that ptr align is UINT16. Optimize function SyncIncrement and SyncDecrement. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Reviewed-by: Chao Li <lichao@loongson.cn>
* MdePkg: Remove VS2008-VS2013 remnantsRebecca Cran2023-05-052-12/+4
| | | | | | | | | | | Since Visual Studio versions older than VS2015 are no longer supported, remove mention of them from MdePkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Tested-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BasePeCoffLib: Deal with broken debug directoriesArd Biesheuvel2023-05-051-0/+15
| | | | | | | | | | | | | | | | | | | | | | | Older versions of GenFw put the wrong value in the debug directory size field in the PE/COFF header: instead of putting the combined size of all the entries, it puts the size of the only entry it creates, but adds the size of the NB10 payload that the entry points to. This confuses the loader now that we started using additional debug directory entries to describe DLL characteristics. GenFw was fixed in commit 60e85a39fe49071, but the binaries that were generated with it still need to be supported. So let's detect this condition, and check whether the size of the debug directory is consistent with the NB10 payload: if we should expect additional directory entries where we observe the NB10 payload, the size field is clearly wrong, and we can break from the loop. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4425 Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: Support FDT library.Benny Lin2023-05-0515-1/+1232
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4392 Add FDT support in EDK2 by submodule 3rd party libfdt (https://github.com/devicetree-org/pylibfdt/tree/main/libfdt) and refer to LibcLib implementation by Pedro. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Benny Lin <benny.lin@intel.com> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* Tianocore: Support FDT library.Benny Lin2023-05-051-0/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4392 Add FDT support in EDK2 by submodule 3rd party libfdt (https://github.com/devicetree-org/pylibfdt/tree/main/libfdt) Add submodule libfdt and update ReadMe for the license. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Benny Lin <benny.lin@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add DEBUG_MANAGEABILITY print error levelAbner Chang2023-04-212-20/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bug #4414 Add DEBUG_MANAGEABILITY print error lever to output debug message of detailed manageability related module information, such as - RedfishPkg: - HTTP header/request/response - JSON plain text - Refish resource - Redfish Host interface information - Redfish credential information - Platform configuration to Redfish mapping - etc. - ManageabilityPKg - Protocol payload of MCTP/PLDM/IPMI - Payload of transport interface transfers - IPMI BLOB transfer - etc. - RedfishClinetPkg - Redfish feature driver dispatcher - Redfish BIOS attributes - Platform configuration (HII) to Redfish property information - Redfish C structure information - etc. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
* MdePkg/Include: Add DMTF PLDM SMBIOS definitionsAbner Chang2023-04-201-0/+183
| | | | | | | | | | | | | | | | | | | | BZ #4396 This change adds definitions for DMTF PLDM SMBIOS Transfer specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0246_1.0.1.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Add DMTF PLDM Base definitionsAbner Chang2023-04-201-0/+82
| | | | | | | | | | | | | | | | | | | BZ #4396 This change adds definitions for DMTF PLDM base specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0240_1.1.0.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add new JedecJep106Lib to fetch JEDEC JEP106 manufacturerRebecca Cran2023-04-125-0/+1898
| | | | | | | | | Add a new library, JedecJep106Lib which provides a service to return the JEDEC JEP106 manufacturer string given the code and continuation bytes values. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Library/BaseLib: HOST_APPLICATION IA32/X64 onlyMichael D Kinney2023-04-101-1/+1
| | | | | | | | | | | | | | Update BaseLib host-based unit test INF file to only list VALID_ARCHITECTURES of IA32 and X64 to align with all other host-based unit test INF files. The UnitTestFrameworkPkg only provides build support of host-based unit tests to OS applications for IA32 and X64. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* MdePkg: Add gmock examplesChris Johnson2023-04-108-0/+202
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4389 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chris Johnson <chris.n.johnson@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/PeCoffLib: Capture DLL characteristics fields in image contextArd Biesheuvel2023-04-073-12/+53
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4405 When loading a PE/COFF image, capture the DLL characteristics fields of the header into our image context structure so we can refer to them when mapping the image. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix conditionally uninitialized variablesMichael Kubacki2023-04-031-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes CodeQL alerts for CWE-457: https://cwe.mitre.org/data/definitions/457.html Note that this change affects the actual return value from the following functions. The functions documented that if an integer overflow occurred, MAX_UINTN would be returned. They were implemented to actually return an undefined value from the stack. This change makes the function follow its description. However, this is technically different than what callers may have previously expected. MdePkg/Library/BaseLib/String.c: - StrDecimalToUintn() - StrDecimalToUint64() - StrHexToUintn() - StrHexToUint64() - AsciiStrDecimalToUintn() - AsciiStrDecimalToUint64() - AsciiStrHexToUintn() - AsciiStrHexToUint64() Cc: Erich McMillan <emcmillan@microsoft.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Co-authored-by: Erich McMillan <emcmillan@microsoft.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/Base.h: Introduce various alignment-related macrosMarvin Häuser2023-04-011-1/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | ALIGNOF: Determining the alignment requirement of data types is crucial to ensure safe memory accesses when parsing untrusted data. IS_POW2: Determining whether a value is a power of two is important to verify whether untrusted values are valid alignment values. IS_ALIGNED: In combination with ALIGNOF data offsets can be verified. A more general version of the IS_ALIGNED macro previously defined by several modules. ADDRESS_IS_ALIGNED: Variant of IS_ALIGNED for pointers and addresses. Replaces module-specific definitions throughout the code base. ALIGN_VALUE_ADDEND: The addend to align up can be used to directly determine the required offset for data alignment. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Marvin Häuser <mhaeuser@posteo.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add TME-MK related CPUID and MSR definitionsRay Ni2023-04-012-3/+112
| | | | | | | | | | | | | | | TME (Total Memory Encryption) is the capability to encrypt the entirety of physical memory of a system. TME-MK (Total Memory Encryption-Multi-Key) builds on TME and adds support for multiple encryption keys. The patch adds some necessary CPUID/MSR definitions for TME-MK. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Update MemoryAttributesTable to v2.10Ard Biesheuvel2023-03-301-2/+6
| | | | | | | | | | | | | | | | UEFI v2.10 introduces a new flag to the memory attributes table to inform the OS whether or not runtime services code regions were emitted by the compiler with guard instructions for forward edge control flow integrity enforcement. So update our definition accordingly. Link: https://uefi.org/specs/UEFI/2.10/04_EFI_System_Table.html#efi-memory-attributes-table Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseRngLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-2/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseSynchronizationLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+5
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseMemoryLibOptDxe AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-305-0/+9
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-308-0/+10
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make LongJump() BTI compatibleArd Biesheuvel2023-03-301-2/+1
| | | | | | | | | | | | | | | | | | Currently, the AArch64 implementation of LongJump() avoids using the RET instruction to perform the jump, even though the target address is held in the link register X30, as the nature of a long jump implies that the ordinary return address prediction machinery will not be able to make a correct prediction. However, LongJump() is rarely used, and the return stack will be out of sync in any case, so this optimization has little value in practice, and given that indirect calls other than function returns require a BTI landing pad at the call site, this optimization is not compatible with BTI. So let's just use RET instead. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseIoLibIntrinsic AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+8
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseCpuLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-0/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/ProcessorBind AARCH64: Add asm macro to emit GNU BTI noteArd Biesheuvel2023-03-301-0/+34
| | | | | | | | | | Implement a CPP macro that can be called from .S files to emit the .note section carrying the annotation that informs the linker that the object file is compatible with BTI control flow integrity checks. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/Include: Add IPMI KCS definitionsAbner Chang2023-03-262-0/+82
| | | | | | | | | | | | | | | | | | | | BZ #4354 This change adds definitions for IPMI KCS. Spec ref: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Acked-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
* MdePkg/Include: Add DMTF MCTP definitionsAbner Chang2023-03-261-0/+139
| | | | | | | | | | | | | | | | | | | | BZ #4355 This change adds definitions for DMTF MCTP base specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Acked-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include/Ppi: Remove Itanium leftover data structurePaweł Poławski2023-03-261-46/+5
| | | | | | | | | | | | | | | | | | | | | | | | Itanium support has been removed from EDK2 around 2019. ITANIUM_HANDOFF_STATUS data structure looks to be some leftover from that process. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1560 GitHub: https://github.com/tianocore/edk2/commit/4e1daa60f5372c22a11503961061ffa569eaf873 There is also positive side effect of this data structure removal. Due to HOB allocation type used in PEI stage there is a limit how much data about virtual CPU can be hold. This limit result in only 1024 vCPU can be used by VM. With Itanium related data structure removed more allocated space can be used for vCPU data and with current allocation limit will change from 1024 to around 8k vCPUs. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Paweł Poławski <ppolawsk@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Update code to be more C11 compliant by using __func__Rebecca Cran2023-03-177-33/+33
| | | | | | | | | | | | | | | | | | __FUNCTION__ is a pre-standard extension that gcc and Visual C++ among others support, while __func__ was standardized in C99. Since it's more standard, replace __FUNCTION__ with __func__ throughout MdePkg. Visual Studio versions before VS 2015 don't support __func__ and so will fail to compile. A workaround is to define __func__ as __FUNCTION__ : #define __func__ __FUNCTION__ Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Update Base.h to be compliant with C11Rebecca Cran2023-03-171-6/+6
| | | | | | | | | | | | | | | | With the introduction of the use of _Static_assert, edk2 requires a C11 compatible compiler. Update Include/Base.h to be compliant with C11. As of C11, the maximum type of an enum is type `int`. Since the UEFI Specification 2.3.1 Errata C allows either `int` or `unsigned int`, fix the 32-bit enum check to use a signed int. Since the UEFI 2.3 Specification only allowed signed int, update the comment to reference 2.3.1 Errata C where the change was made to allow unsigned int. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add Memory Attribute Protocol definitionArd Biesheuvel2023-03-162-0/+145
| | | | | | | | | | Add the Memory Attribute Protocol definition, which was adopted and included in version 2.10 of the UEFI specification. Link: https://bugzilla.tianocore.org/show_bug.cgi?id=3519 Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix InvalidateInstructionCacheRangeTuan Phan2023-03-161-1/+6
| | | | | | | | When the range instruction cache invalidating not supported, the whole instruction cache should be invalidated instead. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Move API and implementation from UefiCpuLib to CpuLibYu Pu2023-03-105-0/+254
| | | | | | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib. Change-Id: Ic26f4c2614ed6bd9840f817d50e47ac1de4bd013 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean upAndrei Warkentin2023-03-081-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RegisterCpuInterruptHandler did not allow setting exception handlers for anything beyond the timer IRQ. Beyond that, it didn't meet the spec around handling of inputs. RiscVSupervisorModeTrapHandler now will invoke set handlers for both exceptions and interrupts. Two arrays of handlers are maintained - one for exceptions and one for interrupts. For unhandled traps, RiscVSupervisorModeTrapHandler dumps state using the now implemented DumpCpuContext. For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped PC address (SEPC), just like on AArch64 (ELR). This is necessary for X86EmulatorPkg to work as it allows a trap handler to return execution to a different place. Add SSTATUS/STVAL as well, at least for debugging purposes. There is no value in hiding this. Fix nested exception handling. Handler code should not be saving SIE (the value is saved in SSTATUS.SPIE) or directly restored (that's done by SRET). Save and restore the entire SSTATUS and STVAL, too. Cc: Daniel Schaefer <git@danielschaefer.me> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: BaseCpuLib: Fix RISCV CpuSleep symbol name.Andrei Warkentin2023-03-081-2/+2
| | | | | | | | | | | CpuSleep, not _CpuSleep. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: BaseLib: don't log in RISCV InternalSwitchStackAndrei Warkentin2023-03-081-8/+0
| | | | | | | | | | | | | | InternalSwitchStack may be called with a TPL high enough for a DebugLib implementation to assert. Other arch implementations don't log either. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-28 02:03:22 +0000