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* MdePkg/Library/BaseIoLibIntrinsic: Fix TD MMIO read type castZhiquan Li2024-01-201-3/+3
| | | | | | | | | | | Currently the types of casting mismatch with TD MMIO read 1, 2 and 4 bytes, that might introduce potential issues. So fix the types as conventional MmioRead[8|16|32] does. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiquan Li <zhiquan1.li@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/IndustryStandard: Add _PSD/_CPC/Coord types definitionsPierre Gondois2024-01-2010-0/+99
| | | | | | | | | | | Add definitions for: - _PSD version: added in ACPI 3.0 - C-state Coordination Types: added in ACPI 3.0 - _CPC version: added in ACPI 5.0 Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add DECLARE_LENGTH opcode of dependency expressionYi Li2024-01-191-14/+15
| | | | | | | | | | | | | | | | | | To avoid messy parsing of the Depex section of a Capsule, it would be a lot easier for everyone involved if we preceded the Capsule Depex Section with a length declaration. It provides simple bounds checking to avoid having to parse the op-codes, but in the case of a malformed depex being parsed, avoid other issues which can be messy. REF: UEFI spec 2.10 Table 23.4 Signed-off-by: Yi Li <yi1.li@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the Label definitions of the EFI_NVDIMM_LABELJunfeng Guan2024-01-161-1/+15
| | | | | | | | | | | Refer to Uefi spec 2.10 section 13.19.5, update the label definitions for NVDIMM SPA location cookie. Signed-off-by: Junfeng Guan <junfengx.guan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: RFC1323 definition changed to RFC7323Suqiang Ren2024-01-161-2/+2
| | | | | | | | | | | | | Change the description of RFC1323 to RFC7323 to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 28.2.5 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the comments of callback in EFI_FORM_BROWSER2_PROTOCOLSuqiang Ren2024-01-151-1/+4
| | | | | | | | | | | | | | Add status code return for BROWSER callback in EFI_FORM_BROWSER2_PROTOCOL to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 35.6.3 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Felix Polyudov <felixp@ami.com>
* MdePkg: Update the comments of HiiConfigAccess ExtractConfigSuqiang Ren2024-01-151-1/+8
| | | | | | | | | | | | | Add the status code return for HiiConfigAccess ExtractConfig to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 35.5.2 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix boot DxeCore hang on riscv platform王洋2024-01-113-7/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | For scene of HandOffToDxeCore()->SwitchStack(DxeCoreEntryPoint)-> InternalSwitchStack()->LongJump(),Variable HobList.Raw will be passed (from *Context1 to register a0) to DxeMain() in parameter *HobStart. However, meanwhile the function LongJump() overrides register a0 with a1 (-1) due to commit (ea628f28e5 "RISCV: Fix InternalLongJump to return correct value"), then cause hang. Replacing calling LongJump() with new InternalSwitchStackAsm() to pass addres data in register s0 to register a0 could fix this issue (just like the solution in MdePkg/Library/BaseLib/AArch64/SwitchStack.S) Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Cc: Bamvor Jian ZHANG <zhangjian@bosc.ac.cn> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ran Wang <wangran@bosc.ac.cn> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg/BaseLib: RISC-V: Add function to update stimecmp registerSunil V L2024-01-113-0/+15
| | | | | | | | | | | | | | stimecmp is a CSR supported only when Sstc extension is supported by the platform. This register can be used to set the timer interrupt directly in S-mode instead of going via SBI call. Add a function to update this register. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg.dec: RISC-V: Define override bit for Sstc extensionSunil V L2024-01-111-0/+2
| | | | | | | | | | | | | Define the BIT 1 as the override bit for Sstc extension. This will be used by the timer driver to decide whether to use SBI calls or direct CSR access to configure the timer. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: Update GetHealthStatus function descriptionJunfeng Guan2024-01-111-24/+8
| | | | | | | | | | | Refer to Uefi spec 2.10 section 11.10.2, update the return value for EFI_DRIVER_HEALTH_PROTOCOL.GetHealthStatus. Signed-off-by: Junfeng Guan <junfengx.guan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the definition of EFI_NVDIMM_LABEL_FLAGS_LOCALSuqiang Ren2024-01-091-0/+2
| | | | | | | | | | | | | Add the description of EFI_NVDIMM_LABEL_FLAGS_LOCAL to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 13.19.4 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the definition of CapsuleImageSize on EFI_CAPSULE_HEADERSuqiang Ren2024-01-081-1/+1
| | | | | | | | | | | | | Add the description of CapsuleImageSize to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 8.5.3.1 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Felix Polyudov <felixp@ami.com>
* MdePkg/MdeLibs.dsc.inc: Add SafeIntLib instanceJiaxin Wu2023-12-201-0/+1
| | | | | | | | | | | | | This patch is to add SafeIntLib in MdeLibs.dsc.inc Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Utilize Cache Management Operations Implementation For RISC-VDhaval Sharma2023-12-194-28/+165
| | | | | | | | | | | | | | | | Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Implement RISC-V Cache Management OperationsDhaval2023-12-194-1/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Sunil V L <sunilvl@...> Reviewed-by: Jingyu Li <jingyu.li01@...>
* MdePkg: Rename Cache Management Function To Clarify Fence Based OpDhaval2023-12-193-8/+8
| | | | | | | | | | | | | | | | | | | | There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Move RISC-V Cache Management Declarations Into BaseLibDhaval Sharma2023-12-192-20/+20
| | | | | | | | | | | | | | | The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg:simplify Fifo API in BaseIoLibIntrinsicDun Tan2023-12-114-259/+222
| | | | | | | | | | | | | | | | | | Simplify IoRead/WriteFifo implement by repeatedly calling IoRead/Write in the C code. This can avoid calling assembly code to use string I/O instructions. With this change Ia32/IoFifo.nasm and X64/IoFifo.nasm can be removed. Then the source files for IA32 and X64 are the same. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Change IoLibFifo.c to IoLibFifoCc.cDun Tan2023-12-112-2/+2
| | | | | | | | | | | | | | | | Change IoLibFifo.c to IoLibFifoCc.c since the file is for Tdx and SEV in BaseIoLibIntrinsicSev. It's also to distinguish with a new incoming IoLibFifo.c for BaseIoLibIntrinsic. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Update MdePkg.uni with manageability debug levelRebecca Cran2023-12-111-0/+2
| | | | | | | Update MdePkg.uni with the manageability debug level. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add manageability debug level to PcdFixedDebugPrintErrorLevelRebecca Cran2023-12-111-0/+1
| | | | | | | | Update MdePkg.dec to add the manageability debug level to PcdFixedDebugPrintErrorLevel. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Improve wording of manageability debug level commentRebecca Cran2023-12-111-2/+2
| | | | | | | | Improve the wording of the comment explaining the DEBUG_MANAGEABILITY debug level. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add UEFI v2.10 ISA memory type definitionManickamX Srinivasan2023-12-091-0/+15
| | | | | | | | | | | | New memory type as defined in UEFI standard v2.10 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: T V Krishnamoorthy <krishnamoorthy.t.v@intel.com> Signed-off-by: ManickamX Srinivasan <manickamx.srinivasan@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Define the DevicePath argument from LoadImage as optionalManickamX Srinivasan2023-12-081-1/+1
| | | | | | | | | | | | | Update the EFI LoadImage API in accordance with the UEFI v2.10 specification. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: T V Krishnamoorthy <krishnamoorthy.t.v@intel.com> Signed-off-by: ManickamX Srinivasan <manickamx.srinivasan@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* BaseStackCheckLib: Fix STACK FAULT messageJake Garver2023-12-061-1/+2
| | | | | | | | __builtin_return_address returns a pointer, not a string. Fix the STACK FAULT message in BaseStackCheckLib appropriately. Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg:Add NVME Sanitize command support to Nvme.hTina Chen2023-12-051-11/+110
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4591 1. Refer NVME spec 2.0c chapter 5.24, add Sanitize Command related definition. 2. Refer NVME spec 2.0c chapter 5.16, add Get Log Page Command related definition for Sanitize status support. Cc: Ray Ni <ray.ni@intel.com> Cc: Xiao X Chen <xiao.x.chen@intel.com> Cc: Arthur Chen <arthur.g.chen@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Tina Chen <tina.chen@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Test: Add google tests for BaseLibPedro Falcato2023-12-034-0/+118
| | | | | | | | | | | | Add GoogleTestBaseLib, which contains gtest unit tests for BaseLib. For now, only add checksum tests for CRC32C and CRC16; these tests check for correctness on various inputs using precomputed hashes. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: Fix CRC16-ANSI calculationPedro Falcato2023-12-032-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4609 The current CalculateCrc16Ansi implementation does the following: 1) Invert the passed checksum 2) Calculate the new checksum by going through data and using the lookup table 3) Invert it back again This emulated my design for CalculateCrc32c, where 0 is passed as the initial checksum, and it inverts in the end. However, CRC16 does not invert the checksum on input and output. So this is incorrect. Fix the problem by not inverting input checksums nor output checksums. Callers should now pass CRC16ANSI_INIT as the initial value instead of "0". This is a breaking change. This problem was found out-of-list when older ext4 filesystems (that use crc16 checksums) failed to mount with "corruption". Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Tdx.h: Add TDVMCALL_STATUS_RETRYCeping Sun2023-11-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4572 TDVMCALL_STATUS_RETRY is defined in GHCI spec section 2.4.1. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.0 https://cdrdv2.intel.com/v1/dl/getContent/726790 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
* MdePkg/BaseLib: Update TdVmcall to always output the value in R11Ceping Sun2023-11-091-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4572 According to section 3.2 of the [GHCI] spec, if the return status of MapGPA is "TDG.VP.VMCALL_RETRY", TD must retry this operation for the pages in the region starting at the GPA specified in R11. Currently, TDVF has not handled the retry results and always clears the R11 on unsuccessful return status. For this, the TdVmcall needs to output the value of R11 on unsuccessful return status to handle the retry results of MapGPA. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.0 https://cdrdv2.intel.com/v1/dl/getContent/726790 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
* MdePkg: IndustryStandard: Add DLL CharacteristicsJoey Vagedes2023-11-061-1/+16
| | | | | | | | | | | | | | | | Add the bit masks for DLL Characteristics, used within the optional header of a PE, to the PeImage.h header file. Update the Visual Studio, Microsoft Portable Executable and Common Object File Format Specification, and the PE/COFF Specification to the latest version. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Joey Vagedes <joeyvagedes@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg ACPI65: Add 0x0B/PRM to Generic Address StructureJinlong Xu2023-10-311-0/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4567 ACPI_Spec_6_5_Aug29 Table 5.1, add 0x0B/Platform Runtime Mechanism (PRM) in Address Space ID of Generic Address Structure (GAS) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Jinlong Xu <jinlong.xu@intel.com> Message-Id: <20231020111348.2921-1-jinlong.xu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: MADT: Add TRBE interrupt to GICCSami Mujawar2023-10-301-0/+1
| | | | | | | | | | | | | | The ASWG ECR 2303 introduces a new field 'TRBE interrupt' to GICC structure in ACPI 6.5. The Trace Buffer Extension (TRBE) interrupt is a Processor Private interrupt (PPI) and is used to specify a platform-specific interrupt to signal TRBE events. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: MADT: Add Online capable flag in GICCSami Mujawar2023-10-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Bugzilla: 3706 'Code First - MADT GICC new flags' On ARM systems physical CPU hotplug is not supported. All CPUs are considered present and this is true throughout the system uptime. The ECR 2285 introduces a new 'online-capable' flag in the GICC structure flags in ACPI 6.5, to signal firmware policy (CPU is not enabled but it can be enabled and onlined). This enables OSPM to support virtual CPU hotplug (on virtual platforms for instance). This ECR also updates the MADT table revision to 6 to reflect the ACPI 6.5 changes. Therefore, update the MADT table revision to match the value as specified in ACPI 6.5. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: Apply uncrustify formatting to relevant filesVivian Nowka-Keane2023-10-2711-458/+463
| | | | | | | | | | Apply uncrustify formatting to GoogleTest cpp and header files. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Vivian Nowka-Keane <vnowkakeane@linux.microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Definitions of IPMI Get System Interface CapabilitiesAbner Chang2023-10-261-0/+8
| | | | | | | | | | | | Define the structure for IPMI Get System Interface Capabilities command (0x57) Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Nickle Wang <nicklew@nvidia.com>
* MdePkg: Add Cxl20.h into IndustryStandardChris Li2023-10-262-1/+464
| | | | | | | | | | | | | 1) Add CXL 2.0 header file to comply with CXL 2.0 specification 2) CXL 2.0 header will embed Cxl11.h 3) Updated Cxl.h to point to 2.0 header file Signed-off-by: Chris Li <chrisli@os.amperecomputing.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Yao, Jiewen <jiewen.yao@intel.com> Cc: Nong, Foster <foster.nong@intel.com> Cc: Kinney, Michael D <michael.d.kinney@intel.com>
* MdePkg/Pldm.h: Add define for the PLDM response flagKonstantin Aladyshev2023-10-251-0/+1
| | | | | | | | | The PLDM protocol uses Request bit to help differentiate between PLDM request and response messages. Currently the Pldm.h header only have a flag for the request message. Add a flag for the response message as well. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
* MdePkg/Mctp.h: Correct typo in structure member nameKonstantin Aladyshev2023-10-251-1/+1
| | | | | | | | Correct MCTP_TRANSPORT_HEADER structure field 'SourceEndpointIdId' to 'SourceEndpointId'. Signed-off-by: Abner Chang <abner.chang@amd.com> Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
* MdePkg: CI: Add PrEval entryJoey Vagedes2023-10-231-0/+3
| | | | | | | | | | | | | | | | | | | Adds a PrEval entry to the package's ci.yaml file which is used to verify if the package uses a particular library instance when that library instance file (INF) is updated. When a library instance file (INF) is updated, PrEval will review each package's DSC as described in the ci.yaml file to determine if the package uses said library instance. If the package does use the library instance, it will be built and tested to ensure the package is not broken from the change. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Joey Vagedes <joeyvagedes@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Test: Add DevicePathLib host test moduleMateusz Albecki2023-10-196-1/+1073
| | | | | | | | | | This commit adds host-based unit tests for device path lib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@bysoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com> Reviewed-by: Michael D Kinney <Michael.d.kinney@intel.com>
* MdePkg/UefiDevicePathLib: Fix AcpiEx print logicMateusz Albecki2023-10-191-27/+45
| | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4555 Add logic that checks if the code doesn't overflow ACPI_EXTENDED_HID_DEVICE_PATH node when searching for optional strings. If the string is not provided in the device path node default value of "\0" is used. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@bysoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com> Reviewed-by: Michael D Kinney <Michael.d.kinney@intel.com>
* MdePkg/DxeRngLib: Add missing GUID declaration in infPierre Gondois2023-10-041-0/+1
| | | | | | | | | | | | Add missing GUID declaration in DxeRngLib.inf. Fixes: bd1f0eecc1df ("MdePkg/DxeRngLib: Request raw algorithm instead of default") Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Leif Lindholm <quic_llindhol@quicinc.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/BaseLib: fix typo in Arm SetJumpLeif Lindholm2023-10-031-1/+1
| | | | | | | | | | RO -> R0 Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: ensure ARM LongJump never returns 0Leif Lindholm2023-10-022-0/+4
| | | | | | | | | | | The ARM implementation of InternalLongJump always returned the value Value - but it is not supposed to ever return 0. Add the test to prevent that, and return 1 if Value is 0 - as is already present in AArch64. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: correct register sizes in AArch64 SetJump/LongJumpLeif Lindholm2023-10-022-8/+8
| | | | | | | | | | | | | | | | Both in SetJump and in InternalLongJump, 32-bit w register views were used for the UINTN return value. In SetJump, this did not cause errors; it was only counterintuitive. But in InternalLongJump, it meant the top 32 bits of Value were stripped off. Change all of these to use the 64-bit x register views. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reanimated-by: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg/BaseLib: use normal register init in ARM SetJump implementationsLeif Lindholm2023-10-022-2/+2
| | | | | | | | | | | | | There may be architectures on which there are benefits to eor r0, r0(, r0) but ARM was never one of them. Change to more readable mov r0, #0 instead. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: add ASSERT in ARM* SetJump implementationsLeif Lindholm2023-10-022-0/+16
| | | | | | | | | | | | | The SetJump comment header states that: If JumpBuffer is NULL, then ASSERT(). However, this was not currently done. Add a call to InternalAssertJumpBuffer. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: fix comments in ARM* SetJump/LongJump implementationsLeif Lindholm2023-10-024-8/+4
| | | | | | | | | | | | | | Drop redundant comment about IPF (clearly copied across from now deleted code). Also change "Instead is resumes execution" -> "Instead it resumes execution" Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 22:42:17 +0000