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* MdePkg Cper.h: Add generic error macros for ARM platformedk2-stable201808Ming Huang2018-08-151-0/+3
| | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <ming.huang@linaro.org>
* MdePkg/BaseLib: Add an additional check within AsciiStriCmpRuiyu Ni2018-08-061-1/+1
| | | | | | | | | | | This commit adds an addtional check in AsciiStriCmp. It explicitly checks the end of the sting pointed by 'SecondString' to make the code logic easier for reading and to prevent possible mis-reports by static code checkers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <Hao.a.wu@intel.com>
* MdePkg FirmwareManagement.h: Fix code style issueStar Zeng2018-08-011-4/+4
| | | | | | | | | | | Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Hess Chen <hesheng.chen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* MdePkg/SmmMemLib: Avoid possible NULL ptr dereferenceHao Wu2018-07-311-1/+1
| | | | | | | | | Within function SmmMemLibInternalGetUefiMemoryAttributesTable(), add a check to avoid possible null pointer dereference. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg/SmmMemLib: Check EFI_MEMORY_RO in UEFI mem attrib table.Jiewen Yao2018-07-262-3/+59
| | | | | | | | | It treats the UEFI runtime page with EFI_MEMORY_RO attribute as invalid SMM communication buffer. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdePkg/SmmMemLib: Check for untested memory in GCDJiewen Yao2018-07-262-5/+92
| | | | | | | | | It treats GCD untested memory as invalid SMM communication buffer. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdePkg/BaseLib: Add bit field population calculating methodsTomas Pilar (tpilar)2018-07-092-0/+142
| | | | | | | | | | | | | | | | Hopefully this should tidy the conversion warnings. ---- Add 32-bit and 64-bit functions that count number of set bits in a bitfield using a divide-and-count method. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Tomas Pilar <tpilar@solarflare.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* MdePkg: IORT Specification Rev D updatesSami Mujawar2018-06-281-4/+6
| | | | | | | | | | | | | | | Updated IORT structure definitions to conform to the IO Remapping Table, Platform Design Document, Revision D, March 2018. The following structures have been updated: 1. SMMUv3 - fix on proximity node. 2. PMCG - added page 1 support. 3. Root complex node - added DMA mask (memory address size limit). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: SMMUv3 updates for IORT table definitionsSami Mujawar2018-06-281-1/+10
| | | | | | | | | | | | Updated the IORT SMMUv3 Node structure and flags to match the IO Remapping Table, Platform Design Document, Revision C dated 15 MAY 2017. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Clean up source filesLiming Gao2018-06-28729-15717/+15717
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* MdePkg: TpmPtp: Add CapCRBIdleBypass definitionZhang, Chao B2018-06-271-2/+3
| | | | | | | | | | | Add CapCRBIdleBypass definition to interface ID register. It complies with existing register Cc: Long Qin <qin.long@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Long Qin <qin.long@intel.com>
* MdePkg/PerformanceLib.h: Add new Perf macrosBi, Dandan2018-06-264-3/+477
| | | | | | | | | | | | | | 1. Add new Perf macros for performance measurement and related APIs and definitions in Performance library class. 2. Update NULL performance library instance in MdePkg. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/IndustryStandard/Ipmi: Use union for bitmap fieldsHao Wu2018-06-195-536/+1076
| | | | | | | | | | | | This commit enhances the bitmap fields defined in the IPMI header files, union types will be used to provide the users with both the individual bitmap access and the whole byte/word access. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/IndustryStandard/Ipmi: Update IPMI header filesHao Wu2018-06-196-60/+789
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=814 This commit updates the IPMI related header files. Cc: Younas Khan <pmdyounaskhan786@gmail.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg UefiLib: Use comparison logic to check UINTN parameterLiming Gao2018-06-122-7/+7
| | | | | | | | | | Commit d2aafe1e410c80d1046f2d1e743055882ead8489 changes the input parameter from BOOLEAN to UINTN. Its comparison logic should be updated. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVMArd Biesheuvel2018-06-118-0/+1400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KVM on ARM refuses to decode load/store instructions used to perform I/O to emulated devices, and instead relies on the exception syndrome information to describe the operand register, access size, etc. This is only possible for instructions that have a single input/output register (as opposed to ones that increment the offset register, or load/store pair instructions, etc). Otherwise, QEMU crashes with the following error error: kvm run failed Function not implemented R00=01010101 R01=00000008 R02=00000048 R03=08000820 R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8 R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080 R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c PSR=800001f3 N--- T svc32 QEMU: Terminated and KVM produces a warning such as the following in the kernel log kvm [17646]: load/store instruction decoding not implemented The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic is based on C code, and when LTO is in effect, the MMIO accesses could be merged with, e.g., manipulations of the loop counter, producing opcodes that KVM does not support for emulated MMIO. So let's add a special ArmVirt flavor of this library that implements that actual load/store operations in assembler, ensuring that the instructions involved can be emulated by KVM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Remove X86 ASM and S filesLiming Gao2018-06-07308-15375/+8
| | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* MdePkg UefiLib: Fix in EfiLocateProtocolBuffer()Star Zeng2018-06-051-0/+4
| | | | | | | | | | Free HandleBuffer for error path in EfiLocateProtocolBuffer(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/UefiRuntimeLib: Do not allow to be linked by DXE driverRuiyu Ni2018-06-051-2/+2
| | | | | | | | | | | | | | | | | | When UefiRuntimeLib links to a DXE driver, its constructor still registers a Virtual Address Change event. The event callback will get called when RT.SetVirtualAddressMap() is called from OS. But when the driver is a DXE driver, the memory occupied by the callback function might be zeroed or used by OS since the BS type memory is free memory when entering to RT phase. The patch reverts commit 97511979b4fdd84cf7cd51e43c22dc03e79bd4f3 "MdePkg/UefiRuntimeLib: Support more module types." It makes sure that DXE driver cannot link to this library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdePkg/DxeServicesLib: introduce AllocatePeiAccessiblePages routineArd Biesheuvel2018-05-294-2/+155
| | | | | | | | | | | | | Add a routine to DxeServicesLib that abstracts the allocation of memory that should be accessible by PEI after resuming from S3. We will use it to replace open coded implementations that limit the address to < 4 GB, which may not be possible on non-Intel systems that have no 32-bit addressable memory at all. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Update MmSwDispatch.h's references to SmmSw2Dispatch.Marvin.Haeuser@outlook.com2018-05-281-3/+3
| | | | | | | | | | | | MmSwDispatch.h current refers to the deprecated SmmSw2Dispatch protocol. Replace those references with the new MmSwDispatch name. V2: - Do not change the copyright date as requested. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Hpet: Add Event Timer Block ID definition.Marvin.Haeuser@outlook.com2018-05-281-0/+16
| | | | | | | | | | | | This patch adds the HPET Event Timer Block ID definition that can be found in the IA-PC HPET Specification, section 3.2.4. V2: - Do not change the copyright date as requested. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/TcgStorage*.h: Fixed ECC reported issues.Eric Dong2018-05-242-5/+5
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* MdePkg/IndustryStandard: Add header file for SPMI ACPI tableHao Wu2018-05-231-0/+104
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=840 Add the header file for Service Processor Management Interface ACPI table definition. Cc: Younas Khan <pmdyounaskhan786@gmail.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg UefiLib: Fix XCODE5 varargs warningLiming Gao2018-05-232-2/+2
| | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=741 Change GetBestLanguage() parameter type from BOOLEAN to UINTN Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Steven Shi <steven.shi@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/SmmPeriodicSmiLib: Get Periodic SMI Context More RobustlyRuiyu Ni2018-05-211-23/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PeriodicSmiDispatchFunction() in SmmPeriodicSmiLib may assert with "Bad CR signature". Currently, the SetActivePeriodicSmiLibraryHandler() function (invoked at the beginning of the PeriodicSmiDispatchFunction() function) attempts to locate the PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT structure pointer for the current periodic SMI from a given EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT (RegiserContext) structure pointer (using the CR macro). The RegisterContext structure pointer passed to the PeriodicSmiDispatchFunction() is assumed to point to the same RegisterContext structure address given to the SmmPeriodicTimerDispatch2 protocol Register() API in PeriodicSmiEnable(). However, certain SmmPeriodicTimerDispatch2 implementation may copy the RegisterContext to a local buffer and pass that address as the context to PeriodicSmiDispatchFunction() in which case usage of the CR macro to find the parent structure base fails. The patch uses the LookupPeriodicSmiLibraryHandler() function to find the PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT structure pointer. This works even in this scenario since the DispatchHandle returned from the SmmPeriodicTimerDispatch2 Register() function uniquely identifies that registration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/UefiLib: Add 'OUT' decorator where necessary.Marvin.Haeuser@outlook.com2018-05-172-18/+18
| | | | | | | | | | | | The functions AddUnicodeString() and AddUnicodeString2() might return a new value into their parameter UnicodeStringTable, hence add the appropiate 'OUT' decorator. V2: Update FrameworkUefiLib as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/PeiServicesLib: Decorate 'PpiDescriptor' as OPTIONAL for LocatePpi().Marvin.Haeuser@outlook.com2018-05-172-4/+4
| | | | | | | | | | | The UEFI PI specification defines PpiDescriptor to be OPTIONAL for the LocatePpi PEI Service. This patch reflects this in the function declaration and definition of the corresponding PeiServices library function. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/TcgStorage*.h: Add referenced spec information.Eric Dong2018-05-172-2/+21
| | | | | | | | | Add link and version info for the referenced spec. Cc: Jiewen yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdePkg: Add Feature definitions added in pyrite 2.0 spec.Eric Dong2018-05-072-0/+56
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdePkg/DevicePathToText: Fix iSCSI.Lun byte order issueRuiyu Ni2018-05-021-6/+8
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg FirmwareManagement.h: Fix typo EFI_SECURITY_VIOLATIOStar Zeng2018-04-251-6/+7
| | | | | | | | | | | Fix typo EFI_SECURITY_VIOLATIO to EFI_SECURITY_VIOLATION. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg/Library/BaseCpuLib: Enable VS2017/ARM64 buildsPete Batard2018-04-173-3/+84
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/BaseSynchronizationLib: Enable VS2017/ARM64 buildsPete Batard2018-04-172-1/+207
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include/Protocol/Tls.h: pack structures from the TLS RFCLaszlo Ersek2018-04-131-0/+10
| | | | | | | | | | | | | | | | The structures defined in RFC 5246 are not to have any padding between fields or at the end; use the "pack" pragma as necessary. Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=915 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Long Qin <qin.long@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
* MdePkg DxeHstiLib: Fix ErrorString pointer incorrectly calculatedStar Zeng2018-04-131-2/+2
| | | | | | | | | | | | Fix ErrorString pointer is incorrectly calculated in InternalHstiIsValidTable(). Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg/BaseLib: add PatchInstructionX86()Laszlo Ersek2018-04-043-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | Some edk2 modules generate X86 machine code at module execution time by: - compiling "template" code with NASM at module build time, - linking the object code into the module, - and patching the immediate (constant) operands of some instructions when the module is executed. Add a helper function to BaseLib so that the C code performing the patching is easier to read and maintain. The implementation in this patch is taken mainly from Mike Kinney's mailing list messages at <http://mid.mail-archive.com/E92EE9817A31E24EB0585FDF735412F5B895C360@ORSMSX113.amr.corp.intel.com>, <http://mid.mail-archive.com/E92EE9817A31E24EB0585FDF735412F5B898BF66@ORSMSX112.amr.corp.intel.com>. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib.h: state preprocessing conditions in comments after #endifsLaszlo Ersek2018-04-041-13/+11
| | | | | | | | | | | | | | "#endif" preprocessing directives near the top of "BaseLib.h" helpfully repeat the preprocessing conditions from their matching "#if", "#ifdef", and "#ifndef" directives. This practice has been less followed recently; supplement the missing comments. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Tls1.h: Add TLS record header length and max payload length.Jiaxin Wu2018-03-221-1/+15
| | | | | | | | | | Cc: Karunakar P <karunakarp@amiindia.co.in> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Ye Ting <ting.ye@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Karunakar p <karunakarp@amiindia.co.in> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
* MdePkg BaseStackCheckLib: Correct style of file headerLiming Gao2018-03-201-5/+2
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Bi Dandan <dandan.bi@intel.com>
* MdePkg/Library/BaseLib/AArch64: Comment style harmonizationPete Batard2018-03-202-94/+98
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include: Add VA list support for VS2017/ARM64Pete Batard2018-03-191-4/+3
| | | | | | | | | | | We need to explicitly call the built-in __va_start() for ARM64, otherwise the variable parameters are not properly enqueued for the next function calls. Also do the same for ARM, as as it doesn't harm us. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/BaseLib: Enable VS2017/ARM64 buildsPete Batard2018-03-198-0/+378
| | | | | | | | Required GCC assembly files are converted for the MSFT assembler Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Disable some Level 4 warnings for VS2017/ARM64Pete Batard2018-03-191-2/+51
| | | | | | | | We disable the exact same warnings as IA32 and X64. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/DevicePathFromText: Fix byte orders of iSCSI.LunRuiyu Ni2018-03-031-1/+3
| | | | | | | | | | | | | | | Per UEFI spec, iSCSI.Lun is a 8-byte array with byte #0 in the left. It means "0102030405060708" should be converted to: UINT8[8] = {01, 02, 03, 04, 05, 06, 07, 08} or UINT64 = {0807060504030201} Today's implementation wrongly uses the reversed order. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jie Lin <jie.lin@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com>
* MdePkg/DevicePathFromText: Fix bug when converting iSCSI nodeRuiyu Ni2018-03-031-2/+2
| | | | | | | | | | If protocol string is not specified, default TCP(0) should be used. Today's implementation wrongly sets to 1 for this case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header fileFelix Polyudov2018-03-031-0/+89
| | | | | | | | | | | | | | v3: LaneEqualizationControl is changed to be an array. v2: The structure is updated to include all the fields defined in the PCI-E specification. The header includes Physical Layer PCI Express Extended Capability definitions described in section 7.7.5 of PCI Express Base Specification rev. 4.0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Felix Polyudov <felixp@ami.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseSafeIntLib: Fix VS2015 IA32 NOOPT build failureDandan Bi2018-02-283-5/+10
| | | | | | | | | | | | | | | | | | | | v2: Add [LibraryClasses] section in INF file and refine coding style. There are VS2015 NOOPT IA32 build failure like below in BaseSafeIntLib. XXX.lib(XXX.obj): error LNK2001: unresolved external symbol __allmul XXX.lib(XXX.obj): error LNK2001: unresolved external symbol __allshl XXX.lib(XXX.obj): error LNK2001: unresolved external symbol __aullshr This patch replaces direct shift/multiplication of 64-bit integer with related function call to fix these failure. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg BaseCpuLib: Make it pass VS ARM buildLiming Gao2018-02-261-1/+3
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Pete Batard <pete@akeo.ie>
* MdePkg: introduce DxeRuntimeDebugLibSerialPortArd Biesheuvel2018-02-243-0/+422
| | | | | | | | | | | | | | Introduce a variant of BaseDebugLibSerialPort that behaves correctly with regards to the use of the serial port after ExitBootServices(). At boot time, all DEBUG() prints and ASSERT() invocations are executed normally. At runtime, DEBUG() prints are dropped entirely, and ASSERT()s omit the serial output as well, and only perform the configured post-ASSERT() action, i.e., issue a CPU breakpoint or enter a deadloop. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 06:36:13 +0000