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* MdePkg/BaseSynchronizationLib: RISC-V cache related code.Abner Chang2020-05-072-0/+83
| | | | | | | | | | | | | | | | | Support RISC-V cache related functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseCpuLib: RISC-V Base CPU libraryAbner Chang2020-05-073-3/+27
| | | | | | | | | | | | | | | | | | implementation. Implement RISC-V CPU related functions in BaseCpuLib. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.Abner Chang2020-05-075-1/+151
| | | | | | | | | | | | | | | | Support RISC-V image relocation. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.cAbner Chang2020-05-072-5/+12
| | | | | | | | | | | | | | | | | | RISC-V MMIO library instance. IoLibArm.c in fact implements a generic Mmio-only (and ANSI C compliant), so rename it to better reflect this. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseCacheMaintenanceLib:Abner Chang2020-05-072-0/+254
| | | | | | | | | | | | | | | | | | | RISC-V cache maintenance implementation. Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseLib: BaseLib for RISCV64 architectureAbner Chang2020-05-0713-1/+374
| | | | | | | | | | | | | | | | Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/Include: RISC-V definitions.Abner Chang2020-05-075-0/+89
| | | | | | | | | | | | | | | | Add RISC-V processor related definitions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg: Add RISC-V RISCV64 bindingAbner Chang2020-05-073-2/+179
| | | | | | | | | | | | | | | | Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/Security2: Mark the File parameter as OPTIONAL.Guomin Jiang2020-04-221-1/+1
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2652 According to the description, the File is OPTIONAL and can be NULL. Signed-off-by: Guomin Jiang <guomin.jiang@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Add linked list iteration macrosMichael Kubacki2020-04-211-0/+27
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1959 The macros EFI_LIST_FOR_EACH and EFI_LIST_FOR_EACH_SAFE have been duplicated across several drivers. These macros have proven useful and established a commonly used pattern for linked list iteration. This change defines the macros in BaseLib.h alongside other generic linked list macros and functions. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Guomin Jiang <guomin.jiang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
* MdePkg: Add AML FieldList OpCode definitionsPierre Gondois2020-04-171-0/+8
| | | | | | | | | | | | | | | | | | | | | The ACPI specification, version 6.3, January 2019, defines the Named Objects Encoding for FieldElements in section '20.2.5.2 Named Objects Encoding'. FieldElements can be one of the following: NamedField | ReservedField | AccessField | ExtendedAccessField | ConnectField Some of these keywords are starting with an opcode, allowing to identify their type. E.g.: ReservedField := 0x00 PkgLength This patch adds these FieldElement opcodes definitions to the list of AML Opcode definitions. Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* MdePkg/UefiScsiLib: Set FUA bit for synchronous SCSI Write operationsZurcher, Christopher J2020-04-152-7/+15
| | | | | | | | | | | | | | The FUA (Force Unit Access) bit forces data to be written directly to disk instead of the write cache. This prevents data from being lost if a shutdown or reset is requested immediately after a SCSI write operation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Christopher J Zurcher <christopher.j.zurcher@intel.com>
* MdePkg DebugLib: Enable FILE NAME as DEBUG ASSERT for CLANGZhiguang Liu2020-04-131-1/+5
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1548 For clang compiler, This change will make the generated image not include the absolute file path. If so, the generated debug image can be reproduced in the different root directory. Also, it will reduce the size of debug image size. To do so, use __FILE_NAME__ macro to replace __FILE__. __FILE_NAME__ is Clang-specific extension that functions similar to __FILE__ but only renders the last path component (the filename) instead of an invocation dependent full path to that file, and __FILE_NAME__ is introduced since clang 9. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: remove PropertiesTable GUIDArd Biesheuvel2020-04-072-34/+0
| | | | | | | | | | | | | Remove the GUID definition that describes the deprecated properties table, which is no longer generated by the DXE core. Link: https://bugzilla.tianocore.org/show_bug.cgi?id=2633 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Acked-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdePkg/DxeServicesLib: Add RISC-V architectureDaniel Schaefer2020-04-031-2/+2
| | | | | | | | | | | | | | BZ:2562: https://bugzilla.tianocore.org/show_bug.cgi?id=2562 Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com>
* MdePkg/Include: Add RISC-V related definitions EDK2 CI.Abner Chang2020-04-031-0/+7
| | | | | | | | | | | | | | | | HTTP/PXE boot RISC-V related definitions for EDK2 CI. BZ:2562: https://bugzilla.tianocore.org/show_bug.cgi?id=2562 Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
* MdeModulePkg: Remove gEfiFormBrowserExProtocolGuid Protocol GuidGuoMinJ2020-03-301-1/+0
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2145 Replace the gEfiFormBrowserExProtocolGuid with gEdkiiFormBrowserExProtocolGuid, remove the unnecessary declaration. Signed-off-by: GuoMinJ <newexplorerj@gmail.com> Acked-by: Hao A Wu <hao.a.wu@intel.com>
* MdePkg/UnitTestBaseLib: Add check for pointer BinDataGuomin Jiang2020-03-271-1/+3
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2531 AllocatePool may fail and BinData may be invalid, check it before use. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Guomin Jiang <guomin.jiang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
* MdePkg/PciExpress40.h: DVSEC definition missingJaveed, Ashraf2020-03-191-0/+28
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598 All registers definition of DVSEC are defined as per the PCI Express Base Specification 4.0 chapter 7.9.6. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Remove FIT table industry standard header file.Siyuan Fu2020-02-141-76/+0
| | | | | | | | | | | | | | Commit c7c964b and dd01704 add header file for FIT table and update MpInitLib to support FIT based microcode shadow operation. There are comments that FIT is Intel specific specification instead of industry standard, which should not be placed in EDK2 MdePkg and UefiCpuPkg. This patch removes the header file added by c7c964b. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add PCCT table signature definitionKrzysztof Koch2020-02-136-1/+36
| | | | | | | | | | | | | | | The Platform Communications Channel Table (PCCT) was defined in: ACPI Specification Version 5.0, Errata A - Published Nov. 13, 2013. Starting from the Acpi50.h header file, there are definitions describing the table but a macro with the table's signature is missing. This patch adds the definition of Platform Communications Channel Table's signature to the relevant ACPI header files. Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseSafeIntLib: Fix VS20xx IA32 link failuresMichael D Kinney2020-02-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=2525 SafeUint64Mult() looks for 64-bit overflows and performs several 32-bit multiples with 64-bit results to check for all possible overflow conditions. IA32 builds using VS20xx with optimizations enabled are producing a reference to the _allmull intrinsic. The fix is to use MultU64x64() instead of '*' for these operations. These are safe because the inputs are guaranteed to have the upper 32-bits clear, which means MultU64x64() can never overflow with those inputs. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add PCI Express 5.0 Header FileFelix Polyudov2020-02-121-0/+136
| | | | | | | | The header includes Physical Layer PCI Express Extended Capability definitions based on section 7.7.6 of PCI Express Base Specification 5.0. Signed-off-by: Felix Polyudov <felixp@ami.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Disable EBC for unit tests in MdePkg.dscMichael D Kinney2020-02-111-0/+1
| | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=2514 Update the target unit tests in MdePkg.dsc to only build for IA32, X64, ARM, AARCH64. This disables EBC for these components. The UnitTestLib class uses vararg macros that the EBC compiler does not support. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bret Barkelew <Bret.Barkelew@microsoft.com>
* MdePkg/SmBios.h: Add two additional DWORD for smbios 3.3.0 type17Matthew Carlson2020-02-111-0/+5
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2482 Refer to DSP0134_3.3.0.pdf, there are two additional DWORD added for type 17. One is "Extended Speed", the other is "Extended Configured Memory Speed". The lack of these field may cause strange error in some operating systems. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Register: Fix various typosAntoine Coeur2020-02-106-9/+9
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-29-philmd@redhat.com>
* MdePkg/Ppi: Fix various typosAntoine Coeur2020-02-1011-13/+13
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-28-philmd@redhat.com>
* MdePkg/Library/Smm: Fix various typosAntoine Coeur2020-02-108-36/+36
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-27-philmd@redhat.com>
* MdePkg/Library/Pci: Fix various typosAntoine Coeur2020-02-106-11/+11
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-26-philmd@redhat.com>
* MdePkg/Library/Dxe: Fix various typosAntoine Coeur2020-02-1010-21/+21
| | | | | | | | | | | | | | Fix various typos in documentation, comments and strings, and remove the duplicated 'the'. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-25-philmd@redhat.com>
* MdePkg/IndustryStandard: Fix various typosAntoine Coeur2020-02-1019-65/+65
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-24-philmd@redhat.com>
* MdePkg/Test: Add SafeIntLib and BaseLib Base64 unit testsMichael D Kinney2020-02-0716-3/+5034
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=2505 * Add unit tests for SafeIntLib class * Add unit tests for BaseLib Base64 conversion APIs. * Add Test/MdePkgHostTest.dsc -to build host based unit tests * Update MdePkg.dsc to build target based tests for SafeIntLib and BaseLib * Update MdePkg.ci.yaml to build and run host based tests for SafeIntLib and BaseLib Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Bret Barkelew <Bret.Barkelew@microsoft.com>
* MdePkg/Include/Library: Add UnitTestLib classBret Barkelew2020-02-072-0/+761
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=2505 Add UnitTestLib class to MdePkg that provides services and macros to implement unit tests. These services and macros support the following features: * Create a Unit Test Framework * Add a Unit Test Suite to a Unit Test Framework + Support optional step that executes before a Unit Test Suite is started. + Support optional step that executes after a Unit Test Suite is finished. * Add a Unit Test to a Unit Test Suite + Support optional step that executes before a Unit Test is started. + Support optional step that executes after a Unit Test is finished. * Run all unit tests added to a Unit Test Framework * Save Unit Test Framework state to persistent storage * Support assertion checks in a unit test for TRUE, FALSE, EQUAL, MEM_EQUAL, NOT_EFI_ERROR, STATUS_EQUAL, and NOT_NULL. * Support generation of log messages at ERROR, WARN, INFO, and VERBOSE levels. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdePkg Base.h: Use correct style to check macro _MSC_VER valueLiming Gao2020-02-063-3/+3
| | | | | Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Avoid using __clang__ to specify CLANGPDBLiu, Zhiguang2020-02-061-1/+1
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2415 Avoid using __clang__ to specify CLANGPDB because this macro is also defined in CLANG38 and this causes CLANG38 build failure. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add definition for Fmp Capsule Dependency.Xu, Wei62020-01-192-11/+43
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2421 Add new definitions for Fmp Capsule dependency in UEFI Spec 2.8. 1. Extend the Last Attempt Status with a value to indicate the firmware update fails with unsatisfied dependencies. 2. Add the definition of dependency expression op-codes. 3. Add the definition of EFI_FIRMWARE_IMAGE_DEP which is an array of FMP dependency expression op-codes. 4. Extend the EFI_FIRMWARE_IMAGE_DESCRIPTOR with a pointer to the array of FMP dependency expression op-codes. 5. Extend the Image Attribute Definitions with IMAGE_ATTRIBUTE_DEPENDENCY to indicate that there is and EFI_FIRMWARE_IMAGE_DEP section associated with the image. 6. Update EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION to 4. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg Base.h: Use correct style to check the defined macroLiming Gao2020-01-171-2/+2
| | | | | | | | #if MACRO is not good style. It should be changed to #ifdef MACRO style or #if defined (MACRO) style. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Add header file for Firmware Interface Table specification.Siyuan Fu2020-01-101-0/+76
| | | | | | | | | | | | | | | | This patch add FirmwareInterfaceTable.h for the Firmware Interface Table BIOS specification. This is to remove future edk2 dependency on edk2-platforms repo. The file content comes from edk2-platforms\Silicon\Intel\IntelSiliconPkg\Include\IndustryStandard BZ link: https://tianocore.acgmultimedia.com/show_bug.cgi?id=2449 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg BaseLib.h: Update IA32_CR4 strut to include all public fieldsJason Voelz2020-01-101-3/+12
| | | | | | | | | Based on Intel Software Develeper's Manual, add all fields in IA32_CR4. Signed-off-by: Jason Voelz <jason.voelz@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg: Do not use CreateEventEx unless requiredVitaly Cheptsov via Groups.Io2020-01-1014-47/+15
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2446 There are many firmwares in the wild not supporting CreateEventEx, including devices less than 5 years old. Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Tcg: Add new definition in TCG PFP spec.Jiewen Yao2019-12-201-9/+173
| | | | | | | | | | | The latest TCG PFP specification (TCG PC Client Platform Firmware Profile Specification, Revision 1.05) added new data structure. For example, the SPDM device measurement. This patch adds the new content. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Use __builtin_offset with CLANGPDB toolchainAlex James2019-12-201-3/+1
| | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2393 CLANGPDB does not define __GNUC__, but it does define __clang__. Check for the __clang__ preprocessor definition to use __builtin_offsetof to implement the OFFSET_OF macro. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Alex James <theracermaster@gmail.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg PciExpress21: PCI_REG_PCIE_DEVICE_CONTROL2 struct has 17 bitsDaniel Pawel Banaszek2019-12-191-1/+1
| | | | | | | | | Device Control 2 Structure have an issue. LtrMechanism - there is 2 bits instead of 1. Signed-off-by: Daniel Pawel Banaszek <daniel.pawel.banaszek@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/Spdm: fix Nonce structure error.Jiewen Yao2019-12-191-5/+5
| | | | | | | | | | Align to SPDM 1.0.0 specification. Fix Nonce data structure error. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include: Add DCC and BCM2835 SPCR UART typesPete Batard2019-12-121-0/+10
| | | | | | | | | | | | | | | | As per the Microsoft Debug Port Table 2 (DBG2) documentation, that can be found online, we are missing 2 serial interface types for Arm DCC and Bcm2835 (the latter being used with the Raspberry Pi). These same types are present in DebugPort2Table.h so add them to SerialPortConsoleRedirectionTable.h too. Note that we followed the same idiosyncrasies as DebugPort2Table for naming these new macros. Signed-off-by: Pete Batard <pete@akeo.ie> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Update the comments of IsLanguageSupportedShenglei Zhang2019-11-202-18/+19
| | | | | | | | | | Keep the comment style of IsLanguageSupported align with other functions. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 Update Intel Persistent Memory stringGao, Zhichao2019-11-141-0/+4
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Memory Device (Type 17): - SMBIOSCR00179: update the string for Intel persistent memory Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 Add value HBM and Die for type 17Gao, Zhichao2019-11-141-2/+5
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Memory Device (Type 17): - SMBIOSCR00178: add new memory device type value (HBM) and new form factor value (Die) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 add support for CXL FlexbusGao, Zhichao2019-11-141-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 Various: - SMBIOSCR00183: add support for CXL Flexbus Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg/SmBios.h: SMBIOS 3.3.0 add PCI gen4 values for type 9Gao, Zhichao2019-11-141-2/+8
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305 System Slots (Type 9): - SMBIOSCR00184: add PCI Express Gen 4 values Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 02:39:13 +0000