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* MdePkg/Include: Rename _DEBUG() to address name collisionMichael D Kinney2024-02-141-3/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4683 When VS20xx host-based unit tests are built with debug libraries a name collision occurs with the DebugLib.h internal macro _DEBUG(). Rename this internal macro to _DEBUGLIB_DEBUG() to address the name collision. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: Add EFI_UNSUPPORTED return for some Runtime Service functionsSuqiang Ren2024-02-093-11/+122
| | | | | | | | | | | | | | | | | According to UEFI Spec 2.10 page 206, if any EFI_RUNTIME_SERVICES* calls are not supported for use by the OS at runtime, an EFI_RT_PROPERTIES_TABLE configuration table should be published describing which runtime services are supported at runtime. So need to add EFI_UNSUPPORTED return for some Runtime Service functions. REF: UEFI spec 2.10 section 8 Services ? Runtime Services Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add SynchronizationLib to MdeLibs.dsc.incMichael D Kinney2024-02-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4675 Add library mapping for the SynchronizationLib to MdeLibs.dsc.inc to resolve build failures in the FmpDevicePkg and NetworkPkg for missing library mapping. The following email details why this was missed by EDK II CI * https://edk2.groups.io/g/devel/message/115185 Local builds of all packages that use -D CONTINUOUS_INTEGRATION were performed to verify that this change resolves the missing library mapping. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: Test: Add gRT_GetTime Google Test MockDoug Flick via groups.io2024-02-062-2/+10
| | | | | | | | | | | This adds support for GetTime Google Test Mock Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add some comments for LoongArch exceptionsChao Li2024-02-061-0/+14
| | | | | | | | | | | | Added some comments for registing LoongArch exceptions. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add a new library named PeiServicesTablePointerLibKs0Chao Li2024-02-065-4/+152
| | | | | | | | | | | | | | | | | | Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides setting and getting the PEI service table pointer through the CSR KS0 register. The idea of this library is derived from ArmPkg/Library/PeiServicesTablePointerLib/ BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add IOCSR operation for LoongArchChao Li2024-02-063-0/+233
| | | | | | | | | | | | | | | Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8, IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR registers of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add CSR operation for LoongArchChao Li2024-02-064-0/+550
| | | | | | | | | | | | | | | Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them to operate the CSR register of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add read stable counter operation for LoongArchChao Li2024-02-063-0/+37
| | | | | | | | | | | | | Add LoongArch gets stable counter ASM function. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch Cpucfg functionChao Li2024-02-065-1/+606
| | | | | | | | | | | | | | | | Add LoongArch AsmCpucfg function and Cpucfg definitions. Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of EccCheck. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 local interrupt function set into BaseLibChao Li2024-02-063-10/+54
| | | | | | | | | | | | | | | Adding LoongArch local interrupt function set, which is used to control the opening or closing of the local interrupt when the global interrupt is enabled. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 exception function set into BaseLibChao Li2024-02-063-0/+62
| | | | | | | | | | | | | | Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 FPU function set into BaseCpuLibChao Li2024-02-065-7/+128
| | | | | | | | | | | | | | Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and DisableFloatingPointUnits functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add the header file named Csr.h for LoongArch64Chao Li2024-02-061-0/+263
| | | | | | | | | | | | | Adding Csr.h for LoongArch64, it is use for accessing the CSR registers. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Adds AMD Extended CPU topology CPUIDAbdul Lateef Attar2024-01-311-1/+22
| | | | | | | | | | | | | | | | Adds cpuid macro for AMD extended CPU topology. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Message-Id: <15199aaefbc497bb1ea7b20028c13ebedd8c488b.1705549445.git.AbdulLateef.Attar@amd.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
* MdePkg/Library/BaseCpuLibNull: Add missing X86 specific servicesMichael D Kinney2024-01-273-15/+69
| | | | | | | | | | | | | | | | * Add InitializeFloatingPointUnits() to x86 specific file * Add GetCpuFamilyModel() to x86 specific file * Add GetCpuSteppingId() to x86 specific file * Move StandardSignatureIsAuthenticAMD() to x86 specific file. * Add CpuLib library class include to all C files. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Qing Huang <qing.huang@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Add EFI_BROWSER_ACTION_REQUEST_QUESTION_APPLYMing Tan2024-01-241-0/+1
| | | | | | | | | | | | | | | REF: UEFI_Spec_2_10_Aug29.pdf page 1694 In 35.5.4 EFI_HII_CONFIG_ACCESS_PROTOCOL.CallBack() parameter ActionRequest, add EFI_BROWSER_ACTION_REQUEST_QUESTION_APPLY. Signed-off-by: Ming Tan <ming.tan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add FdtLib gmock supportdevel@edk2.groups.io2024-01-244-0/+227
| | | | | | | | | | | Add Google Mock Library for FdtLib Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com>
* MdePkg/BaseFdtLib: Rename standard functionsJeff Brasen2024-01-242-25/+7
| | | | | | | | | | | Rename the standard functions in the LibFdtSupport to remove conflicts with other libraries that define them. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Library/BaseCpuLibNull: Add StandardSignatureIsAuthenticAMD()devel@edk2.groups.io2024-01-231-0/+15
| | | | | | | | | | | | CpuLib.h exposes StandardSignatureIsAuthenticAMD() API and we require stub function in its BaseCpuLibNull library instance to avoid potential link issue. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Qing Huang <qing.huang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include/Guid: Update the definition of FileName in EFI_FILE_INFOSuqiang Ren2024-01-231-0/+1
| | | | | | | | | | | Add the description of EFI_FILE_INFO FileName[1] field to align with UEFI spec 2.10 Section 13.5.16. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Library/BaseIoLibIntrinsic: Fix TD MMIO read type castZhiquan Li2024-01-201-3/+3
| | | | | | | | | | | Currently the types of casting mismatch with TD MMIO read 1, 2 and 4 bytes, that might introduce potential issues. So fix the types as conventional MmioRead[8|16|32] does. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiquan Li <zhiquan1.li@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/IndustryStandard: Add _PSD/_CPC/Coord types definitionsPierre Gondois2024-01-2010-0/+99
| | | | | | | | | | | Add definitions for: - _PSD version: added in ACPI 3.0 - C-state Coordination Types: added in ACPI 3.0 - _CPC version: added in ACPI 5.0 Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add DECLARE_LENGTH opcode of dependency expressionYi Li2024-01-191-14/+15
| | | | | | | | | | | | | | | | | | To avoid messy parsing of the Depex section of a Capsule, it would be a lot easier for everyone involved if we preceded the Capsule Depex Section with a length declaration. It provides simple bounds checking to avoid having to parse the op-codes, but in the case of a malformed depex being parsed, avoid other issues which can be messy. REF: UEFI spec 2.10 Table 23.4 Signed-off-by: Yi Li <yi1.li@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the Label definitions of the EFI_NVDIMM_LABELJunfeng Guan2024-01-161-1/+15
| | | | | | | | | | | Refer to Uefi spec 2.10 section 13.19.5, update the label definitions for NVDIMM SPA location cookie. Signed-off-by: Junfeng Guan <junfengx.guan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: RFC1323 definition changed to RFC7323Suqiang Ren2024-01-161-2/+2
| | | | | | | | | | | | | Change the description of RFC1323 to RFC7323 to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 28.2.5 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the comments of callback in EFI_FORM_BROWSER2_PROTOCOLSuqiang Ren2024-01-151-1/+4
| | | | | | | | | | | | | | Add status code return for BROWSER callback in EFI_FORM_BROWSER2_PROTOCOL to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 35.6.3 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Felix Polyudov <felixp@ami.com>
* MdePkg: Update the comments of HiiConfigAccess ExtractConfigSuqiang Ren2024-01-151-1/+8
| | | | | | | | | | | | | Add the status code return for HiiConfigAccess ExtractConfig to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 35.5.2 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix boot DxeCore hang on riscv platform王洋2024-01-113-7/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | For scene of HandOffToDxeCore()->SwitchStack(DxeCoreEntryPoint)-> InternalSwitchStack()->LongJump(),Variable HobList.Raw will be passed (from *Context1 to register a0) to DxeMain() in parameter *HobStart. However, meanwhile the function LongJump() overrides register a0 with a1 (-1) due to commit (ea628f28e5 "RISCV: Fix InternalLongJump to return correct value"), then cause hang. Replacing calling LongJump() with new InternalSwitchStackAsm() to pass addres data in register s0 to register a0 could fix this issue (just like the solution in MdePkg/Library/BaseLib/AArch64/SwitchStack.S) Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Cc: Bamvor Jian ZHANG <zhangjian@bosc.ac.cn> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ran Wang <wangran@bosc.ac.cn> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg/BaseLib: RISC-V: Add function to update stimecmp registerSunil V L2024-01-113-0/+15
| | | | | | | | | | | | | | stimecmp is a CSR supported only when Sstc extension is supported by the platform. This register can be used to set the timer interrupt directly in S-mode instead of going via SBI call. Add a function to update this register. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg.dec: RISC-V: Define override bit for Sstc extensionSunil V L2024-01-111-0/+2
| | | | | | | | | | | | | Define the BIT 1 as the override bit for Sstc extension. This will be used by the timer driver to decide whether to use SBI calls or direct CSR access to configure the timer. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: Update GetHealthStatus function descriptionJunfeng Guan2024-01-111-24/+8
| | | | | | | | | | | Refer to Uefi spec 2.10 section 11.10.2, update the return value for EFI_DRIVER_HEALTH_PROTOCOL.GetHealthStatus. Signed-off-by: Junfeng Guan <junfengx.guan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the definition of EFI_NVDIMM_LABEL_FLAGS_LOCALSuqiang Ren2024-01-091-0/+2
| | | | | | | | | | | | | Add the description of EFI_NVDIMM_LABEL_FLAGS_LOCAL to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 13.19.4 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Update the definition of CapsuleImageSize on EFI_CAPSULE_HEADERSuqiang Ren2024-01-081-1/+1
| | | | | | | | | | | | | Add the description of CapsuleImageSize to align with UEFI spec 2.10. REF: UEFI spec 2.10 section 8.5.3.1 Signed-off-by: Suqiang Ren <suqiangx.ren@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Felix Polyudov <felixp@ami.com>
* MdePkg/MdeLibs.dsc.inc: Add SafeIntLib instanceJiaxin Wu2023-12-201-0/+1
| | | | | | | | | | | | | This patch is to add SafeIntLib in MdeLibs.dsc.inc Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Utilize Cache Management Operations Implementation For RISC-VDhaval Sharma2023-12-194-28/+165
| | | | | | | | | | | | | | | | Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Implement RISC-V Cache Management OperationsDhaval2023-12-194-1/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Sunil V L <sunilvl@...> Reviewed-by: Jingyu Li <jingyu.li01@...>
* MdePkg: Rename Cache Management Function To Clarify Fence Based OpDhaval2023-12-193-8/+8
| | | | | | | | | | | | | | | | | | | | There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Move RISC-V Cache Management Declarations Into BaseLibDhaval Sharma2023-12-192-20/+20
| | | | | | | | | | | | | | | The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg:simplify Fifo API in BaseIoLibIntrinsicDun Tan2023-12-114-259/+222
| | | | | | | | | | | | | | | | | | Simplify IoRead/WriteFifo implement by repeatedly calling IoRead/Write in the C code. This can avoid calling assembly code to use string I/O instructions. With this change Ia32/IoFifo.nasm and X64/IoFifo.nasm can be removed. Then the source files for IA32 and X64 are the same. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Change IoLibFifo.c to IoLibFifoCc.cDun Tan2023-12-112-2/+2
| | | | | | | | | | | | | | | | Change IoLibFifo.c to IoLibFifoCc.c since the file is for Tdx and SEV in BaseIoLibIntrinsicSev. It's also to distinguish with a new incoming IoLibFifo.c for BaseIoLibIntrinsic. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Update MdePkg.uni with manageability debug levelRebecca Cran2023-12-111-0/+2
| | | | | | | Update MdePkg.uni with the manageability debug level. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add manageability debug level to PcdFixedDebugPrintErrorLevelRebecca Cran2023-12-111-0/+1
| | | | | | | | Update MdePkg.dec to add the manageability debug level to PcdFixedDebugPrintErrorLevel. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Improve wording of manageability debug level commentRebecca Cran2023-12-111-2/+2
| | | | | | | | Improve the wording of the comment explaining the DEBUG_MANAGEABILITY debug level. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add UEFI v2.10 ISA memory type definitionManickamX Srinivasan2023-12-091-0/+15
| | | | | | | | | | | | New memory type as defined in UEFI standard v2.10 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: T V Krishnamoorthy <krishnamoorthy.t.v@intel.com> Signed-off-by: ManickamX Srinivasan <manickamx.srinivasan@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Define the DevicePath argument from LoadImage as optionalManickamX Srinivasan2023-12-081-1/+1
| | | | | | | | | | | | | Update the EFI LoadImage API in accordance with the UEFI v2.10 specification. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: T V Krishnamoorthy <krishnamoorthy.t.v@intel.com> Signed-off-by: ManickamX Srinivasan <manickamx.srinivasan@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* BaseStackCheckLib: Fix STACK FAULT messageJake Garver2023-12-061-1/+2
| | | | | | | | __builtin_return_address returns a pointer, not a string. Fix the STACK FAULT message in BaseStackCheckLib appropriately. Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg:Add NVME Sanitize command support to Nvme.hTina Chen2023-12-051-11/+110
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4591 1. Refer NVME spec 2.0c chapter 5.24, add Sanitize Command related definition. 2. Refer NVME spec 2.0c chapter 5.16, add Get Log Page Command related definition for Sanitize status support. Cc: Ray Ni <ray.ni@intel.com> Cc: Xiao X Chen <xiao.x.chen@intel.com> Cc: Arthur Chen <arthur.g.chen@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Tina Chen <tina.chen@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Test: Add google tests for BaseLibPedro Falcato2023-12-034-0/+118
| | | | | | | | | | | | Add GoogleTestBaseLib, which contains gtest unit tests for BaseLib. For now, only add checksum tests for CRC32C and CRC16; these tests check for correctness on various inputs using precomputed hashes. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: Fix CRC16-ANSI calculationPedro Falcato2023-12-032-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4609 The current CalculateCrc16Ansi implementation does the following: 1) Invert the passed checksum 2) Calculate the new checksum by going through data and using the lookup table 3) Invert it back again This emulated my design for CalculateCrc32c, where 0 is passed as the initial checksum, and it inverts in the end. However, CRC16 does not invert the checksum on input and output. So this is incorrect. Fix the problem by not inverting input checksums nor output checksums. Callers should now pass CRC16ANSI_INIT as the initial value instead of "0". This is a breaking change. This problem was found out-of-list when older ext4 filesystems (that use crc16 checksums) failed to mount with "corruption". Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 23:52:55 +0000