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* OvmfPkg/PlatformPei: log pei memory cap detailsGerd Hoffmann2024-02-271-0/+24
| | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240214104504.2931339-5-kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/PlatformPei: rewrite page table calculationGerd Hoffmann2024-02-271-22/+36
| | | | | | | | | Consider 5-level paging. Simplify calculation to make it easier to understand. Add some comments, improve ASSERTs. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240214104504.2931339-4-kraxel@redhat.com>
* OvmfPkg/PlatformPei: consider AP stacks for pei memory capGerd Hoffmann2024-02-271-3/+14
| | | | | | | | | Needed to avoid running out of memory when booting with a large (~2048) number of vcpus. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240214104504.2931339-3-kraxel@redhat.com>
* OvmfPkg/PlatformPei: log a warning when memory is tightGerd Hoffmann2024-02-271-0/+8
| | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240214104504.2931339-2-kraxel@redhat.com>
* OvmfPkg: remove PcdCsmEnableLaszlo Ersek2023-12-071-23/+13
| | | | | | | | | | | | | | | | | | | | | | | | | PcdCsmEnable was introduced in commits 50f911d25d39 ("OvmfPkg: introduce PcdCsmEnable feature flag", 2020-02-05) and 75839f977d37 ("OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (for real)", 2020-02-05). Remove it, and substitute constant FALSE wherever it has been evaluated thus far. Regression test: after building OVMF IA32X64 with -D SMM_REQUIRE, and booting it on Q35, the log still contains > Q35SmramAtDefaultSmbaseInitialization: SMRAM at default SMBASE found Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> https://bugzilla.tianocore.org/show_bug.cgi?id=4588 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20231110235820.644381-3-lersek@redhat.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Corvin Köhne <corvink@FreeBSD.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg: Update code to be more C11 compliant by using __func__Rebecca Cran2023-04-101-6/+6
| | | | | | | | | | | | | __FUNCTION__ is a pre-standard extension that gcc and Visual C++ among others support, while __func__ was standardized in C99. Since it's more standard, replace __FUNCTION__ with __func__ throughout OvmfPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* OvmfPkg/PlatformInitLib: Add PlatformGetLowMemoryCBGerd Hoffmann2023-01-171-1/+2
| | | | | | | | | | | | | | | | | Add PlatformGetLowMemoryCB() callback function for use with PlatformScanE820(). It stores the low memory size in PlatformInfoHob->LowMemory. This replaces calls to PlatformScanOrAdd64BitE820Ram() with non-NULL LowMemory. Write any actions done (setting LowMemory) to the firmware log with INFO loglevel. Also change PlatformGetSystemMemorySizeBelow4gb() to likewise set PlatformInfoHob->LowMemory instead of returning the value. Update all Callers to the new convention. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/PlatformPei: PeiMemory: stop using mPlatformInfoHobGerd Hoffmann2022-12-141-18/+18
| | | | | | | | | | Stop using the mPlatformInfoHob global variable in PublishPeiMemory() and GetPeiMemoryCap() functions. Pass a pointer to the PlatformInfoHob instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/PlatformPei Q35 SMM helpers: stop using mPlatformInfoHobGerd Hoffmann2022-12-141-10/+10
| | | | | | | | | | | Stop using the mPlatformInfoHob global variable in Q35TsegMbytesInitialization() and Q35SmramAtDefaultSmbaseInitialization() ) functions. Pass a pointer to the PlatformInfoHob instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg: Update PlatformPei to support Tdx guestMin Xu2022-04-021-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 OvmfPkg/PlatformPei is updated to support Tdx guest. There are below major changes. - Set Tdx related PCDs - Publish Tdx RamRegions In this patch there is another new function BuildPlatformInfoHob (). This function builds EFI_HOB_PLATFORM_INFO which contains the HostBridgeDevId. The hob is built in both Td guest and Non-Td guest. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/PlatformInitLib: Create MemDetect.cMin Xu2022-04-021-803/+1
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 Move functions in PlatformPei\MemDetect.c to PlatformInitLib\MemDetect.c. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/PlatformPei: Refactor InitializeRamRegionsMin Xu2022-04-021-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 InitializeRamRegions is refactored into 3 calls: - PlatformQemuInitializeRam - SevInitializeRam - PlatformQemuInitializeRamForS3 SevInitializeRam is not in PlatformInitLib. Because in the first stage PlatformInitLib only support the basic platform featues. PlatformQemuInitializeRamForS3 wraps the code which was previously in InitializeRamRegions (many code in 2 if-checks). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/PlatformPei: Refactor QemuUc32BaseInitializationMin Xu2022-04-021-1/+2
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 Rename QemuUc32BaseInitialization to PlatformQemuUc32BaseInitialization. This function is for PlatformInitLib. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/PlatformPei: Refactor AddressWidthInitializationMin Xu2022-04-021-43/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 From this patch we start to restruct the functions which set PCDs into two, one for PlatformInitLib, one for PlatformPei. AddressWidthInitialization is the first one. It is splitted into two: - PlatformAddressWidthInitialization is for PlatformInitLib - AddressWidthInitialization is for PlatformPei. It calls PlatformAddressWidthInitialization then set PCDs. Below functions are also refined for PlatformInitLib: - PlatformScanOrAdd64BitE820Ram - PlatformGetSystemMemorySizeAbove4gb - PlatformGetFirstNonAddress All the SetPcd codes are removed from above functions. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/PlatformPei: Move global variables to PlatformInfoHobMin Xu2022-04-021-106/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 The intention of PlatformInitLib is to extract the common function used in OvmfPkg/PlatformPei. This lib will be used not only in PEI phase but also in SEC phase. SEC phase cannot use global variables between different functions. So PlatformInfoHob is created to hold the informations shared between functions. For example, HostBridgeDevId corespond to mHostBridgeDevId in PlatformPei. In this patch we will first move below global variables to PlatformInfoHob. - mBootMode - mS3Supported - mPhysMemAddressWidth - mMaxCpuCount - mHostBridgeDevId - mQ35SmramAtDefaultSmbase - mQemuUc32Base - mS3AcpiReservedMemorySize - mS3AcpiReservedMemoryBase PlatformInfoHob also holds other information, for example, PciIoBase / PciIoSize. This is because in SEC phase, PcdSetxxx doesn't work. So we will restruct the functions which set PCDs into two, one for PlatformInfoLib, one for PlatformPei. So in this patch we first move global variables and PCDs to PlatformInfoHob. All the changes are in OvmfPkg/PlatformPei. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/PlatformInitLib: Add hob functionsMin Xu2022-04-021-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 In this patch of PlatformInitLib, below hob functions are introduced: - PlatformAddIoMemoryBaseSizeHob - PlatformAddIoMemoryRangeHob - PlatformAddMemoryBaseSizeHob - PlatformAddMemoryRangeHob - PlatformAddReservedMemoryBaseSizeHob They correspond the below functions in OvmfPkg/PlatformPei: - AddIoMemoryBaseSizeHob - AddIoMemoryRangeHob - AddMemoryBaseSizeHob - AddMemoryRangeHob - AddReservedMemoryBaseSizeHob After above hob functions are introduced in PlatformInitLib, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg: Create initial version of PlatformInitLibMin Xu2022-04-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 There are 3 variants of PlatformPei in OvmfPkg: - OvmfPkg/PlatformPei - OvmfPkg/XenPlatformPei - OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf These PlatformPeis can share many common codes, such as Cmos / Hob / Memory / Platform related functions. This commit (and its following several patches) are to create a PlatformInitLib which wraps the common code called in above PlatformPeis. In this initial version of PlatformInitLib, below Cmos related functions are introduced: - PlatformCmosRead8 - PlatformCmosWrite8 - PlatformDebugDumpCmos They correspond to the functions in OvmfPkg/PlatformPei: - CmosRead8 - CmosWrite8 - DebugDumpCmos Considering this PlatformInitLib will be used in SEC phase, global variables and dynamic PCDs are avoided. We use PlatformInfoHob to exchange information between functions. EFI_HOB_PLATFORM_INFO is the data struct which contains the platform information, such as HostBridgeDevId, BootMode, S3Supported, SmmSmramRequire, etc. After PlatformInitLib is created, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg: CloudHv: Rely on PVH memmap instead of CMOSSebastien Boeuf2022-03-041-0/+73
| | | | | | | | | | Instead of using the CMOS, the CloudHv platform relies on the list of memmap entries provided through the PVH boot protocol to determine the last RAM address below 4G. Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg/PlatformPei: Revert "stop using cmos for memory detection"Ard Biesheuvel2021-12-151-4/+55
| | | | | | | | This reverts commit 41d8bb30386ceab55787fc9f5aac6434e2493e27, as it breaks Cloud Hypervisor. Reported-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/PlatformPei: stop using cmos for memory detectionGerd Hoffmann2021-12-131-55/+4
| | | | | | | | Not needed for qemu 1.7 (released in 2013) and newer. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3593 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/PlatformPei: prefer etc/e820 for memory detectionGerd Hoffmann2021-12-131-5/+14
| | | | | | | | | | Prefer the e820 map provided via qemu firmware config interface for memory detection. Use rtc cmos only as fallback, which should be rarely needed these days as qemu supports etc/e820 since 2013. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3593 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* OvmfPkg/PlatformPei: ScanOrAdd64BitE820Ram improvementsGerd Hoffmann2021-12-131-8/+24
| | | | | | | | | | | | | | | | | | Add a bool parameter to ScanOrAdd64BitE820Ram to explicitly specify whenever ScanOrAdd64BitE820Ram should add HOBs for high memory (above 4G) or scan only. Also add a lowmem parameter so ScanOrAdd64BitE820Ram can report the memory size below 4G. This allows a more flexible usage of ScanOrAdd64BitE820Ram, a followup patch will use it for all memory detection. No functional change. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3593 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* OvmfPkg: Handle Cloud Hypervisor host bridgeSebastien Boeuf2021-12-111-1/+8
| | | | | | | | | | Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Rob Bradford <robert.bradford@intel.com> Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
* OvmfPkg/PlatformPei: mark cpuid and secrets memory reserved in EFI mapBrijesh Singh via groups.io2021-12-091-0/+2
| | | | | | | | | | | | | | | | | | | When SEV-SNP is active, the CPUID and Secrets memory range contains the information that is used during the VM boot. The content need to be persist across the kexec boot. Mark the memory range as Reserved in the EFI map so that guest OS or firmware does not use the range as a system RAM. Cc: Michael Roth <michael.roth@amd.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
* OvmfPkg: Apply uncrustify changesMichael Kubacki2021-12-071-151/+203
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the OvmfPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
* OvmfPkg/Microvm: PlatformPei/MemDetect tweaksGerd Hoffmann2021-10-051-0/+4
| | | | | | | | Skip host bridge setup on microvm. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3599 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg: introduce a common work areaBrijesh Singh2021-08-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Both the TDX and SEV support needs to reserve a page in MEMFD as a work area. The page will contain meta data specific to the guest type. Currently, the SEV-ES support reserves a page in MEMFD (PcdSevEsWorkArea) for the work area. This page can be reused as a TDX work area when Intel TDX is enabled. Based on the discussion [1], it was agreed to rename the SevEsWorkArea to the OvmfWorkArea, and add a header that can be used to indicate the work area type. [1] https://edk2.groups.io/g/devel/message/78262?p=,,,20,0,0,0::\ created,0,SNP,20,2,0,84476064 Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/PlatformPei: remove Xen supportLaszlo Ersek2021-06-041-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "OvmfPkg/PlatformPei/PlatformPei.inf" module is used by the following platform DSCs: OvmfPkg/AmdSev/AmdSevX64.dsc OvmfPkg/OvmfPkgIa32.dsc OvmfPkg/OvmfPkgIa32X64.dsc OvmfPkg/OvmfPkgX64.dsc Remove Xen support from "OvmfPkg/PlatformPei", including any dependencies that now become unused. The basic idea is to substitute FALSE for "mXen". Remove "OvmfPkg/PlatformPei" from the "OvmfPkg: Xen-related modules" section of "Maintainers.txt". This patch is best reviewed with "git show -b -W". Cc: Andrew Fish <afish@apple.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210526201446.12554-22-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* OvmfPkg/PlatformPei: Reserve GHCB backup pages if S3 is supportedTom Lendacky2021-01-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3108 Protect the GHCB backup pages used by an SEV-ES guest when S3 is supported. Regarding the lifecycle of the GHCB backup pages: PcdOvmfSecGhcbBackupBase (a) when and how it is initialized after first boot of the VM If SEV-ES is enabled, the GHCB backup pages are initialized when a nested #VC is received during the SEC phase [OvmfPkg/Library/VmgExitLib/SecVmgExitVcHandler.c]. (b) how it is protected from memory allocations during DXE If S3 and SEV-ES are enabled, then InitializeRamRegions() [OvmfPkg/PlatformPei/MemDetect.c] protects the ranges with an AcpiNVS memory allocation HOB, in PEI. If S3 is disabled, then these ranges are not protected. PEI switches to the GHCB backup pages in permanent PEI memory and DXE will use these PEI GHCB backup pages, so we don't have to preserve PcdOvmfSecGhcbBackupBase. (c) how it is protected from the OS If S3 is enabled, then (b) reserves it from the OS too. If S3 is disabled, then the range needs no protection. (d) how it is accessed on the S3 resume path It is rewritten same as in (a), which is fine because (b) reserved it. (e) how it is accessed on the warm reset path It is rewritten same as in (a). Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Julien Grall <julien@xen.org> Cc: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <119102a3d14caa70d81aee334a2e0f3f925e1a60.1610045305.git.thomas.lendacky@amd.com>
* OvmfPkg/PlatformPei: Reserve SEV-ES work area if S3 is supportedTom Lendacky2020-08-171-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Protect the SEV-ES work area memory used by an SEV-ES guest. Regarding the lifecycle of the SEV-ES memory area: PcdSevEsWorkArea (a) when and how it is initialized after first boot of the VM If SEV-ES is enabled, the SEV-ES area is initialized during the SEC phase [OvmfPkg/ResetVector/Ia32/PageTables64.asm]. (b) how it is protected from memory allocations during DXE If SEV-ES is enabled, then InitializeRamRegions() [OvmfPkg/PlatformPei/MemDetect.c] protects the ranges with either an AcpiNVS (S3 enabled) or BootServicesData (S3 disabled) memory allocation HOB, in PEI. (c) how it is protected from the OS If S3 is enabled, then (b) reserves it from the OS too. If S3 is disabled, then the range needs no protection. (d) how it is accessed on the S3 resume path It is rewritten same as in (a), which is fine because (b) reserved it. (e) how it is accessed on the warm reset path It is rewritten same as in (a). Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Julien Grall <julien@xen.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/PlatformPei: Reserve GHCB-related areas if S3 is supportedTom Lendacky2020-08-171-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Protect the memory used by an SEV-ES guest when S3 is supported. This includes the page table used to break down the 2MB page that contains the GHCB so that it can be marked un-encrypted, as well as the GHCB area. Regarding the lifecycle of the GHCB-related memory areas: PcdOvmfSecGhcbPageTableBase PcdOvmfSecGhcbBase (a) when and how it is initialized after first boot of the VM If SEV-ES is enabled, the GHCB-related areas are initialized during the SEC phase [OvmfPkg/ResetVector/Ia32/PageTables64.asm]. (b) how it is protected from memory allocations during DXE If S3 and SEV-ES are enabled, then InitializeRamRegions() [OvmfPkg/PlatformPei/MemDetect.c] protects the ranges with an AcpiNVS memory allocation HOB, in PEI. If S3 is disabled, then these ranges are not protected. DXE's own page tables are first built while still in PEI (see HandOffToDxeCore() [MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c]). Those tables are located in permanent PEI memory. After CR3 is switched over to them (which occurs before jumping to the DXE core entry point), we don't have to preserve PcdOvmfSecGhcbPageTableBase. PEI switches to GHCB pages in permanent PEI memory and DXE will use these PEI GHCB pages, so we don't have to preserve PcdOvmfSecGhcbBase. (c) how it is protected from the OS If S3 is enabled, then (b) reserves it from the OS too. If S3 is disabled, then the range needs no protection. (d) how it is accessed on the S3 resume path It is rewritten same as in (a), which is fine because (b) reserved it. (e) how it is accessed on the warm reset path It is rewritten same as in (a). Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Julien Grall <julien@xen.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: replace old EFI_D_ debug levels with new DEBUG_ onesRebecca Cran2020-04-301-4/+4
| | | | | | | | | | | | | Generated mechanically with: find OvmfPkg -type f -exec sed -i -e 's/EFI_D_/DEBUG_/g' {} \; Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Cc: Philippe Mathieu-Daude <philmd@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Laszlo Ersek <lersek@redhat.com> Message-Id: <20200429215327.606467-1-rebecca@bsdio.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/PlatformPei: parse "X-PciMmio64Mb" with QemuFwCfgSimpleParserLibLaszlo Ersek2020-04-281-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | Replace the - QemuFwCfgFindFile(), - QemuFwCfgSelectItem(), - QemuFwCfgReadBytes(), - AsciiStrDecimalToUint64() sequence in the GetFirstNonAddress() function with a call to QemuFwCfgSimpleParserLib. This change is compatible with valid strings accepted previously. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Per Sundstrom <per_sundstrom@yahoo.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2681 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20200424075353.8489-3-lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (for real)Laszlo Ersek2020-02-051-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the SMRAM at the default SMBASE is honored everywhere necessary, implement the actual detection. The (simple) steps are described in previous patch "OvmfPkg/IndustryStandard: add MCH_DEFAULT_SMBASE* register macros". Regarding CSM_ENABLE builds: according to the discussion with Jiewen at https://edk2.groups.io/g/devel/message/48082 http://mid.mail-archive.com/74D8A39837DF1E4DA445A8C0B3885C503F7C9D2F@shsmsx102.ccr.corp.intel.com if the platform has SMRAM at the default SMBASE, then we have to (a) either punch a hole in the legacy E820 map as well, in LegacyBiosBuildE820() [OvmfPkg/Csm/LegacyBiosDxe/LegacyBootSupport.c], (b) or document, or programmatically catch, the incompatibility between the "SMRAM at default SMBASE" and "CSM" features. Because CSM is out of scope for the larger "VCPU hotplug with SMM" feature, option (b) applies. Therefore, if the CSM is enabled in the OVMF build, then PlatformPei will not attempt to detect SMRAM at the default SMBASE, at all. This is approach (4) -- the most flexible one, for end-users -- from: http://mid.mail-archive.com/868dcff2-ecaa-e1c6-f018-abe7087d640c@redhat.com https://edk2.groups.io/g/devel/message/48348 Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20200129214412.2361-12-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg/PlatformPei: reserve the SMRAM at the default SMBASE, if it existsLaszlo Ersek2020-02-051-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 128KB SMRAM at the default SMBASE will be used for protecting the initial SMI handler for hot-plugged VCPUs. After platform reset, the SMRAM in question is open (and looks just like RAM). When BDS signals EFI_DXE_MM_READY_TO_LOCK_PROTOCOL (and so TSEG is locked down), we're going to lock the SMRAM at the default SMBASE too. For this, we have to reserve said SMRAM area as early as possible, from components in PEI, DXE, and OS runtime. * QemuInitializeRam() currently produces a single resource descriptor HOB, for exposing the system RAM available under 1GB. This occurs during both normal boot and S3 resume identically (the latter only for the sake of CpuMpPei borrowing low RAM for the AP startup vector). But, the SMRAM at the default SMBASE falls in the middle of the current system RAM HOB. Split the HOB, and cover the SMRAM with a reserved memory HOB in the middle. CpuMpPei (via MpInitLib) skips reserved memory HOBs. * InitializeRamRegions() is responsible for producing memory allocation HOBs, carving out parts of the resource descriptor HOBs produced in QemuInitializeRam(). Allocate the above-introduced reserved memory region in full, similarly to how we treat TSEG, so that DXE and the OS avoid the locked SMRAM (black hole) in this area. (Note that these allocations only occur on the normal boot path, as they matter for the UEFI memory map, which cannot be changed during S3 resume.) Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-8-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg/PlatformPei: assert there's no permanent PEI RAM at default SMBASELaszlo Ersek2020-02-051-0/+10
| | | | | | | | | | | | | | | | | | | | | | | The permanent PEI RAM that is published on the normal boot path starts strictly above MEMFD_BASE_ADDRESS (8 MB -- see the FDF files), regardless of whether PEI decompression will be necessary on S3 resume due to SMM_REQUIRE. Therefore the normal boot permanent PEI RAM never overlaps with the SMRAM at the default SMBASE (192 KB). The S3 resume permanent PEI RAM is strictly above the normal boot one. Therefore the no-overlap statement holds true on the S3 resume path as well. Assert the no-overlap condition commonly for both boot paths in PublishPeiMemory(). Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-7-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (skeleton)Laszlo Ersek2020-02-051-0/+18
| | | | | | | | | | | | | | | | | Introduce the Q35SmramAtDefaultSmbaseInitialization() function for detecting the "SMRAM at default SMBASE" feature. For now, the function is only a skeleton, so that we can gradually build upon the result while the result is hard-coded as FALSE. The actual detection will occur in a later patch. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-6-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg/PlatformPei: factor out Q35BoardVerification()Laszlo Ersek2020-02-051-12/+1
| | | | | | | | | | | | | | Before adding another SMM-related, and therefore Q35-only, dynamically detectable feature, extract the current board type check from Q35TsegMbytesInitialization() to a standalone function. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-5-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg/PlatformPei: set 32-bit UC area at PciBase / PciExBarBase (pc/q35)Laszlo Ersek2019-06-031-4/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This is a replacement for commit 39b9a5ffe661 ("OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear", 2019-05-16).) Reintroduce the same logic as seen in commit 39b9a5ffe661 for the pc (i440fx) board type. For q35, the same approach doesn't work any longer, given that (a) we'd like to keep the PCIEXBAR in the platform DSC a fixed-at-build PCD, and (b) QEMU expects the PCIEXBAR to reside at a lower address than the 32-bit PCI MMIO aperture. Therefore, introduce a helper function for determining the 32-bit "uncacheable" (MMIO) area base address: - On q35, this function behaves statically. Furthermore, the MTRR setup exploits that the range [0xB000_0000, 0xFFFF_FFFF] can be marked UC with just two variable MTRRs (one at 0xB000_0000 (size 256MB), another at 0xC000_0000 (size 1GB)). - On pc (i440fx), the function behaves dynamically, implementing the same logic as commit 39b9a5ffe661 did. The PciBase value is adjusted to the value calculated, similarly to commit 39b9a5ffe661. A further simplification is that we show that the UC32 area size truncation to a whole power of two automatically guarantees a >=2GB base address. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* Revert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits ↵Laszlo Ersek2019-06-031-21/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | clear" This reverts commit 39b9a5ffe6618b7870be2a54fe7725000249c33a. The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814> triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clearLaszlo Ersek2019-05-161-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assume that we boot OVMF in a QEMU guest with 1025 MB of RAM. The following assertion will fire: > ASSERT_EFI_ERROR (Status = Out of Resources) > ASSERT OvmfPkg/PlatformPei/MemDetect.c(696): !EFI_ERROR (Status) That's because the range [1025 MB, 4 GB) that we try to mark as uncacheable with MTRRs has size 3071 MB: 0x1_0000_0000 -0x0_4010_0000 -------------- 0x0_BFF0_0000 The integer that stands for the uncacheable area size has 11 (eleven) bits set to 1. As a result, covering this size requires 11 variable MTRRs (each MTRR must cover a naturally aligned, power-of-two sized area). But, if we need more variable MTRRs than the CPU can muster (such as 8), then MtrrSetMemoryAttribute() fails, and we refuse to continue booting (which is justified, in itself). Unfortunately, this is not difficult to trigger, and the error message is well-hidden from end-users, in the OVMF debug log. The following mitigation is inspired by SeaBIOS: Truncate the uncacheable area size to a power-of-two, while keeping the end fixed at 4 GB. Such an interval can be covered by just one variable MTRR. This may leave such an MMIO gap, between the end of low-RAM and the start of the uncacheable area, that is marked as WB (through the MTRR default). Raise the base of the 32-bit PCI MMIO aperture accordingly -- the gap will not be used for anything. On Q35, the minimal 32-bit PCI MMIO aperture (triggered by RAM size 2815 MB) shrinks from 0xE000_0000 - 0xAFF0_0000 = 769 MB to 0xE000_0000 - 0xC000_0000 = 512 MB On i440fx, the minimal 32-bit PCI MMIO aperture (triggered by RAM size 3583 MB) shrinks from 0xFC00_0000 - 0xDFF0_0000 = 449 MB to 0xFC00_0000 - 0xE000_0000 = 448 MB Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/PlatformPei: debug log "etc/reserved-memory-end" from fw_cfgLaszlo Ersek2018-03-281-0/+2
| | | | | | | | | | | | | | QEMU calculates the UINT64 value in "etc/reserved-memory-end" in a quite complex way, in the pc_memory_init() function. Log the value as a DEBUG_VERBOSE message to support debugging. Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1353591 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg/PlatformPei: support >=1TB high RAM, and discontiguous high RAMLaszlo Ersek2017-08-051-2/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In OVMF we currently get the upper (>=4GB) memory size with the GetSystemMemorySizeAbove4gb() function. The GetSystemMemorySizeAbove4gb() function is used in two places: (1) It is the starting point of the calculations in GetFirstNonAddress(). GetFirstNonAddress() in turn - determines the placement of the 64-bit PCI MMIO aperture, - provides input for the GCD memory space map's sizing (see AddressWidthInitialization(), and the CPU HOB in MiscInitialization()), - influences the permanent PEI RAM cap (the DXE core's page tables, built in permanent PEI RAM, grow as the RAM to map grows). (2) In QemuInitializeRam(), GetSystemMemorySizeAbove4gb() determines the single memory descriptor HOB that we produce for the upper memory. Respectively, there are two problems with GetSystemMemorySizeAbove4gb(): (1) It reads a 24-bit count of 64KB RAM chunks from the CMOS, and therefore cannot return a larger value than one terabyte. (2) It cannot express discontiguous high RAM. Starting with version 1.7.0, QEMU has provided the fw_cfg file called "etc/e820". Refer to the following QEMU commits: - 0624c7f916b4 ("e820: pass high memory too.", 2013-10-10), - 7d67110f2d9a ("pc: add etc/e820 fw_cfg file", 2013-10-18) - 7db16f2480db ("pc: register e820 entries for ram", 2013-10-10) Ever since these commits in v1.7.0 -- with the last QEMU release being v2.9.0, and v2.10.0 under development --, the only two RAM entries added to this E820 map correspond to the below-4GB RAM range, and the above-4GB RAM range. And, the above-4GB range exactly matches the CMOS registers in question; see the use of "pcms->above_4g_mem_size": pc_q35_init() | pc_init1() pc_memory_init() e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); pc_cmos_init() val = pcms->above_4g_mem_size / 65536; rtc_set_memory(s, 0x5b, val); rtc_set_memory(s, 0x5c, val >> 8); rtc_set_memory(s, 0x5d, val >> 16); Therefore, remedy the above OVMF limitations as follows: (1) Start off GetFirstNonAddress() by scanning the E820 map for the highest exclusive >=4GB RAM address. Fall back to the CMOS if the E820 map is unavailable. Base all further calculations (such as 64-bit PCI MMIO aperture placement, GCD sizing etc) on this value. At the moment, the only difference this change makes is that we can have more than 1TB above 4GB -- given that the sole "high RAM" entry in the E820 map matches the CMOS exactly, modulo the most significant bits (see above). However, Igor plans to add discontiguous (cold-plugged) high RAM to the fw_cfg E820 RAM map later on, and then this scanning will adapt automatically. (2) In QemuInitializeRam(), describe the high RAM regions from the E820 map one by one with memory HOBs. Fall back to the CMOS only if the E820 map is missing. Again, right now this change only makes a difference if there is at least 1TB high RAM. Later on it will adapt to discontiguous high RAM (regardless of its size) automatically. -*- Implementation details: introduce the ScanOrAdd64BitE820Ram() function, which reads the E820 entries from fw_cfg, and finds the highest exclusive >=4GB RAM address, or produces memory resource descriptor HOBs for RAM entries that start at or above 4GB. The RAM map is not read in a single go, because its size can vary, and in PlatformPei we should stay away from dynamic memory allocation, for the following reasons: - "Pool" allocations are limited to ~64KB, are served from HOBs, and cannot be released ever. - "Page" allocations are seriously limited before PlatformPei installs the permanent PEI RAM. Furthermore, page allocations can only be released in DXE, with dedicated code (so the address would have to be passed on with a HOB or PCD). - Raw memory allocation HOBs would require the same freeing in DXE. Therefore we process each E820 entry as soon as it is read from fw_cfg. -*- Considering the impact of high RAM on the DXE core: A few years ago, installing high RAM as *tested* would cause the DXE core to inhabit such ranges rather than carving out its home from the permanent PEI RAM. Fortunately, this was fixed in the following edk2 commit: 3a05b13106d1, "MdeModulePkg DxeCore: Take the range in resource HOB for PHIT as higher priority", 2015-09-18 which I regression-tested at the time: http://mid.mail-archive.com/55FC27B0.4070807@redhat.com Later on, OVMF was changed to install its high RAM as tested (effectively "arming" the earlier DXE core change for OVMF), in the following edk2 commit: 035ce3b37c90, "OvmfPkg/PlatformPei: Add memory above 4GB as tested", 2016-04-21 which I also regression-tested at the time: http://mid.mail-archive.com/571E8B90.1020102@redhat.com Therefore adding more "tested memory" HOBs is safe. Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1468526 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PlatformPei: honor extended TSEG in PcdQ35TsegMbytes if availableLaszlo Ersek2017-07-051-1/+51
| | | | | | | | | | | | | | | | | | | | Recognize an extended TSEG when available in Q35TsegMbytesInitialization(), and set both PcdQ35TsegMbytes (for OvmfPkg/SmmAccess) and "mQ35TsegMbytes" (for PlatformPei's own use) accordingly. The new logic interfaces with the QEMU feature added in QEMU commit 2f295167e0c4 ("q35/mch: implement extended TSEG sizes", 2017-06-08). At this point we have to explicitly restrict Q35TsegMbytesInitialization() to the Q35 board, but that's OK, because Q35TsegMbytesInitialization() is only called when PcdSmmSmramRequire is set, and for that Q35 is already an enforced requirement. Cc: Jordan Justen <jordan.l.justen@intel.com> Suggested-by: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PlatformPei: prepare for PcdQ35TsegMbytes becoming dynamicLaszlo Ersek2017-07-051-3/+14
| | | | | | | | | | | | | | | | | | | | | In one of the next patches we'll turn PcdQ35TsegMbytes into a dynamic PCD, to be set by PlatformPei. Introduce the Q35TsegMbytesInitialization() function and the "mQ35TsegMbytes" global variable to support this. Q35TsegMbytesInitialization() manages the PCD and caches its final value into "mQ35TsegMbytes". Call Q35TsegMbytesInitialization() from InitializePlatform() just in time for the current PCD consumers, PublishPeiMemory(), InitializeRamRegions() and QemuInitializeRam() -- which is called from InitializeRamRegions() -- to be rebased on top of "mQ35TsegMbytes". Call Q35TsegMbytesInitialization() only when PcdSmmSmramRequire is TRUE, given that PcdQ35TsegMbytes is consumed in that case only. Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg: widen PcdQ35TsegMbytes to UINT16Laszlo Ersek2017-07-051-3/+3
| | | | | | | | | | | Widen PcdQ35TsegMbytes to UINT16, in preparation for setting it dynamically to the QEMU-advertized extended TSEG size (which is 16-bits wide). Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PlatformPei: take VCPU count from QEMU and configure MpInitLibLaszlo Ersek2016-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | These settings will allow CpuMpPei and CpuDxe to wait for the initial AP check-ins exactly as long as necessary. It is safe to set PcdCpuMaxLogicalProcessorNumber and PcdCpuApInitTimeOutInMicroSeconds in OvmfPkg/PlatformPei. OvmfPkg/PlatformPei installs the permanent PEI RAM, producing gEfiPeiMemoryDiscoveredPpiGuid, and UefiCpuPkg/CpuMpPei has a depex on gEfiPeiMemoryDiscoveredPpiGuid. It is safe to read the fw_cfg item QemuFwCfgItemSmpCpuCount (0x0005). It was added to QEMU in 2008 as key FW_CFG_NB_CPUS, in commit 905fdcb5264c ("Add common keys to firmware configuration"). Even if the key is unavailable (or if fw_cfg is entirely unavailable, for example on Xen), QemuFwCfgRead16() will return 0, and then we stick with the current behavior. Cc: Igor Mammedov <imammedo@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PlatformPei: eliminate unchecked PcdSetXX() callsLaszlo Ersek2016-10-251-3/+8
| | | | | | | | | | | | | | | | | | These are deprecated / disabled under the DISABLE_NEW_DEPRECATED_INTERFACES feature test macro. Introduce a variable called PcdStatus, and use it to assert the success of these operations (there is no reason for them to fail here). Cc: Anthony PERARD <anthony.perard@citrix.com> Cc: Gary Lin <glin@suse.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=166 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Gary Lin <glin@suse.com> Tested-by: Gary Lin <glin@suse.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg: Fix typing errorsThomas Huth2016-09-121-1/+1
| | | | | | | | | | | Correct some typos (discovered with the codespell utility) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Thomas Huth <thuth@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 23:58:32 +0000