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* UefiCpuPkg/CpuDxe: make register access more readableJian J Wang2018-06-191-15/+29
| | | | | | | | | | | | | | | Update code to use more meaningful constant macro or predefined register structure. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: allow accessing (DXE) page table in SMM modeJian J Wang2018-06-192-35/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MdePkg/Library/SmmMemoryAllocationLib, used only by DXE_SMM_DRIVER, allows to free memory allocated in DXE (before EndOfDxe). This is done by checking the memory range and calling gBS services to do real operation if the memory to free is out of SMRAM. If some memory related features, like Heap Guard, are enabled, gBS interface will turn to EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), provided by DXE driver UefiCpuPkg/CpuDxe, to change memory paging attributes. This means we have part of DXE code running in SMM mode in certain circumstances. Because page table in SMM mode is different from DXE mode and CpuDxe always uses current registers (CR0, CR3, etc.) to get memory paging attributes, it cannot get the correct attributes of DXE memory in SMM mode from SMM page table. This will cause incorrect memory manipulations, like fail the releasing of Guard pages if Heap Guard is enabled. The solution in this patch is to store the DXE page table information (e.g. value of CR0, CR3 registers, etc.) in a global variable of CpuDxe driver. If CpuDxe detects it's in SMM mode, it will use this global variable to access page table instead of current processor registers. This can avoid retrieving wrong DXE memory paging attributes and changing SMM page table attributes unexpectedly. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Remove X86 ASM and S filesLiming Gao2018-06-075-234/+1
| | | | | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules expect for the ones in ResetVector directory. The ones in ResetVector directory are included by Vtf0.nasmb. They are also nasm style. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: remove all code to flush TLB for APsJian J Wang2018-01-291-80/+5
| | | | | | | | | | | | | | | | | | | The reason doing this is that we found that calling StartupAllAps() to flush TLB for all APs in CpuDxe driver after changing page attributes will spend a lot of time to complete. If there are many page attributes update requests, the whole system performance will be slowed down explicitly, including any shell command and UI operation. The solution is removing the flush operation for AP in CpuDxe driver and let AP flush TLB after woken up. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuDxe: fix bad boot performanceJian J Wang2018-01-191-2/+0
| | | | | | | | | | | | | | | | If features like memory profile, protection and heap guard are enabled, a lot of more memory page attributes update actions will happen than usual. An unnecessary sync of CR0.WP setting among APs will then cause worse performance in memory allocation action. Removing the calling of SyncMemoryPageAttributesAp() in function DisableReadOnlyPageWriteProtect and EnableReadOnlyPageWriteProtect can fix this problem. In DEBUG build case, the boot performance can be boosted from 11 minute to 6 minute. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: clear NX attr for page directoryJian J Wang2018-01-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiBootServicesCode, EfiConventionalMemory and EfiReservedMemoryType, the BIOS will hang at a page fault exception randomly. The root cause is that the memory allocation for driver images (actually a memory type conversion from free memory, type of EfiConventionalMemory, to code memory, type of EfiBootServicesCode/EfiRuntimeServicesCode) will get memory with NX set, because the CpuDxe driver will keep the NX attribute (with free memory) in page directory during page table splitting and then override the NX attribute of all its entries. This patch fixes this issue by not inheriting NX attribute when turning a page entry into a page directory during page granularity split. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: fix SetMemoryAttributes issue in 32-bit modeJian J Wang2018-01-181-0/+4
| | | | | | | | | | | | | | | | | | In 32-bit mode, the BIOS will not create page table for memory beyond 4GB and therefore it cannot handle the attributes change request for those memory. But current CpuDxe doesn't check this situation and still try to complete the request, which will cause attributes of incorrect memory address to be changed due to type cast from 64-bit to 32-bit. This patch fixes this issue by checking the end address of input memory block and returning EFI_UNSUPPORTED if it's out of range. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuDxe: suppress invalid warning about uninitialized variableJian J Wang2017-12-131-0/+5
| | | | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Wu Hao <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Wu Hao <hao.a.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Enable protection for newly added page tableJian J Wang2017-12-124-9/+267
| | | | | | | | | | | | | | | | | | | | | | | | | One of the functionalities of CpuDxe is to update memory paging attributes. If page table protection is applied, it must be disabled temporarily before any attributes update and enabled again afterwards. This patch makes use of the same way as DxeIpl to allocate page table memory from reserved memory pool, which helps to reduce potential "split" operation and recursive calling of SetMemorySpaceAttributes(). Laszlo (lersek@redhat.com) did a regression test on QEMU virtual platform with one middle version of this series patch. The details can be found at https://lists.01.org/pipermail/edk2-devel/2017-December/018625.html There're a few changes after his work. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/CpuDxe: Initialize stack switch for MPJian J Wang2017-12-082-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current MP implementation, BSP and AP shares the same exception configuration. Stack switch required by Stack Guard feature needs that BSP and AP have their own configuration. This patch adds code to ask BSP and AP to do exception handler initialization separately. Since AP is not supposed to do memory allocation, all memory needed to setup stack switch will be reserved in BSP and pass to AP via new API EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL ); Following two new PCDs are introduced to configure how to setup new stack for specified exception handlers. gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg/CpuDxe: Fix multiple entries of RT_CODE in memory mapJian J Wang2017-11-241-21/+73
| | | | | | | | | | | | | | | | | | | | | | | | More than one entry of RT_CODE memory might cause boot problem for some old OSs. This patch will fix this issue to keep OS compatibility as much as possible. More detailed information, please refer to https://bugzilla.tianocore.org/show_bug.cgi?id=753 Laszlo did a thorough test on OVMF emulated platform. The details can be found at https://bugzilla.tianocore.org/show_bug.cgi?id=753#c10 Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Fix unix style of EOLJian J Wang2017-11-211-2/+2
| | | | | | | | | Cc: Wu Hao <hao.a.wu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuDxe: Reduce debug messageJian J Wang2017-11-171-2/+2
| | | | | | | | | | | | | | | Heap guard feature will frequently update page attributes. The debug message in CpuDxe driver will slow down the boot performance noticeably. Changing the debug level to DEBUG_VERBOSE to reduce the message output for normal debug configuration. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Fix assert issue on IA32 platformJian J Wang2017-09-301-10/+40
| | | | | | | | | | | | | | | | | This patch is to fix an assert issue during booting IA32 platforms such as OvmfIa32 or Quark. This issue is caused by trying to access page table on a platform without page table. A check is added to avoid the assert. Bug tracker: https://bugzilla.tianocore.org/show_bug.cgi?id=724 Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Add missing function description commentsDandan Bi2017-09-271-0/+3
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* UefiCpuPkg/CpuDxe: Fix GCC build warningJian J Wang2017-09-221-2/+6
| | | | | | | | | | | | | There're uninitialized variables warning reported by GCC. This patch will fix it. The original commit is c1cab54ce57c2608b8b3ea051c7041f036f21153 Cc: Hao Wu <hao.a.wu@intel.com> Cc: Anthony PERARD <anthony.perard@citrix.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuDxe: Fix out-of-sync issue in page attributesJian J Wang2017-09-213-0/+113
| | | | | | | | | | | | | | | | From CpuDxe driver perspective, it doesn't update GCD memory attributes from current page table setup during its initialization. So the memory attributes in GCD might not reflect all memory attributes in real world. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/CpuDxe: log informative message at DEBUG_INFO levelLaszlo Ersek2017-09-111-1/+1
| | | | | | | | | | "Detect CPU count: %d\n" is an informative message, not an error report. Set its debug mask to DEBUG_INFO. Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg CpuDxe: Remove reference deprecated macro.Eric Dong2017-08-072-11/+12
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg CpuDxe: Enhance get mtrr mask logic.Eric Dong2017-08-071-7/+6
| | | | | | | | | | | In order to not use the deprecated macro, refine get mtrr mask value logic. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg CpuDxe: Update return status to follow spec.Eric Dong2017-07-072-2/+2
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Move ProgramVirtualWireMode() to MpInitLibJeff Fan2017-04-261-5/+0
| | | | | | | | | | | | | | | In PEI phase, BSP did not program vitural wired mode while APs did. Move program virtual wired mode from CpuDxe to MpInitLib, thus it could benefit on both CpuDxe and CpuMpPei. https://bugzilla.tianocore.org/show_bug.cgi?id=496 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Error Level is not used correctlyJeff Fan2017-04-121-1/+1
| | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE checkJeff Fan2017-03-171-6/+3
| | | | | | | | | | | | | | The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors. Because reading CPUID.80000001H:EDK[20] is enough to check if XD feature is supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0). Cc: Anthony PERARD <anthony.perard@citrix.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMaskLeo Duran2017-03-062-9/+26
| | | | | | | | | | | | | | | | | This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables entries are created or modified. CC: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuDxe: Do not ASSERT on AllocateMemorySpace() errorJeff Fan2017-02-271-1/+9
| | | | | | | | | | | | | | | | | | | | | | | Platform PEI may add LOCAL APIC memory mapped space into EFI_HOB_MEMORY_ALLOCATION. Or platform may allocate this range before. So, we skip AllocateMemorySpace()'s return status checking. Instead, we add one DEBUG message for possible trace. https://bugzilla.tianocore.org/show_bug.cgi?id=390 This updating is suggested by Ersek's comments at https://www.mail-archive.com/edk2-devel@lists.01.org/msg22585.html Cc: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Replace EFI_D_xxx with DEBUG_xxx in DEBUG()Jeff Fan2017-02-242-7/+7
| | | | | | | | | | Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Fix hard code actual TimerPeriod valueJeff Fan2017-02-223-3/+25
| | | | | | | | | | | | | | | Current CpuGetTimerValue() implementation return hard code TimerPeriod value. We could calculate the actual TimerPeriod value over period of time (100us) at the first time invoking CpuGetTimerValue() and save the TimerPeriod value into one global variable to avoid delay at the next CpuGetTimerValue() invoking. https://bugzilla.tianocore.org/show_bug.cgi?id=382 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuDxe: Add Local APIC memory mapped space in GCDJeff Fan2017-02-221-0/+35
| | | | | | | | | | | | | | | | | | | | | Local APIC memory mapped space should be added into GCD and be allocated. Otherwise, UEFI firmware cannot get correct memory map for it. For example, SMM profile feature needs to get the completed MMIO map to protect them. v2: Consume AddMemoryMappedIoSpace() to handle the case that Local APIC memory space has already been added before. https://bugzilla.tianocore.org/show_bug.cgi?id=390 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Copy two functions from PciHostBridgeJeff Fan2017-02-221-0/+148
| | | | | | | | | | | | | | | | Copy AddMemoryMappedIoSpace() and IntersectMemoryDescriptor() from MdeModulePkg\Bus\Pci\PciHostBridgeDxe\PciHostBridge.c. https://bugzilla.tianocore.org/show_bug.cgi?id=390 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Add memory attribute setting.Jiewen Yao2017-02-224-61/+977
| | | | | | | | | | | | | | Add memory attribute setting in CpuArch protocol. Previous SetMemoryAttributes() API only supports cache attribute setting. This patch updated SetMemoryAttributes() API to support memory attribute setting by updating CPU page table. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Make the comments align with the functionsDandan Bi2016-12-141-1/+1
| | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuDxe: Fix duplicated status code reportJeff Fan2016-09-141-14/+15
| | | | | | | | | | | | | | | If CPU Bist data is not zero, we will report Status code. But there is one bug that will report each processor's status code duplicated with NumberOfData times. This fix is to exchange the loop order on NumberOfData and mNumberOfProcessors. It could make sure the report status code only once for each processor. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuDxe: Fixed typo in function header to match PI specJeff Fan2016-08-171-18/+18
| | | | | | | | | | | | | Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Remove PcdCpuMaxLogicalProcessorNumber consumingJeff Fan2016-08-172-16/+5
| | | | | | | | | | | | | | | | | | | v5: If PcdCpuMaxLogicalProcessorNumber is set to 1 on UP system, MpInitLibInitialize() will be invoked. This is one bug, we need to call MpInitLibInitialize() always and get the BSP information. Just to remove PcdCpuMaxLogicalProcessorNumber() consuming from this driver. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Remove unused codes and filesJeff Fan2016-08-179-1359/+1
| | | | | | | | | | | | | | | | | | v5: 1. Remove unused PcdCpuApStackSize and PcdCpuApInitTimeOutInMicroSeconds. v4: 1. Keep GDT table setup to fix IA32 S3 boot issue. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Move SetMtrrsFromBuffer() location.Jeff Fan2016-08-172-16/+15
| | | | | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Consume MpInitLib to produce CPU MP Protocol servicesJeff Fan2016-08-177-815/+76
| | | | | | | | | | | | | | | | | | | | | | | | | Consume MP Initialize library to produce CPU MP Protocol services to simply the code. v4: 1. Update CpuDxe.c file header to mention it produces CPU Arch protocol. 2. Update BistData type from UINT32 to EFI_HEALTH_FLAG. 3. Move some header location from CpuMp.h to CpuDxe.h. v3: 1. Move the code Consume MpInitLib APIs to produce CPU MP Protocol from patch #40 to this patch. 2. Add DxeMpInitLib.inf in DSC file Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: StartupAllAPs in parallel modeJeff Fan2016-07-201-2/+2
| | | | | | | | | | | | | | SetMemoryAttributes() will sync BSP's MTRRs settings to all APs by StartupAllAPs service in serial mode. It may caused much performance impact if there are too much processors in system. This update is to invoke StartupAllAps in parallel mode. IA32 SDM does suggest to program MTRRs in parallel mode. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg CpuDxe: Add nasm source file in CpuDxe.infLiming Gao2016-06-282-13/+63
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg CpuDxe: Convert Ia32/CpuAsm.asm to NASMLiming Gao2016-06-281-0/+53
| | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/CpuAsm.asm to Ia32/CpuAsm.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Convert all .uni files to utf-8Jordan Justen2015-12-152-0/+0
| | | | | | | | | | | | | To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuDxe: Don't use gBS->StallJordan Justen2015-11-201-3/+3
| | | | | | | | | | | | | The CpuDxe driver may run before the gEfiMetronomeArchProtocolGuid protocol is installed. gBS->Stall does not work until this arch protocol is installed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18914 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: CpuDxe: Update GDT to be consistent with DxeIplPeimMichael Kinney2015-10-302-40/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PiSmmCpuDxeSmm module makes some assumptions about GDT selectors that are based on the GDT layout from the DxeIplPeim. For example, the protected mode entry code and (where appropriate) the long mode entry code in the UefiCpuPkg/PiSmmCpuDxeSmm/*/MpFuncs.* assembly files, which are used during S3 resume, open-code segment selector values that depend on DxeIplPeim's GDT layout. This updates the CpuDxe module to use the same GDT layout as the DxeIplPeim. This enables modules that are dispatched after CpuDxe to find, and potentially save and restore, a GDT layout that matches that of DxeIplPeim. The DxeIplPeim has a 2 GDT entries for data selectors that are identical. These are LINEAR_SEL (GDT Offset 0x08)and LINEAR_DATA64_SEL (GDT offset 0x30). LINEAL_SEL is used for for IA32 DXE and the LINEAR_DATA64_SEL is used for X64 DXE. This duplicate data selector was added to the CpuDxe module to keep the GDT and all selectors consistent. Using a consistent GDT also improves debug experience. Reported-by: Laszlo Ersek <lersek@redhat.com> Analyzed-by: Laszlo Ersek <lersek@redhat.com> Link: http://article.gmane.org/gmane.comp.bios.edk2.devel/3568 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18710 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: CpuDxe: broadcast MTRR changes to APsLaszlo Ersek2015-10-193-0/+71
| | | | | | | | | | | | | | | | | | | | | | The Quark_EDKII_v1.1.0/IA32FamilyCpuBasePkg/CpuArchDxe driver applies any MTRR changes to APs, if the EFI_MP_SERVICES_PROTOCOL is available. We should do the same. Additionally, the broadcast should occur at MP startup as well, not only when MTRR settings are changed. The inspiration is taken from Quark_EDKII_v1.1.0/IA32FamilyCpuBasePkg/CpuMpDxe/ (see the EarlyMpInit() function and its call sites in "ProcessorConfig.c"). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18632 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: CpuDxe: Wait for APs to enter idle loopMichael Kinney2015-10-191-1/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Address a race condition in first call to StartupAllAPs() with SingleThread set to TRUE in the MP initialization. If the APs have not entered their idle loop before StartupAllAPs() is called, then some of the APs will be in an unexpected state, and StartupAllAPs() will hang. This is the hang condition that is only seen when SingleThread parameter is set to TRUE and StartupAllAPs() is called very shortly after mAPsAlreadyInitFinished is set to TRUE that releases the APs to complete their initialization. An internal function has been added to check if all APs are in the sleeping state in their idle loop. On the first call to StartupAllAPs(), this internal function is used in a loop to make sure the APs are in a state that is compatible with the use of StartupAllAPs(). PcdCpuApInitTimeOutInMicroSeconds is used as the maximum wait time for the APs to enter their idle loop. If all APs have not entered their idle loop within the timeout, then an ASSERT() is generated. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18631 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: CpuDxe: Use PCD for AP detection timeoutMichael Kinney2015-10-192-4/+5
| | | | | | | | | | | | | | | Use PcdCpuApInitTimeOutInMicroSeconds instead of hardcoded 100ms for the time to wait for all APs to respond to first INIT SIPI SIPI wake request. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18630 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Update CPU MP drivers to support single CPU configurationMichael Kinney2015-10-191-21/+28
| | | | | | | | | | | Only perform AP detection if PcdCpuMaxLogicalProcessorNumber > 1 Only free AP related structures of they were allocated Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18629 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg CpuDxe: Sync up the settings of Execute Disable to APsStar Zeng2015-08-081-2/+133
| | | | | | | | | | | | | | | | | | | when stack NX has been enabled for BSP. DxeIpl may have enabled Execute Disable for BSP, APs need to get the status and sync up the settings, otherwise EFI_MP_SERVICES_PROTOCOL->StartupAllAPs may not work. Got positive comments and test result from Laszlo for the early draft patch, thanks. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18191 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuDxe: NumberOfData is not BOOLEAN typeJeff Fan2015-06-191-1/+1
| | | | | | | | | | Should check NumberOfData value instead of treat its value as one BOOLEAN type. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shuming Qiu <shuming.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17672 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 10:54:12 +0000