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* UefiCpuPkg/CpuDxe: Fix few typosAntoine Coeur2020-02-108-15/+15
| | | | | | | | | | | | | | Fix few typos in comments and documentation. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-77-philmd@redhat.com>
* UefiCpuPkg/CpuDxe: clean up PAGE_TABLE_LIB_PAGING_CONTEXT usage.Dong, Eric2019-09-255-16/+112
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1039 Current implementation not checks system mode before using PAGE_TABLE_LIB_PAGING_CONTEXT.ContextData.X64 or PAGE_TABLE_LIB_PAGING_CONTEXT.ContextData.Ia32. This patch check the mode before using the correct one. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Update code to include register definitions from MdePkgNi, Ray2019-08-092-4/+4
| | | | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: Support parsing 5-level page tableNi, Ray2019-08-092-2/+19
| | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: Remove unnecessary macrosNi, Ray2019-08-091-19/+24
| | | | | | | | | | | | | | | | | Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE when checking whether individual bits are set in CR0 or CR4 register. The patch changes the code to use IA32_CR0 and IA32_CR4 structure defined in MdePkg/Include/Library/BaseLib.h so that the module local macros can be removed. There is no functionality impact to this change. Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0913-91/+13
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: restore strict page attributes via #DB in nonstop mode onlyJian J Wang2019-03-011-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1576 The root cause of this issue is that non-stop mode of Heap Guard and NULL Detection set TF bit (single-step) in EFLAG unconditionally in the common handler in CpuExceptionLib. If PcdCpuSmmStaticPageTable is FALSE, the SMM will only create page table for memory below 4G. If SMM tries to access memory beyond 4G, a page fault exception will be triggered and the memory to access will be added to page table so that SMM code can continue the access. Because of above issue, the TF bit is set after the page fault is handled and then fall into another DEBUG exception. Since non-stop mode of Heap Guard and NULL Detection are not enabled, no special DEBUG exception handler is registered. The default handler just prints exception context and go into dead loop. Actually EFLAGS can be changed in any standard exception handler. There's no need to do single-step setup in assembly code. So the fix is to move the logic to C code part of page fault exception handler so that we can fully validate the configuration and prevent TF bit from being set unexpectedly. Fixes: dcc026217fdc363f55c217039fc43d344f69fed6 16b918bbaf51211a32ae04d9d8a5ba6ccca25a6a Test: - Pass special test of accessing memory beyond 4G in SMM mode - Boot to OS with Qemu emulator platform (Fedora27, Ubuntu18.04, Windows7, Windows10) Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: prevent recursive calling of InitializePageTablePoolJian J Wang2018-10-261-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The freed-memory guard feature will cause a recursive calling of InitializePageTablePool(). This is due to a fact that AllocateAlignedPages() is used to allocate page table pool memory. This function will most likely call gBS->FreePages to free unaligned pages and then cause another round of page attributes change, like below (freed pages will be always marked not-present if freed-memory guard is enabled) FreePages() <===============| => CpuSetMemoryAttributes() | => <if out of page table> | => InitializePageTablePool() | => AllocateAlignedPages() | => FreePages() ================| The solution is add a global variable as a lock in page table pool allocation function and fail any other requests if it has not been done. Since this issue will only happen if free-memory guard is enabled, it won't affect CpuSetMemoryAttributes() in default build of a BIOS. If free-memory guard is enabled, it only affect the pages (failed to mark them as not-present) freed in AllocateAlignedPages(). Since those freed pages haven't been used yet (their addresses not yet exposed to code outside AllocateAlignedPages), it won't compromise the freed-memory guard feature. This change will just fail the CpuSetMemoryAttributes() called from FreePages() but it won't fail the FreePages(). So the error status won't be propagated upper layer of code. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: consider freed-memory guard in non-stop modeJian J Wang2018-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Non-stop mode was introduced / explained in commit 8f2613628acf ("MdeModulePkg/MdeModulePkg.dec: add new settings for PCDs", 2018-08-30). The macro HEAP_GUARD_NONSTOP_MODE was added to CpuDxe in commit dcc026217fdc ("UefiCpuPkg/CpuDxe: implement non-stop mode for uefi", 2018-08-30). Another instance of the macro HEAP_GUARD_NONSTOP_MODE was added to PiSmmCpuDxeSmm -- with BIT1|BIT0 replaced with BIT3|BIT2 -- in commit 09afd9a42a7f ("UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMM", 2018-08-30) Since the freed-memory guard is for UEFI-only. This patch only updates HEAP_GUARD_NONSTOP_MODE in "UefiCpuPkg/CpuDxe/CpuDxe.h" (add BIT4). Cc: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Remove redundant library classes, Ppis and GUIDsshenglei2018-09-211-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some redundant library classes Ppis and GUIDs have been removed in inf, .c and .h files. v2: 1.Remove ReadOnlyVariable2.h in S3Resume.c which should be deleted in last version in which gEfiPeiReadOnlyVariable2PpiGuid was removed. 2.Remove the library class BaseLib in CpuPageTable.c which is included elsewhere. 3.Add library classes in SecCore.inf which are removed at last version. They are DebugAgentLib and CpuExceptionHandlerLib. 4.Add two Ppis in SecCore.inf which are removed at last version. They are gEfiSecPlatformInformationPpiGuid and gEfiSecPlatformInformation2PpiGuid. https://bugzilla.tianocore.org/show_bug.cgi?id=1043 https://bugzilla.tianocore.org/show_bug.cgi?id=1013 https://bugzilla.tianocore.org/show_bug.cgi?id=1032 https://bugzilla.tianocore.org/show_bug.cgi?id=1016 Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: fix an incorrect bit-wise operationJian J Wang2018-09-101-1/+1
| | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1164 The left operand is 64-bit but right operand could be 32-bit. A typecast is a must because of '~' op before it. Cc: Hao A Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuDxe: fix ECC reported issuesJian J Wang2018-09-101-2/+2
| | | | | | | | | | | BZ#: https://bugzilla.tianocore.org/show_bug.cgi?id=1160 There're two parameters which have different name in comment and prototype. Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/CpuDxe: change level of DEBUG messageJian J Wang2018-08-302-3/+3
| | | | | | | | | | | | | | | | BZ#1127: https://bugzilla.tianocore.org/show_bug.cgi?id=1127 It's reported the debug message in CpuDxe driver is quite annoying in boot and shell, and slow down the boot process. To solve this issue, this patch changes the DEBUG_INFO to DEBUG_VERBOSE. On a typical Intel real platform, at least 16s boot time can be saved. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: implement non-stop mode for uefiJian J Wang2018-08-304-6/+237
| | | | | | | | | | | | | | | | | | | | | Same as SMM profile feature, a special #PF is used to set page attribute to 'present' and a special #DB handler to reset it back to 'not-present', right after the instruction causing #PF got executed. Since the new #PF handler won't enter into dead-loop, the instruction which caused the #PF will get chance to re-execute with accessible pages. The exception message will still be printed out on debug console so that the developer/QA can find that there's potential heap overflow or null pointer access occurred. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: fix incorrect check of SMM modeJian J Wang2018-07-201-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current IsInSmm() method makes use of gEfiSmmBase2ProtocolGuid.InSmm() to check if current processor is in SMM mode or not. But this is not correct because gEfiSmmBase2ProtocolGuid.InSmm() can only detect if the caller is running in SMRAM or from SMM driver. It cannot guarantee if the caller is running in SMM mode. Because SMM mode will load its own page table, adding an extra check of saved DXE page table base address against current CR3 register value can help to get the correct answer for sure (in SMM mode or not in SMM mode). There's indiscriminate uses of Context.X64 and Context.Ia32 in code which is not a good coding practice and will cause potential issue. In addition, the related structure type definition is not packed and has also potential issue. This will not be covered by this patch but be tracked by a bug below. https://bugzilla.tianocore.org/show_bug.cgi?id=1039 This is an issue caused by check-in at 2a1408d1d739ead00c96397549be7a9fc53c9c6e Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-283-9/+9
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/CpuDxe: make register access more readableJian J Wang2018-06-191-15/+29
| | | | | | | | | | | | | | | Update code to use more meaningful constant macro or predefined register structure. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: allow accessing (DXE) page table in SMM modeJian J Wang2018-06-192-35/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MdePkg/Library/SmmMemoryAllocationLib, used only by DXE_SMM_DRIVER, allows to free memory allocated in DXE (before EndOfDxe). This is done by checking the memory range and calling gBS services to do real operation if the memory to free is out of SMRAM. If some memory related features, like Heap Guard, are enabled, gBS interface will turn to EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), provided by DXE driver UefiCpuPkg/CpuDxe, to change memory paging attributes. This means we have part of DXE code running in SMM mode in certain circumstances. Because page table in SMM mode is different from DXE mode and CpuDxe always uses current registers (CR0, CR3, etc.) to get memory paging attributes, it cannot get the correct attributes of DXE memory in SMM mode from SMM page table. This will cause incorrect memory manipulations, like fail the releasing of Guard pages if Heap Guard is enabled. The solution in this patch is to store the DXE page table information (e.g. value of CR0, CR3 registers, etc.) in a global variable of CpuDxe driver. If CpuDxe detects it's in SMM mode, it will use this global variable to access page table instead of current processor registers. This can avoid retrieving wrong DXE memory paging attributes and changing SMM page table attributes unexpectedly. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Remove X86 ASM and S filesLiming Gao2018-06-075-234/+1
| | | | | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules expect for the ones in ResetVector directory. The ones in ResetVector directory are included by Vtf0.nasmb. They are also nasm style. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: remove all code to flush TLB for APsJian J Wang2018-01-291-80/+5
| | | | | | | | | | | | | | | | | | | The reason doing this is that we found that calling StartupAllAps() to flush TLB for all APs in CpuDxe driver after changing page attributes will spend a lot of time to complete. If there are many page attributes update requests, the whole system performance will be slowed down explicitly, including any shell command and UI operation. The solution is removing the flush operation for AP in CpuDxe driver and let AP flush TLB after woken up. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuDxe: fix bad boot performanceJian J Wang2018-01-191-2/+0
| | | | | | | | | | | | | | | | If features like memory profile, protection and heap guard are enabled, a lot of more memory page attributes update actions will happen than usual. An unnecessary sync of CR0.WP setting among APs will then cause worse performance in memory allocation action. Removing the calling of SyncMemoryPageAttributesAp() in function DisableReadOnlyPageWriteProtect and EnableReadOnlyPageWriteProtect can fix this problem. In DEBUG build case, the boot performance can be boosted from 11 minute to 6 minute. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: clear NX attr for page directoryJian J Wang2018-01-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiBootServicesCode, EfiConventionalMemory and EfiReservedMemoryType, the BIOS will hang at a page fault exception randomly. The root cause is that the memory allocation for driver images (actually a memory type conversion from free memory, type of EfiConventionalMemory, to code memory, type of EfiBootServicesCode/EfiRuntimeServicesCode) will get memory with NX set, because the CpuDxe driver will keep the NX attribute (with free memory) in page directory during page table splitting and then override the NX attribute of all its entries. This patch fixes this issue by not inheriting NX attribute when turning a page entry into a page directory during page granularity split. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuDxe: fix SetMemoryAttributes issue in 32-bit modeJian J Wang2018-01-181-0/+4
| | | | | | | | | | | | | | | | | | In 32-bit mode, the BIOS will not create page table for memory beyond 4GB and therefore it cannot handle the attributes change request for those memory. But current CpuDxe doesn't check this situation and still try to complete the request, which will cause attributes of incorrect memory address to be changed due to type cast from 64-bit to 32-bit. This patch fixes this issue by checking the end address of input memory block and returning EFI_UNSUPPORTED if it's out of range. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuDxe: suppress invalid warning about uninitialized variableJian J Wang2017-12-131-0/+5
| | | | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Wu Hao <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Wu Hao <hao.a.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Enable protection for newly added page tableJian J Wang2017-12-124-9/+267
| | | | | | | | | | | | | | | | | | | | | | | | | One of the functionalities of CpuDxe is to update memory paging attributes. If page table protection is applied, it must be disabled temporarily before any attributes update and enabled again afterwards. This patch makes use of the same way as DxeIpl to allocate page table memory from reserved memory pool, which helps to reduce potential "split" operation and recursive calling of SetMemorySpaceAttributes(). Laszlo (lersek@redhat.com) did a regression test on QEMU virtual platform with one middle version of this series patch. The details can be found at https://lists.01.org/pipermail/edk2-devel/2017-December/018625.html There're a few changes after his work. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/CpuDxe: Initialize stack switch for MPJian J Wang2017-12-082-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current MP implementation, BSP and AP shares the same exception configuration. Stack switch required by Stack Guard feature needs that BSP and AP have their own configuration. This patch adds code to ask BSP and AP to do exception handler initialization separately. Since AP is not supposed to do memory allocation, all memory needed to setup stack switch will be reserved in BSP and pass to AP via new API EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL ); Following two new PCDs are introduced to configure how to setup new stack for specified exception handlers. gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg/CpuDxe: Fix multiple entries of RT_CODE in memory mapJian J Wang2017-11-241-21/+73
| | | | | | | | | | | | | | | | | | | | | | | | More than one entry of RT_CODE memory might cause boot problem for some old OSs. This patch will fix this issue to keep OS compatibility as much as possible. More detailed information, please refer to https://bugzilla.tianocore.org/show_bug.cgi?id=753 Laszlo did a thorough test on OVMF emulated platform. The details can be found at https://bugzilla.tianocore.org/show_bug.cgi?id=753#c10 Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Fix unix style of EOLJian J Wang2017-11-211-2/+2
| | | | | | | | | Cc: Wu Hao <hao.a.wu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuDxe: Reduce debug messageJian J Wang2017-11-171-2/+2
| | | | | | | | | | | | | | | Heap guard feature will frequently update page attributes. The debug message in CpuDxe driver will slow down the boot performance noticeably. Changing the debug level to DEBUG_VERBOSE to reduce the message output for normal debug configuration. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Fix assert issue on IA32 platformJian J Wang2017-09-301-10/+40
| | | | | | | | | | | | | | | | | This patch is to fix an assert issue during booting IA32 platforms such as OvmfIa32 or Quark. This issue is caused by trying to access page table on a platform without page table. A check is added to avoid the assert. Bug tracker: https://bugzilla.tianocore.org/show_bug.cgi?id=724 Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Add missing function description commentsDandan Bi2017-09-271-0/+3
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* UefiCpuPkg/CpuDxe: Fix GCC build warningJian J Wang2017-09-221-2/+6
| | | | | | | | | | | | | There're uninitialized variables warning reported by GCC. This patch will fix it. The original commit is c1cab54ce57c2608b8b3ea051c7041f036f21153 Cc: Hao Wu <hao.a.wu@intel.com> Cc: Anthony PERARD <anthony.perard@citrix.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuDxe: Fix out-of-sync issue in page attributesJian J Wang2017-09-213-0/+113
| | | | | | | | | | | | | | | | From CpuDxe driver perspective, it doesn't update GCD memory attributes from current page table setup during its initialization. So the memory attributes in GCD might not reflect all memory attributes in real world. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/CpuDxe: log informative message at DEBUG_INFO levelLaszlo Ersek2017-09-111-1/+1
| | | | | | | | | | "Detect CPU count: %d\n" is an informative message, not an error report. Set its debug mask to DEBUG_INFO. Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg CpuDxe: Remove reference deprecated macro.Eric Dong2017-08-072-11/+12
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg CpuDxe: Enhance get mtrr mask logic.Eric Dong2017-08-071-7/+6
| | | | | | | | | | | In order to not use the deprecated macro, refine get mtrr mask value logic. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg CpuDxe: Update return status to follow spec.Eric Dong2017-07-072-2/+2
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Move ProgramVirtualWireMode() to MpInitLibJeff Fan2017-04-261-5/+0
| | | | | | | | | | | | | | | In PEI phase, BSP did not program vitural wired mode while APs did. Move program virtual wired mode from CpuDxe to MpInitLib, thus it could benefit on both CpuDxe and CpuMpPei. https://bugzilla.tianocore.org/show_bug.cgi?id=496 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Error Level is not used correctlyJeff Fan2017-04-121-1/+1
| | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE checkJeff Fan2017-03-171-6/+3
| | | | | | | | | | | | | | The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors. Because reading CPUID.80000001H:EDK[20] is enough to check if XD feature is supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0). Cc: Anthony PERARD <anthony.perard@citrix.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMaskLeo Duran2017-03-062-9/+26
| | | | | | | | | | | | | | | | | This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables entries are created or modified. CC: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuDxe: Do not ASSERT on AllocateMemorySpace() errorJeff Fan2017-02-271-1/+9
| | | | | | | | | | | | | | | | | | | | | | | Platform PEI may add LOCAL APIC memory mapped space into EFI_HOB_MEMORY_ALLOCATION. Or platform may allocate this range before. So, we skip AllocateMemorySpace()'s return status checking. Instead, we add one DEBUG message for possible trace. https://bugzilla.tianocore.org/show_bug.cgi?id=390 This updating is suggested by Ersek's comments at https://www.mail-archive.com/edk2-devel@lists.01.org/msg22585.html Cc: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Replace EFI_D_xxx with DEBUG_xxx in DEBUG()Jeff Fan2017-02-242-7/+7
| | | | | | | | | | Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Fix hard code actual TimerPeriod valueJeff Fan2017-02-223-3/+25
| | | | | | | | | | | | | | | Current CpuGetTimerValue() implementation return hard code TimerPeriod value. We could calculate the actual TimerPeriod value over period of time (100us) at the first time invoking CpuGetTimerValue() and save the TimerPeriod value into one global variable to avoid delay at the next CpuGetTimerValue() invoking. https://bugzilla.tianocore.org/show_bug.cgi?id=382 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuDxe: Add Local APIC memory mapped space in GCDJeff Fan2017-02-221-0/+35
| | | | | | | | | | | | | | | | | | | | | Local APIC memory mapped space should be added into GCD and be allocated. Otherwise, UEFI firmware cannot get correct memory map for it. For example, SMM profile feature needs to get the completed MMIO map to protect them. v2: Consume AddMemoryMappedIoSpace() to handle the case that Local APIC memory space has already been added before. https://bugzilla.tianocore.org/show_bug.cgi?id=390 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Copy two functions from PciHostBridgeJeff Fan2017-02-221-0/+148
| | | | | | | | | | | | | | | | Copy AddMemoryMappedIoSpace() and IntersectMemoryDescriptor() from MdeModulePkg\Bus\Pci\PciHostBridgeDxe\PciHostBridge.c. https://bugzilla.tianocore.org/show_bug.cgi?id=390 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Add memory attribute setting.Jiewen Yao2017-02-224-61/+977
| | | | | | | | | | | | | | Add memory attribute setting in CpuArch protocol. Previous SetMemoryAttributes() API only supports cache attribute setting. This patch updated SetMemoryAttributes() API to support memory attribute setting by updating CPU page table. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Make the comments align with the functionsDandan Bi2016-12-141-1/+1
| | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuDxe: Fix duplicated status code reportJeff Fan2016-09-141-14/+15
| | | | | | | | | | | | | | | If CPU Bist data is not zero, we will report Status code. But there is one bug that will report each processor's status code duplicated with NumberOfData times. This fix is to exchange the loop order on NumberOfData and mNumberOfProcessors. It could make sure the report status code only once for each processor. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuDxe: Fixed typo in function header to match PI specJeff Fan2016-08-171-18/+18
| | | | | | | | | | | | | Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 01:53:21 +0000