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* UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.Eric Dong2018-09-261-0/+48
| | | | | | | | | | | | | Changes includes: 1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for ↵Eric Dong2018-09-262-3/+276
| | | | | | | | | | | | | | | goldmont plus microarchitecture. Changes includes: 1. Add new MSR file which used for goldmont plus microarchitecture. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr: Update reference spec info.Eric Dong2018-09-2621-372/+359
| | | | | | | | | | | | | | | | | | Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4 chapter 2. Current MSR's comments need to be updated to reference the new chapter info. Changes includes: 1. Update referenced chapter info from some MSRs. 2. Update referenced SDM version info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/AcpiCpuData.h: Remove AcpiNVS and Below 4G limitation.Eric Dong2018-08-161-22/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACPI_CPU_DATA structure first introduced to save data in normal boot phase. Also this data will be used in S3 phase by one PEI driver. So in first phase, this data is been defined to use ACPI NVS memory type and must below 4G. Later in order to fix potential security issue, PiSmmCpuDxeSmm driver added logic to copy ACPI_CPU_DATA (except ResetVector and Stack buffer) to smram at smm ready to lock point. ResetVector must below 1M and Stack buffer is write only in S3 phase, so these two fields not copy to smram. Also PiSmmCpuDxeSmm driver owned the task to restore the CPU setting and it's a SMM driver. After above change, the acpi nvs memory type and below 4G limitation is no longer needed. This change remove the limitation in the comments for ACPI_CPU_DATA definition. Cc: Marvin Häuser <Marvin.Haeuser@outlook.com> Cc: Fan Jeff <vanjeff_919@hotmail.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-281-23/+23
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/MtrrLib: Add comments to recommend to use batch-set APIRuiyu Ni2018-01-241-0/+10
| | | | | | | | | | | | | MtrrSetMemoryAttributesInMtrrSettings() is a batch-set API. When setting multiple ranges of memory attributes, the single-set API (MtrrSetMemoryAttributeInMtrrSettings and MtrrSetMemoryAttribute) may fail, but batch-set API may succeed. Add comments to recommend caller to use batch-set API when setting multiple ranges. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/MtrrLib: Update the comments for RETURN_BUFFER_TOO_SMALLRuiyu Ni2018-01-241-3/+7
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* Revert "UefiCpuPkg: Check invalid RegisterCpuFeature parameter"Eric Dong2017-12-271-5/+0
| | | | | | | | | | | This reverts commit 5c59537c1092a1372913274636a8d766fdd97e61. Current code already has function IsCpuFeatureSupported to do the feature validation, not need this check logic anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Check invalid RegisterCpuFeature parameterSong, BinX2017-12-131-0/+5
| | | | | | | | | | | | | | V2: Update function name, add more detail description. V1: Check and assert invalid RegisterCpuFeature function parameter Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkgStar Zeng2017-11-302-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 To consume FIT table for Microcode update, UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe needs to be updated to consume IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h, but UefiCpuPkg could not depend on IntelSiliconPkg. Since the Microcode update feature is specific to Intel, we can first move the Microcode update feature code from UefiCpuPkg to IntelSiliconPkg [first step], then update the code to consume FIT table [second step]. This patch series is for the first step. Note: No any code change in this patch, just move. Next patch will update MicrocodeUpdate to build with the package. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MtrrLib: Make comments align with functionDandan Bi2017-10-241-1/+1
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settingsRuiyu Ni2017-10-161-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new algorithm converts the problem calculating optimal MTRR settings (using least MTRR registers) to the problem finding the shortest path in a graph. The memory required in extreme but rare case can be up to 256KB, so using local stack buffer is impossible considering current DxeIpl only allocates 128KB stack. The patch changes existing MtrrSetMemoryAttributeInMtrrSettings() and MtrrSetMemoryAttribute() to use the 4-page stack buffer for calculation. The two APIs return BUFFER_TOO_SMALL when the buffer is too small for calculation. The patch adds a new API MtrrSetMemoryAttribute*s*InMtrrSettings() to set multiple-range attributes in one function call. Since every call to MtrrSetMemoryAttributeInMtrrSettings (without-s) or MtrrSetMemoryAttribute() requires to calculate the MTRRs for the whole physical memory, combining multiple calls in one API can significantly reduce the calculation time. In theory, if N times of call to without-s API costs N seconds, the new API only costs 1 second. The new API uses the buffer supplied from caller to calculate MTRRs and returns BUFFER_TOO_SMALL when the buffer is too small for calculation. Test performed: 1. Random test a. Generate random memory settings, use the new algorithm to calculate the MTRRs. b. Read back the MTRRs and check the memory settings match the desired memory settings. c. Repeat the above #1 and #2 100000 times. 2. OVMF 32PEI + 64DXE boot to shell. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition.Eric Dong2017-08-281-1/+78
| | | | | | | | | | | | Add RTIT TOPA table entry definition to architecturalMsr.h file. V2: Add RTIT_TOPA_MEMORY_SIZE definition to architecturalMsr.h file. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg MtrrLib: Remove deprecated micro.Eric Dong2017-08-071-27/+0
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Add Processor Trace feature definition.Eric Dong2017-08-041-0/+1
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Msr: Add a missing IvyBridge processor signatureHao Wu2017-08-041-1/+2
| | | | | | | | | | | This commit modifies the CPUID signature check MACRO for IvyBridge processor by adding a missing DisplayModel 0x3E. The missing one appears at Section 35.10.1 to Section 35.10.3 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Add definition for LMCE feature.Eric Dong2017-08-041-0/+1
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Remove deprecated CPU feature.Eric Dong2017-07-201-1/+0
| | | | | | | | | | | | Senter feature could not be a single feature, it has been merge to Smx feature, so remove it. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Add feature definition for PPIN.Eric Dong2017-07-201-0/+1
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Fix coding style issuesDandan Bi2017-06-291-2/+2
| | | | | | | | | Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Add CPUID definitions for AMD.Leo Duran2017-06-261-9/+590
| | | | | | | | | | Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Define AMD Memory Encryption specific CPUID and MSRBrijesh Singh2017-06-263-0/+253
| | | | | | | | | | | | | | | The patch defines AMD's Memory Encryption Information CPUID leaf and SEV status MSR. The complete description for CPUID leaf is available in APM volume 2, Section 15.34. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leo Duran <leo.duran@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuFeatures: Change CPU features name to follow IA32 SDMJeff Fan2017-04-071-2/+2
| | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuFeatures: Change files format to DOSJeff Fan2017-04-053-570/+570
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/MtrrLib: Add CacheInvalid enum type to MtrrLib.hRuiyu Ni2017-03-311-1/+2
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/MtrrLib: Correct typo in comments and remove TABsRuiyu Ni2017-03-311-7/+7
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix the function header issuesJeff Fan2017-03-281-29/+31
| | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO addressJeff Fan2017-03-271-5/+7
| | | | | | | | | | | | | | | | | | | The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB. This update on CPU_REGISTER_TABLE_ENTRY is to add additional UINT32 field HighIndex to indicate the high 32bit MMIO address and original Index still indicate the low 32bit MMIO address. This update makes use of original padding space between ValidBitLength and Value to add HighIndex. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64Jeff Fan2017-03-271-2/+2
| | | | | | | | | | | | | | The input parameter Index of PreSmmCpuRegisterTableWrite() and CpuRegisterTableWrite() is defined as UINT32. Index is MSR/MMIO address that will be saved in CPU register table. UINT32 blocks the MMIO address > 4GB. This fix is to define Index to UINT64 instead of UINT32. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/Include/Library: Add Register CPU Features LibraryJeff Fan2017-03-221-0/+516
| | | | | | | | | | | | | | | | | Register CPU Features Library is used to register/manage/program CPU features. NULL CPU features library instance could consume it register CPU features functions. CPU Feature module could consume this library to detect/analysis/program CPU features on BSP/APs. v4: Fix GCC build issue. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuidJeff Fan2017-03-221-0/+26
| | | | | | | | | | | | | | | | GUID gEdkiiCpuFeaturesInitDoneGuid is used to indicate if CPU features have been initialized. On PEI phase, one gEdkiiCpuFeaturesInitDoneGuid PPI will be installed after CPU features initialized. On DXE phase, one gEdkiiCpuFeaturesInitDoneGuid Protocol will be installed after CPU features initialized. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuidJeff Fan2017-03-221-0/+26
| | | | | | | | | | | | | | | | GUID gEdkiiCpuFeaturesSetDoneGuid is used to indicate if CPU feature related setting are set finished. For example, PCD PcdCpuFeaturesUserConfiguration. On PEI phase, one gEdkiiCpuFeaturesSetDoneGuid PPI will be installed after platform set CPU feature setting. On DXE phase, one gEdkiiCpuFeaturesSetDoneGuid Protocol will be installed after platform set CPU feature setting. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/Msr: Add CPUID signature check MACROsJeff Fan2017-03-2220-20/+365
| | | | | | | | | | | | All model-specific MSRs are related to processor signatures that are defined in each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry typeJeff Fan2017-03-221-3/+3
| | | | | | | | | | | | | | | Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry. This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and make RegisterTableEntry is fixed length. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/ArchitecturalMsr.h: Remove non-Ascii charactersHao Wu2016-12-201-1/+1
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Add STM GUIDs, Protocols, and PCDsMichael Kinney2016-12-195-0/+1431
| | | | | | | | | | | | | | | | * Add GUIDed HOB that described MSEG region in SMRAM * Add SM Monitor Init Protocol * Add PCD to configure size of SMM exception stack * Add PCD to configure MSEG region size if it is not described by the gMsegSmramGuid GUIDed HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Include: Update MSEG structure commentsMichael Kinney2016-12-191-3/+22
| | | | | | | | | | | | | Add comments to describe fields of MSEG_HEADER and add define values for the MonitorFeatures field. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)Hao Wu2016-12-161-116/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update CPUID leaf and sub-leaf indexes and structures as described by Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, September 2016, CPUID instruction. Summary of incompatible changes: 1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed from 'PQE' to 'RDT_A'. 2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring Information' related definitions Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to 'CPUID_INTEL_RDT_MONITORING'. Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'. 3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement Information' related definitions Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'. This commit also updates the relating codes in UefiCpuPkg/Application/Cpuid to reflect the changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)Hao Wu2016-12-162-1/+2517
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Add the MSR header file of Goldmont processor according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)Hao Wu2016-12-161-20/+1169
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update the MSR header file of Skylake processor according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15. Summary of incompatible changes: 1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to IA32_PERF_GLOBAL_STATUS Typo 'STAUS' has been fixed in SDM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)Hao Wu2016-12-1619-2656/+1312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update MSR header files of processors (excluding Goldmont and Skylake processors) according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR). Summary of incompatible changes: General: 1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header files has been removed or renamed to IA32_PERF_GLOBAL_STATUS Typo 'STAUS' has been fixed in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. 2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS) in processor-specific header files have been removed or renamed to IA32_MC{X}_{XXX} (like IA32_MC4_STATUS) Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in SDM are still kept in processor-specific header files. HaswellMsr.h: 1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE' in SDM. Since the MSR definition is the same with architectural MSR, we remove it. SandyBridgeMsr.h: 1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields 0:3 Bit description change from 'Core {X} select' to 'Slice {X} select' for bit 0:3 in SDM. SilvermontMsr.h: 1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed Bit description for this MSR is totally changed in SDM, we modify the structure definition to align with it. XeonDMsr.h: 1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY and MSR_PKG_C10_RESIDENCY have been removed Those 3 MSRs are not defined for this processor in SDM, we remove them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Make the comments align with the functionsDandan Bi2016-12-141-2/+2
| | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Include: Add VMX MSR register structuresMichael Kinney2016-12-011-5/+219
| | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=279 Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER structures with the bit fields for these two MSRs. Also add MSEG_HEADER structure whose base address is in the MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Include: Add MicrocodeFlashAccessLib header.Jiewen Yao2016-11-081-0/+39
| | | | | | | | | | | | | | | | This library is used to abstract microcode flash region access. This library is consumed by a microcode capsule update module. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Include: Add Microcode FMP definition.Jiewen Yao2016-11-081-0/+21
| | | | | | | | | | | | | | | It defined ImageTypeId for Microcode. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/LocalApicLib: Add EFIAPI for GetProcessorLocationByApicId()Jeff Fan2016-11-021-0/+1
| | | | | | | | | | | | We need to add EFIAPI for all interface service including library API. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leo Duran <leo.duran@amd.com> Cc: Michael Kinney <Michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
* UefiCpuPkg/LocalApicLib: Rename GetProcessorLocation()Jeff Fan2016-11-021-1/+1
| | | | | | | | | | | | | | | | GetProcessorLocation() is too generic and will conflict with the API defined in Galileo Board Software Package v1.0.0. This update is just to rename GetProcessorLocation() to one specific name GetProcessorLocationByApicId(). Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leo Duran <leo.duran@amd.com> Cc: Michael Kinney <Michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
* UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib libraryLeo Duran2016-11-011-0/+20
| | | | | | | | | | | | | 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. 2) Remove ExtractProcessorLocation() from MpInitLib library. 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Fix typos in commentsGary Lin2016-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | - excute -> execute - Retrive -> Retrieve - possilbe -> possible - CONTINOUS -> CONTINUOUS - storgage -> storage - allcated -> allocated - triggerred -> triggered - paramter -> parameter - perodically -> periodically - retore -> restore v2: - ruturn -> return Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Cpuid: Remove wrong while-loop check after for-loopJeff Fan2016-10-181-2/+1
| | | | | | | | | | | | | | | while-loop check should not co-exist with for-loop. This should be typo when we check-in the original code. We should keep one loop only. This issue caused CLANG38 build failure reported by https://tianocore.acgmultimedia.com/show_bug.cgi?id=148 Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
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