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* UefiCpuPkg: Add CpuLib to module INFs that depend on UefiCpuLib.Yu Pu2022-05-061-0/+1
| | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build failure, add CpuLib dependency to all modules that depend on UefiCpuLib. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Apply uncrustify changesMichael Kubacki2021-12-071-135/+149
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Change complex DEBUG_CODE() to DEBUG_CODE_BEGIN/END()Michael D Kinney2021-12-071-2/+2
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3767 Update use of DEBUG_CODE(Expression) if Expression is a complex code block with if/while/for/case statements that use {}. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Move StandardSignatureIsAuthenticAMD to BaseUefiCpuLibKirkendall, Garrett2020-07-071-23/+2
| | | | | | | | | | | | | | | | | | | | | Refactor StandardSignatureIsAuthenticAMD into BaseUefiCpuLib from separate copies in BaseXApicLib, BaseXApicX2ApicLib, and MpInitLib. This allows for future use of StandarSignatureIsAuthinticAMD without creating more instances in other modules. This function allows IA32/X64 code to determine if it is running on an AMD brand processor. UefiCpuLib is already included directly or indirectly in all modified modules. Complete move is made in this change. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Message-Id: <20200622131825.1352-4-Garrett.Kirkendall@amd.com>
* UefiCpuPkg: Update code to include register definitions from MdePkgNi, Ray2019-08-091-3/+3
| | | | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/LocalApicLib: Add GetProcessorLocation2ByApicId() APIRay Ni2019-04-081-1/+124
| | | | | | | | | | | GetProcessorLocation2ByApicId() extracts the package/die/tile/module/core/thread ID from the initial APIC ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-281-32/+32
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/LocalApicLib: Exclude second SendIpi sequence on AMD processors.Eric Dong2018-06-191-4/+8
| | | | | | | | | | | | | | | | | On AMD processors the second SendIpi in the SendInitSipiSipi and SendInitSipiSipiAllExcludingSelf routines is not required, and may cause undesired side-effects during MP initialization. This patch leverages the StandardSignatureIsAuthenticAMD check to exclude the second SendIpi and its associated MicroSecondDelay (200). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran <leo.duran@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: ApicLibLeo Duran2017-09-051-47/+15
| | | | | | | | | | | | | GetProcessorLocationByApicId () - Use max possible thread count to decode InitialApicId on AMD processor. - Clean-up on C Coding standards. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.Leo Duran2017-06-261-32/+125
| | | | | | | | | | Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/LocalApicLib: fix feature test for Extended Topology CPUID leafLaszlo Ersek2016-11-231-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Intel SDM (325462-060US / September 2016), > INPUT EAX = 0BH: Returns Extended Topology Information > > [...] Software must detect the presence of CPUID leaf 0BH by verifying > (a) the highest leaf index supported by CPUID is >= 0BH, and > (b) CPUID.0BH:EBX[15:0] reports a non-zero value. [...] The LocalApicLib instances in UefiCpuPkg do not perform check (b). This causes an actual bug in the following OVMF setup: - Intel W3550 host processor <http://ark.intel.com/products/39720/>, - the QEMU/KVM guest's VCPU model is set to "host", that is, "the CPU visible to the guest should be exactly the same as the host CPU". In the GetInitialApicId() function, check (a) passes: the CPUID level of the W3550 is exactly 11 decimal. However, leaf 11 itself is not supported, therefore EDX is set to zero: > If a value entered for CPUID.EAX is less than or equal to the maximum > input value and the leaf is not supported on that processor then 0 is > returned in all the registers. Because we don't check (b), we return 0 as initial APIC ID on the BSP and on all of the APs as well. Add the missing check. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/LocalApicLib: Add EFIAPI for GetProcessorLocationByApicId()Jeff Fan2016-11-021-0/+1
| | | | | | | | | | | | We need to add EFIAPI for all interface service including library API. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leo Duran <leo.duran@amd.com> Cc: Michael Kinney <Michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
* UefiCpuPkg/LocalApicLib: Rename GetProcessorLocation()Jeff Fan2016-11-021-1/+1
| | | | | | | | | | | | | | | | GetProcessorLocation() is too generic and will conflict with the API defined in Galileo Board Software Package v1.0.0. This update is just to rename GetProcessorLocation() to one specific name GetProcessorLocationByApicId(). Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leo Duran <leo.duran@amd.com> Cc: Michael Kinney <Michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
* UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib libraryLeo Duran2016-11-011-0/+146
| | | | | | | | | | | | | 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. 2) Remove ExtractProcessorLocation() from MpInitLib library. 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitionsJeff Fan2016-08-171-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | #define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h. Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from ArchitecturalMsr.h. v5: 1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: LocalApicLib: Add API to set SoftwareEnable bitMichael Kinney2015-10-301-4/+34
| | | | | | | | | | | | | | | The LocalApicLib does not provide a function to manage the state of the Local APIC SoftwareEnable bit in the Spurious Vector register. There are cases where this bit needs to be managed without side effects to. other Local APIC registers. One use case is in the DebugAgent in the SourceLevelDebugPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18711 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Add Cpuid.h include files for CPUID related definesMichael Kinney2015-10-191-0/+1
| | | | | | | | | | | | Move CPUID related defines from LocalApic.h to Cpuid.h Update LocalApicLib instances to include Cpuid.h Update CpuMpPei module to include Cpuid.h Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18633 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg BaseXApic(X2)Lib: Add ASSERT if local APIC not software enabledHao Wu2015-10-091-0/+9
| | | | | | | | | | | Add an ASSERT in GetApicTimerState() to check if the local APIC is software enabled. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18595 6f19259b-4bc3-4df7-8a09-765794883524
* MdePkg/BaseXApicLib: Support IA32 processors without MSR_IA32_APIC_BASE_ADDRESSMichael Kinney2015-04-271-9/+57
| | | | | | | | | | | | | Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS). If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17216 6f19259b-4bc3-4df7-8a09-765794883524
* 1. Save/restore ICR high 32bit value and check Delivery Status before ↵Jeff Fan2014-07-111-0/+32
| | | | | | | | | | | | | | | sending IPI. It could be fix the interrupted issue between ICR high/low writes by SMI handler. 2. Save/restore CPU Interrupt state around sending IPI. It could avoid sending IPI be interrupted by CPU interrupt handler. 3. Add note for SetApicMode() API that must not be called from an interrupt handler or SMI handler. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com> Reviewed-by: Mudusuru, Giri <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15652 6f19259b-4bc3-4df7-8a09-765794883524
* Introduce one PCD PcdCpuInitIpiDelayInMicroSeconds to specify the delay ↵Jeff Fan2014-07-101-3/+3
| | | | | | | | | | | | | | value after sending out INIT IPI instead of hard code 10 MicroSeconds. Its default value is 10 millisecond per IA32 manual. Platform could customize this PCD value for performance requirement. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15650 6f19259b-4bc3-4df7-8a09-765794883524
* 1. Read 32bit CPU Init APIC ID from CPUID leaf B in XAPIC mode.Jeff Fan2013-09-161-5/+28
| | | | | | | | | 2. Read CPU APIC ID from CPUID leaf B in case CPU Init APIC ID is larger 255 in XAPIC mode. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14674 6f19259b-4bc3-4df7-8a09-765794883524
* 1. Added SetLocalApicBaseAdress() and GetLocalApicBaseAddress() APIs in ↵vanjeff2012-08-231-4/+49
| | | | | | | | | | | | | | | | Local APIC library. 2. Updated Local APIC library instances to get Local APIC base Address by invoking GetLocalApicBaseAddress() instead of by PCD PcdCpuLocalApicBaseAddress. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com> Reviewed-by: Rui Sun <rui.sun@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13668 6f19259b-4bc3-4df7-8a09-765794883524
* Add generic HPET Timer DXE Driver and support librariesmdkinney2011-09-021-1/+78
| | | | | | | Signed-off-by: mdkinney Reviewed-by: li-elvin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12259 6f19259b-4bc3-4df7-8a09-765794883524
* Add DisableLvtInterrupts() for the Local APIC library class.rsun32010-08-271-0/+22
| | | | git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10827 6f19259b-4bc3-4df7-8a09-765794883524
* Improve Local APIC library class. Add new library APIs: GetApicVersion(), ↵rsun32010-08-261-25/+106
| | | | | | SendFixedIpi(), SendFixedIpiAllExcludingSelf(), GetApicTimerState(). Remove GetApicTimerDivisor (), its functionality can be covered by GetApicTimerState(). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10824 6f19259b-4bc3-4df7-8a09-765794883524
* Add Local APIC Library class defining APIs for common Local APIC operations. ↵rsun32010-08-231-0/+574
Add two Local APIC library instances, one is for xAPIC mode only, the other is for x2APIC capable processors which have xAPIC and x2APIC modes. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10814 6f19259b-4bc3-4df7-8a09-765794883524
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