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* UefiCpuPkg/LocalApicLib: Exclude second SendIpi sequence on AMD processors.Eric Dong2018-06-192-8/+16
| | | | | | | | | | | | | | | | | On AMD processors the second SendIpi in the SendInitSipiSipi and SendInitSipiSipiAllExcludingSelf routines is not required, and may cause undesired side-effects during MP initialization. This patch leverages the StandardSignatureIsAuthenticAMD check to exclude the second SendIpi and its associated MicroSecondDelay (200). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran <leo.duran@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Remove X86 ASM and S filesLiming Gao2018-06-0714-1936/+6
| | | | | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules expect for the ones in ResetVector directory. The ones in ResetVector directory are included by Vtf0.nasmb. They are also nasm style. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuCommonFeatures: Follow SDM for MAX CPUID feature detectRuiyu Ni2018-05-281-2/+2
| | | | | | | | | | | | | | | According to IA manual: "Before setting this bit (MSR_IA32_MISC_ENABLE[22]) , BIOS must execute the CPUID.0H and examine the maximum value returned in EAX[7:0]. If the maximum value is greater than 2, this bit is supported." We need to fix our current detection logic to compare against 2. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg MpInitLib: Fix typo "sCPUID" to "CPUID"Star Zeng2018-04-251-2/+2
| | | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Disable interrupt at ExitBootServices AP MwaitHao Wu2018-03-202-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Within function ApWakeupFunction(): When source level debugger is enabled, AP interrupts will be enabled by EnableDebugAgent(). Then the AP function will be executed by: Procedure (Parameter); After the AP function returns, AP interrupts will be disabled when the APs are placed in loop mode (both HltLoop and MwaiLoop). However, at ExitBootServices, ApWakeupFunction() is called with 'Procedure' equals to RelocateApLoop(). (ExitBootServices callback registered within InitMpGlobalData()) RelocateApLoop() never returns, so it has to disable the AP interrupts by itself. However, we find that interrupts are only disabled for the HltLoop case, but not for the MwaitLoop case (within file MpFuncs.nasm). This commit adds the missing disabling of AP interrupts for MwaitLoop. Also, for X64, this commit will disable the interrupts before switching to 32-bit mode. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg CpuExceptionHandlerLib: use FixedPcdGetSize() as the macro valueLiming Gao2018-03-161-3/+3
| | | | | | | | | | | | FixedPcdGetSize() is used as the macro value, PcdGetSize() is used as global variable or function. Here usage is to access macro value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Wang Jian J <jian.j.wang@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* UefiCpuPkg/MpInitLib: put mReservedApLoopFunc in executable memoryJian J Wang2018-03-081-4/+34
| | | | | | | | | | | | | | | | | | if PcdDxeNxMemoryProtectionPolicy is enabled for EfiReservedMemoryType of memory, #PF will be triggered for each APs after ExitBootServices in SCRT test. The root cause is that AP wakeup code executed at that time is stored in memory of type EfiReservedMemoryType (referenced by global mReservedApLoopFunc), which is marked as non-executable. This patch fixes this issue by setting memory of mReservedApLoopFunc to be executable immediately after allocation. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Fix coding style issueDandan Bi2018-03-081-1/+1
| | | | | | | | | | | | | Boolean values do not need to use explicit comparisons to TRUE or FALSE. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: fix incorrect init of exception stackJian J Wang2018-02-281-1/+1
| | | | | | | | | | | | | | | | | | This issue is introduced at following commit, which tried to add stack switch support on behalf of Stack Guard feature. 0ff5aa9cae1ea276668fa4398d047aa9fda3c2c7 The field KnownGoodStackTop in CPU_EXCEPTION_INIT_DATA is initialized to the start address of array mNewStack. This is wrong. It must be the end of mNewStack. This patch fixes this mistake. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabledRuiyu Ni2018-02-091-15/+17
| | | | | | | | | | | Today's McaInitialize() doesn't check State value before initialize MCi_CTL and MCi_STATUS. The patch fixes this issue by only initializing the two kinds of MSRs when State is enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttlingRuiyu Ni2018-02-081-29/+23
| | | | | | | | | | | | | | | Today's implementation only assumes SandyBridge CPU supports Extended On-Demand Clock Modulation Duty Cycle. Actually it is supported when CPUID.06h.EAX[5] == 1. When platform requests 50% throttling, it causes value 1000b set to the low-4 bits of IA32_CLOCK_MODULATION. But the wrong code sets 1000b to bits[1-3] which causes assertion. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: force flushing TLB for AP in mwait loop modeJian J Wang2018-01-291-0/+7
| | | | | | | | | | | | | | | | | | | | The reason doing this is that we found that calling StartupAllAps() to flush TLB for all APs in CpuDxe driver after changing page attributes will spend a lot of time to complete. If there are many page attributes update requests, the whole system performance will be slowed down explicitly, including any shell command and UI operation. The solution is removing the flush operation for AP in CpuDxe driver. Since TLB is always flushed in HLT loop mode, we just need to enforce a TLB flush for mwait loop mode. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: fix AP init issue in 64-bit PEIJian J Wang2018-01-291-4/+5
| | | | | | | | | | | | | | | | | | | | This issue is introduced by a patch at f32bfe6d061420a15bac6083063d227c567e6388 The above patch miss the case of 64-bit PEI, which will link X64/MpFuncs.nasm instead of Ia32/MpFuncs.nasm. For X64/MpFuncs.nasm, ExchangeInfo->ModeHighMemory should be always initialized no matter if separate wakeup buffer is allocated or not. Ia32/MpFuncs.nasm will not need ModeHighMemory during AP init. So the changes made in this patch should not affect the functionality of it. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: Make sure AP uses correct StartupApSignalStar Zeng2018-01-261-0/+9
| | | | | | | | | | | | | | | | Every processor's StartupApSignal is initialized in MpInitLibInitialize() before calling CollectProcessorCount(). When SortApicId() is called from CollectProcessorCount(), AP Index is re-assigned by APIC ID. But SortApicId() forgets to set the correct StartupApSignal when sorting the AP. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com>
* UefiCpuPkg/CpuExceptionHandler: Init serial port before context dumpRuiyu Ni2018-01-262-2/+10
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/MpInitLib: fix issue in wakeup buffer initializationJian J Wang2018-01-252-10/+11
| | | | | | | | | | | | | | | | | | | | To fix an issue in which enabling NX feature will mark the AP wakeup buffer as non-executable and fail the AP init, the buffer was split into two part: the lower part in memory within 1MB and the higher part within allocated executable memory (EfiBootServicesCode). But the address of higher part memory was stored in lower part memory, which is actually shared with legacy components and will be overwritten by LegacyBiosDxe driver if CSM is enabled. This patch fixes this issue by storing the address of higher part memory in CpuMpData instead of ExchangeInfo. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MtrrLib: Add comments to recommend to use batch-set APIRuiyu Ni2018-01-241-0/+10
| | | | | | | | | | | | | MtrrSetMemoryAttributesInMtrrSettings() is a batch-set API. When setting multiple ranges of memory attributes, the single-set API (MtrrSetMemoryAttributeInMtrrSettings and MtrrSetMemoryAttribute) may fail, but batch-set API may succeed. Add comments to recommend caller to use batch-set API when setting multiple ranges. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/MtrrLib: Update the comments for RETURN_BUFFER_TOO_SMALLRuiyu Ni2018-01-241-2/+6
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/PeiMpLib: Fix a system hang-in-pei issue.Ruiyu Ni2018-01-241-12/+11
| | | | | | | | | | | | | | | | | | GetWakeupBuffer() tries to find a below-1M free memory, it checks whether the memory is allocated already in CheckOverlapWithAllocatedBuffer(). When there is a memory allocation hob (base = 0xff_00000000, size = 0x10000000), CheckOverlapWithAllocateBuffer() truncates the base to 0 which causes it always returns TRUE so GetWakeupBuffer() fails to find a below-1MB memory. The patch fixes this issue by using UINT64 type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg/CpuExceptionHandlerLib: alloc code memory for exception handlersJian J Wang2018-01-181-4/+14
| | | | | | | | | | | | | | | | | | | If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiBootServicesData, EfiConventionalMemory, the BIOS will reset after timer initialized and started. The root cause is that the memory used to hold the exception and interrupt handler is allocated with type of EfiBootServicesData and marked as non-executable due to NX feature enabled. This patch fixes it by allocating EfiBootServicesCode type of memory for those handlers instead. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: split wake up buffer into two partsJian J Wang2018-01-188-49/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiBootServicesCode, EfiConventionalMemory, the BIOS will hang at a page fault exception during MP initialization. The root cause is that the AP wake up buffer, which is below 1MB and used to hold both AP init code and data, is type of EfiConventionalMemory (not really allocated because of potential conflict with legacy code), and is marked as non-executable. During the transition from real address mode to long mode, the AP init code has to enable paging which will then cause itself a page fault exception because it's just running in non-executable memory. The solution is splitting AP wake up buffer into two part: lower part is still below 1MB and shared with legacy system, higher part is really allocated memory of BootServicesCode type. The init code in the memory below 1MB will not enable paging but just switch to protected mode and jump to higher memory, in which the init code will enable paging and switch to long mode. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Fix timer interrupt is disabled after SwitchBSPRuiyu Ni2018-01-181-0/+1
| | | | | | | | | | | | | | Commits a2ea6894e6ca95e8d7a254593661a79e4b988626 * UefiCpuPkg/MpInitLib: Fix a bug that AP enters timer INT handler masked the interrupts in AP. But it didn't unmask the interrupt in new BSP when Switch BSP happens. The patch fixed this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Cc: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chainLiming Gao2018-01-165-22/+52
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=849 In V2, use "mov rax, strict qword 0" to replace the hard code db. 1. Use lea instruction to get the address instead of mov instruction. 2. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chainLiming Gao2018-01-161-7/+20
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=849 In V2, use mov rax, strict qword 0 to replace the hard code db. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Enhance feature dependency checkSong, BinX2018-01-151-0/+3
| | | | | | | | | | Enhance MCA feature dependency check base on SDM pseudocode example 15-1. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: fix 32-bit build errorJian J Wang2018-01-111-1/+1
| | | | | | | | | | Cc: Dandan Bi <dandan.bi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/MtrrLib: Fix an assertion bugRuiyu Ni2018-01-111-1/+0
| | | | | | | | | | | | | | | | | | | | 0 40 f0 100 +---WT--+--UC--+--WT--+-----WB----+----UC----+ When calculating the shortest path from 0 to 100, the MtrrLibCalculateLeastMtrrs() is called to update the Vertices.Previous. When calculating the shortest path from 0 to 40, MtrrLibCalculateLeastMtrrs() is called recursively to update the Vertices.Previous. The second call corrupt the Previous value that will be used later. The patch removes the code that corrupts Previous. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Fix a MTRR calculation bugRuiyu Ni2018-01-111-4/+5
| | | | | | | | | | | | | | | | 80 A8 B0 B8 C0 +----------WB--------+-UC-+-WT-+-WB-+ For above memory settings, current code caused the final MTRR settings miss [A8, B0, UC] when default memory type is UC. The root cause is the code only checks the mandatory weight between A8 to B0, but skips to check the optional weight. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Correct typo to change vector to vertexRuiyu Ni2018-01-101-95/+95
| | | | | | | | | | The patch only change the comments and variable name so doesn't impact the functionality. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/MtrrLib: Handle one setting request covering all memoryRuiyu Ni2018-01-101-1/+6
| | | | | | | | | | | *SetMemoryAttribute*() API cannot handle the setting request that looks like <0, MAX_ADDRESS, Type>. The buggy parameter checking logic returns Unsupported for this case. The patch fixes the checking logic to handle such case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Fix bug that may calculate wrong MTRR resultRuiyu Ni2018-01-101-12/+25
| | | | | | | | | | | | | Code forgot to initialize the optional weight between adjacent vertices. It caused wrong MTRR result was calculated for some memory settings. The logic was incorrectly removed when converting from POC code. The patch adds back the initialization. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Refine the debug messagesRuiyu Ni2018-01-101-30/+53
| | | | | | | | | | | | | MtrrSetMemoryAttributesInMtrrSettings() missed the debug messages of memory attribute request and status. The patch moves all debug messages from MtrrSetMemoryAttributeInMtrrSettings() to MtrrSetMemoryAttributesInMtrrSettings() and refines the debug message to carry more information. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/MpInitLib: fix wrong address set as Stack Guard for APsJian J Wang2018-01-101-1/+18
| | | | | | | | | | | | | | The reason is that DXE part initialization will reuse the stack allocated at PEI phase, if MP was initialized before. Some code added to check this situation and use stack base address saved in HOB passed from PEI. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: fix incorrect stack top init for cpu0Jian J Wang2018-01-101-1/+1
| | | | | | | | | | | | | | | | As the name suggests, CpuMpData->CpuInfoInHob[0].ApTopOfStack must be init to the top of stack. But the MpInitLibInitialize() passed the base address of stack to InitializeApData(), which is not correct. Although this stack is not used for BSP, it's should be fixed in case of misunderstanding and future possible code changes. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Fix a bug that AP enters timer INT handlerRuiyu Ni2018-01-091-1/+5
| | | | | | | | | | When SourceLevelDebug is enabled, AP randomly executes the DXECORE timer handler logic. The root cause is the interrupts are not masked in AP wake up procedure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg CpuExceptionHandlerLib: Enhance DumpModuleImageInfo()Star Zeng2018-01-023-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Enhance DumpModuleImageInfo() for page fault with I/D set. If it is page fault with I/D set, the (E/R)IP in SystemContext could not be used for DumpModuleImageInfo(), instead of, the next IP of the IP triggering this page fault could be found from stack by (E/R)SP in SystemContext. IA32 SDM: — I/D flag (bit 4). This flag is 1 if the access causing the page-fault exception was an instruction fetch. This flag describes the access causing the page-fault exception, not the access rights specified by paging. The idea comes from SmiPFHandler () in UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c and UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Fix comment typo for MtrrLibApplyFixedMtrrs functionSong, BinX2017-12-281-1/+1
| | | | | | | | | | Fix comment typo for MtrrLibApplyFixedMtrrs function Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Rollback field name changesJian J Wang2017-12-273-16/+16
| | | | | | | | | Roll back commit 56649f43013703e95f54c293d708152b765cc49b. The original names follows the spec definition. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Update AESNI support checking logicSong, BinX2017-12-271-9/+11
| | | | | | | | | | | | | | With correct model CPU, current checking logic will always execute AsmReadMsr64 operation and then check ECX.AESNI[bit 25] = 1. Update checking logic to check ECX.AESNI[bit 25] = 1 first and then do AsmReadMsr64 operation. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Delete redundant PcdGetSize PcdCpuFeaturesSupportSong, BinX2017-12-271-1/+0
| | | | | | | | | | | | | When CpuCommonFeaturesLib use RegisterCpuFeaturesLib to register CPU features, the CpuFeaturesData->BitMaskSize has already been initialized. So delete redundant PcdGetSize PcdCpuFeaturesSupport in CpuInitDataInitialize. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* Revert "UefiCpuPkg: Check invalid RegisterCpuFeature parameter"Eric Dong2017-12-271-29/+0
| | | | | | | | | | | This reverts commit 5c59537c1092a1372913274636a8d766fdd97e61. Current code already has function IsCpuFeatureSupported to do the feature validation, not need this check logic anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Update code to use new structure field namesJian J Wang2017-12-263-16/+16
| | | | | | | | | | | | Due to coding style fix of the structure definition in BaseLib.h, all code referencing those structure must be updated accordingly. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/MpInitLib: Add missing Guard page setup for APsJian J Wang2017-12-222-3/+32
| | | | | | | | | | | | | | AP has its own stack for code execution. If PcdCpuStackGuard is enabled, the page at the bottom of stack of AP will be disabled (NOT PRESENT) to monitor the stack overflow issue. This requires PcdCpuApStackSize to be set with value more than one page of memory. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Singularize function nameSong, BinX2017-12-152-28/+28
| | | | | | | | | | | Change GetSupportPcds and GetConfigurationPcds to be singular Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Check invalid RegisterCpuFeature parameterSong, BinX2017-12-131-0/+29
| | | | | | | | | | | | | | V2: Update function name, add more detail description. V1: Check and assert invalid RegisterCpuFeature function parameter Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MtrrLib: Correct debug messageRuiyu Ni2017-12-111-1/+1
| | | | | | | | | | | | | | When printing the ascii format of memory attribute in debug message, %s was used, but %a should be used. The patch additionally changes %x to %r for EFI_STATUS. The whole patch doesn't impact functionality of the MtrrLib. Just debug message fix. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP dataJian J Wang2017-12-082-0/+20
| | | | | | | | | | | | | | | | | | In current implementation of CPU MP service, AP is initialized with data copied from BSP. Stack switch required by Stack Guard feature needs different GDT, IDT table and task gates for each logic processor. This patch adds GDTR, IDTR and TR into structure CPU_VOLATILE_REGISTERS and related code in save and restore methods. This can make sure that any changes to GDT, IDT and task gate for an AP will be kept from overwritten by BSP settings. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch supportJian J Wang2017-12-0814-3/+984
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If Stack Guard is enabled and there's really a stack overflow happened during boot, a Page Fault exception will be triggered. Because the stack is out of usage, the exception handler, which shares the stack with normal UEFI driver, cannot be executed and cannot dump the processor information. Without those information, it's very difficult for the BIOS developers locate the root cause of stack overflow. And without a workable stack, the developer cannot event use single step to debug the UEFI driver with JTAG debugger. In order to make sure the exception handler to execute normally after stack overflow. We need separate stacks for exception handlers in case of unusable stack. IA processor allows to switch to a new stack during handling interrupt and exception. But X64 and IA32 provides different ways to make it. X64 provides interrupt stack table (IST) to allow maximum 7 different exceptions to have new stack for its handler. IA32 doesn't have IST mechanism and can only use task gate to do it since task switch allows to load a new stack through its task-state segment (TSS). The new API, InitializeCpuExceptionHandlersEx, is implemented to complete extra initialization for stack switch of exception handler. Since setting up stack switch needs allocating new memory for new stack, new GDT table and task-state segment but the initialization method will be called in different phases which have no consistent way to reserve those memory, this new API is allowed to pass the reserved resources to complete the extra works. This is cannot be done by original InitializeCpuExceptionHandlers. Considering exception handler initialization for MP situation, this new API is also necessary, because AP is not supposed to allocate memory. So the memory needed for stack switch have to be reserved in BSP before waking up AP and then pass them to InitializeCpuExceptionHandlersEx afterwards. Since Stack Guard feature is available only for DXE phase at this time, the new API is fully implemented for DXE only. Other phases implement a dummy one which just calls InitializeCpuExceptionHandlers(). Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg: SmmCpuFeaturesLib Add the missing ASM_PFX in nasm codeLiming Gao2017-12-081-3/+3
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib:Make function comments align with functionDandan Bi2017-11-021-1/+1
| | | | | | | Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-10 01:32:43 +0000