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* UefiCpuPkg/MpInitLib: Reuse VMSA allocation to avoid unreserved allocationLendacky, Thomas via groups.io2023-04-011-77/+121
| | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4353 When parking the APs on exiting from UEFI, a new page allocation is made. This allocation, however, does not end up being marked reserved in the memory map supplied to the OS. To avoid this, re-use the VMSA by clearing the VMSA RMP flag, updating the page contents and re-setting the VMSA RMP flag. Fixes: 06544455d0d4 ("UefiCpuPkg/MpInitLib: Use SEV-SNP AP Creation ...") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable caseRay Ni2023-04-013-33/+107
| | | | | | | | | | | | | | | | When TME-MK is enabled, the MtrrLib should substract the TME-MK reserved bits from the max PA returned from CPUID instruction. The new test case guarantees such behavior in MtrrLib. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/MtrrLib: Substract TME-MK KEY_ID_BITS from CPU max PARay Ni2023-04-011-2/+22
| | | | | | | | | | | | | | | | | | CPUID enumeration of MAX_PA is unaffected by TME-MK activation and will continue to report the maximum physical address bits available for software to use, irrespective of the number of KeyID bits. So, we need to check if TME is enabled and adjust the PA size accordingly. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/MtrrTest: Only claim CPUID max leaf as 1Ray Ni2023-04-011-1/+8
| | | | | | | | | | | | | | | MtrrLib code queries the CPUID leaf 7h result if support. Update Test code temporary to claim the CPUID only supports max leaf as 1 so MtrrLib skips to query CPUID leaf 7h. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Test: Disable random test casesRay Ni2023-03-311-10/+10
| | | | | | | | | | | | The random test cases just run for too long that may cause timeout in CI test. Disable them for now. Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* UefiCpuPkg/CpuPageTableLib: Reduce the number of random testsDun Tan2023-03-271-5/+5
| | | | | | | | | | | | | | Reduce the number of random tests. In previous patch, non-1:1 mapping is enbaled and it may need more than an hour and a half for the CI test, which may lead to CI timeout. Reduce the number of random test count to pass the CI. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE pagingDun Tan2023-03-273-6/+11
| | | | | | | | | | | Add RandomTest for PAE paging. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Enable PAE pagingDun Tan2023-03-273-11/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Combine branch for non-present and leaf ParentEntryDun Tan2023-03-271-53/+32
| | | | | | | | | | | | | Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add check for page table creationDun Tan2023-03-271-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Modify UnitTest code since tested API is changedZhiguang Liu2023-03-273-59/+67
| | | | | | | | | | | | Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.infZhiguang Liu2023-03-272-73/+74
| | | | | | | | | | | | | | | | | | | The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModifiedDun Tan2023-03-271-12/+33
| | | | | | | | | | | | | | Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.Dun Tan2023-03-274-45/+85
| | | | | | | | | | | | | Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random testDun Tan2023-03-271-4/+4
| | | | | | | | | | | | | | Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/AttrDun Tan2023-03-272-26/+133
| | | | | | | | | | | | | | | | | | | | | Modify RandomTest to check invalid input. When creating new page table or updating exsiting page table: 1.If set [LinearAddress, LinearAddress+Length] to non-present, all other attributes should not be provided. 2.If [LinearAddress, LinearAddress+Length] contain non-present range, the Returnstatus of PageTableMap() should be InvalidParameter when: 2.1Some of attributes are not provided when mapping non-present range to present. 2.2Set any other attribute without setting the non-present range to Present. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Add LastMapEntry pointerDun Tan2023-03-271-8/+10
| | | | | | | | | | | Add LastMapEntry pointer to replace MapEntrys->Maps[MapsIndex] in SingleMapEntryTest () of RandomTest. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTestDun Tan2023-03-271-22/+21
| | | | | | | | | | | | | | Add an input parameter to control the probability of returning true. Change RandomBoolean() in RandomTest from 50% chance returning true to returning true with the percentage of input Probability. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and AttrDun Tan2023-03-271-2/+127
| | | | | | | | | | | | | | | | | | | | Add manual test case to check input Mask and Attribute. The check steps are: 1.Create Page table to cover [0, 2G]. All fields of MapMask should be set. 2.Update Page table to set [2G - 8K,2G] from present to non-present. All fields of MapMask except present should not be set. 3.Still set [2G - 8K, 2G] as not present, this case is permitted. But set [2G - 8K, 2G] as RW is not permitted. 4.Update Page table to set [2G - 8K, 2G] as present and RW. All fields of MapMask should be set. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Add check for Mask and AttrDun Tan2023-03-271-1/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Add code to initialize MapMaskDun Tan2023-03-271-4/+1
| | | | | | | | | | | | | In function CreatePageTable(), add code to initialize MapMask to MAX_UINT64. When creating new page table or map non-present range to present, all attributes should be provided. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entryDun Tan2023-03-271-8/+11
| | | | | | | | | | | | | | | | | | When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leafDun Tan2023-03-271-1/+2
| | | | | | | | | | | | | Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle. This function is used to set non-leaf entry attributes so it should make sure that the PageSize bit of the entry should be 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issueDun Tan2023-03-271-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginningDun Tan2023-03-271-9/+12
| | | | | | | | | | | | Move some local variable initialization to the beginning of the function. Also delete duplicated calculation for RegionLength. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add check for input LengthDun Tan2023-03-271-1/+5
| | | | | | | | | | | | Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' conditionDun Tan2023-03-271-10/+1
| | | | | | | | | | | | | | Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present == 0) is always FALSE. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Solve that stack top address is not mapped in pagetableXie, Yuanhao2023-03-271-0/+1
| | | | | | | | | | | | | For the case CPU logic index is 0, RSP points to the very top of all AP stacks. That address is not mapped in page table. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-107-7/+0
| | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg: Move API and implementation from UefiCpuLib to CpuLibYu Pu2023-03-105-207/+19
| | | | | | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib. Change-Id: Ic26f4c2614ed6bd9840f817d50e47ac1de4bd013 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean upAndrei Warkentin2023-03-083-40/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RegisterCpuInterruptHandler did not allow setting exception handlers for anything beyond the timer IRQ. Beyond that, it didn't meet the spec around handling of inputs. RiscVSupervisorModeTrapHandler now will invoke set handlers for both exceptions and interrupts. Two arrays of handlers are maintained - one for exceptions and one for interrupts. For unhandled traps, RiscVSupervisorModeTrapHandler dumps state using the now implemented DumpCpuContext. For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped PC address (SEPC), just like on AArch64 (ELR). This is necessary for X86EmulatorPkg to work as it allows a trap handler to return execution to a different place. Add SSTATUS/STVAL as well, at least for debugging purposes. There is no value in hiding this. Fix nested exception handling. Handler code should not be saving SIE (the value is saved in SSTATUS.SPIE) or directly restored (that's done by SRET). Save and restore the entire SSTATUS and STVAL, too. Cc: Daniel Schaefer <git@danielschaefer.me> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* UefiCpuPkg: Calculate DisplayFamily correctlyLiu, Zhiguang2023-03-071-3/+3
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4348 Per SDM: DisplayFamily = Extended_Family_ID + Family_ID. DisplayModelID = (Extended_Model_ID << 4) + Family_ID. Correct the related code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasmXie, Yuanhao2023-03-072-169/+170
| | | | | | | | | | | | Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Rename AsmRelocateApLoopStart.Yuanhao Xie2023-03-074-28/+28
| | | | | | | | | | | | | | Rename AsmRelocateApLoopStart to AsmRelocateApLoopStartAmdSev Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Put APs in 64 bit mode before handoff to OS.Xie, Yuanhao2023-03-078-49/+273
| | | | | | | | | | | | | | | | | | | | | | | Add the 'AsmRelocateApLoopStartGeneric' for X64 processors except 64-bit AMD processors with SEV-ES. Remove the unused arguments of AsmRelocateApLoopStartGeneric, updated the stack offset. Create PageTable for the allocated reserved memory. Only keep 4GB limitation of memory allocation for the case APs still need to be transferred to 32-bit mode before OS. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Allocate contiguous memory for stacks and APs loop.Xie, Yuanhao2023-03-071-23/+17
| | | | | | | | | | | | Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Split the path in RelocateApLoop into two.Xie, Yuanhao2023-03-072-28/+48
| | | | | | | | | | | | | | | | | | Add the union RELOCATE_AP_LOOP_ENTRY, split the path in RelocateApLoop into two: 1. 64-bit AMD processors with SEV-ES 2. Intel processors (32-bit or 64-bit), 32-bit AMD processors, or 64-bit AMD processors without SEV-ES. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Check AP_SAFE_STACK_SIZE during build time.Xie, Yuanhao2023-03-071-1/+2
| | | | | | | | | | | | | | | | | Check if AP_SAFE_STACK_SIZE is aligned with CPU_STACK_ALIGNMENT during build time. No functional or structural changes. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Skip SMBASE configurationWu, Jiaxin2023-03-066-9/+36
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add BaseRiscV64CpuTimerLib librarySunil V L2023-02-163-0/+246
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add the RISC-V instance of the TimerLib. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Abner Chang <abner.chang@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLibSunil V L2023-02-165-0/+409
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add Cpu Exception Handler library for RISC-V. This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Abner Chang <abner.chang@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@Intel.com>
* Revert "UefiCpuPkg: Duplicated AsmRelocateApLoop as AsmRelocateApLoopAmd"Yuanhao Xie2023-01-095-235/+20
| | | | | | | | | | | | | This reverts commit 7bda8c648192d76f7b3f7cee54bd7b1c86a6a84f. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4234 Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
* Revert "UefiCpuPkg: Has APs in 64 bit long-mode before booting to OS."Yuanhao Xie2023-01-096-183/+200
| | | | | | | | | | | | | This reverts commit 73ccde8f6d04a246377cabaed2875e69d4b6b719 since it results in a hang of the IA32 processor and needs further clean-up. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4234 Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: drop obsolete API implementationLaszlo Ersek2023-01-041-28/+0
| | | | | | | | | | | | | | | | | | | | | | | Commit 0426115b6738 ("UefiCpuPkg: Remove unused API in SmmCpuFeaturesLib.h", 2022-12-21) removed the declaration of the function SmmCpuFeaturesAllocatePageTableMemory() from the "SmmCpuFeaturesLib.h" library class header. Remove the API's (null-)implementation from UefiCpuPkg/SmmCpuFeaturesLib as well. Build-tested with: build -a IA32 -a X64 -b NOOPT -p UefiCpuPkg/UefiCpuPkg.dsc -t GCC5 Cc: Eric Dong <eric.dong@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4235 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: Has APs in 64 bit long-mode before booting to OS.Xie, Yuanhao2022-12-206-200/+183
| | | | | | | | | | | | | | | | | | | | | | During the finalization of Mp initialization before booting into the OS, depending on whether Mwait is supported or not, AsmRelocateApLoop places Aps in MWAIT-loop or HLT-loop. Since paging is necessary for long mode, the original implementation of moving APs to 32-bit was to disable paging to ensure that the booting does not crash. The current modification creates a page table in reserved memory, avoiding switching modes and reclaiming memory by OS. This modification is only for 64 bit mode. More specifically, we keep the AMD logic as the original code flow, extract and update the Intel-related code, where the APs would stay in 64-bit, and run in a Mwait or Hlt loop until the OS wake them up. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Duplicated AsmRelocateApLoop as AsmRelocateApLoopAmdYuanhao Xie2022-12-205-20/+235
| | | | | | | | AsmRelocateApLoop is replicated for future Intel Logic Extraction, further brings AP into 64-bit, and enables paging. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* OvmfPkg/UefiCpuPkg: Add CcExit prefix to the APIs of CcExitLibMin M Xu2022-11-146-23/+23
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4123 APIs which are defined in CcExitLib.h are added with the CcExit prefix. This is to make the APIs' name more meaningful. This change impacts OvmfPkg/UefiCpuPkg. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/UefiCpuPkg/UefiPayloadPkg: Rename VmgExitLib to CcExitLibMin M Xu2022-11-1418-74/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4123 VmgExitLib once was designed to provide interfaces to support #VC handler and issue VMGEXIT instruction. After TDVF (enable TDX feature in OVMF) is introduced, this library is updated to support #VE as well. Now the name of VmgExitLib cannot reflect what the lib does. This patch renames VmgExitLib to CcExitLib (Cc means Confidential Computing). This is a simple renaming and there is no logic changes. After renaming all the VmgExitLib related codes are updated with CcExitLib. These changes are in OvmfPkg/UefiCpuPkg/UefiPayloadPkg. Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Clean up header file inclusion in SmmStm.cAbner Chang2022-11-021-3/+0
| | | | | | | | | | | | | | | | BZ# 4093: Abstract SmmCpuFeaturesLib for sharing common code Remove the header files those are already included in CpuFeatureLib.h. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <abdattar@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Paul Grimes <paul.grimes@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Abstract arch dependent codeAbner Chang2022-11-026-205/+227
| | | | | | | | | | | | | | | | | | | | BZ# 4093: Abstract SmmCpuFeaturesLib for sharing common code This change stripped away the code that can be shared with other archs or vendors from Intel implementation and put in to the common file, leaves the Intel X86 implementation in the IntelSmmCpuFeatureLib. Also updates the header file and INF file. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <abdattar@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Paul Grimes <paul.grimes@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 02:20:08 +0000