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* UefiCpuPkg/PiSmmCpuDxeSmm: Free SmramRanges to save SMM spaceJeff Fan2016-11-161-0/+1
| | | | | | | | | Cc: Zeng Star <star.zeng@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Zeng Star <star.zeng@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Decrease mNumberToFinish in AP safe codeJeff Fan2016-11-154-15/+18
| | | | | | | | | | | | | | | | | | | | | We will put APs into hlt-loop in safe code. But we decrease mNumberToFinish before APs enter into the safe code. Paolo pointed out this gap. This patch is to move mNumberToFinish decreasing to the safe code. It could make sure BSP could wait for all APs are running in safe code. https://bugzilla.tianocore.org/show_bug.cgi?id=216 Reported-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Place AP to 32bit protected mode on S3 pathJeff Fan2016-11-151-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | On S3 path, we may transfer to long mode (if DXE is long mode) to restore CPU contexts with CR3 = SmmS3Cr3 (in SMM). AP will execute hlt-loop after CPU contexts restoration. Once one NMI or SMI happens, APs may exit from hlt state and execute the instruction after HLT instruction. If APs are running on long mode, page table is required to fetch the instruction. However, CR3 pointer to page table in SMM. APs will crash. This fix is to disable long mode on APs and transfer to 32bit protected mode to execute hlt-loop. Then CR3 and page table will no longer be required. https://bugzilla.tianocore.org/show_bug.cgi?id=216 Reported-by: Laszlo Ersek <lersek@redhat.com> Analyzed-by: Paolo Bonzini <pbonzini@redhat.com> Analyzed-by: Laszlo Ersek <lersek@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Put AP into safe hlt-loop code on S3 pathJeff Fan2016-11-154-2/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On S3 path, we will wake up APs to restore CPU context in PiSmmCpuDxeSmm driver. However, we place AP in hlt-loop under 1MB space borrowed after CPU restoring CPU contexts. In case, one NMI or SMI happens, APs may exit from hlt state and execute the instruction after HLT instruction. But the code under 1MB is no longer safe at that time. This fix is to allocate one ACPI NVS range to place the AP hlt-loop code. When CPU finished restoration CPU contexts, AP will execute in this ACPI NVS range. https://bugzilla.tianocore.org/show_bug.cgi?id=216 v2: 1. Make stack alignment per Laszlo's comment. 2. Trim whitespace at end of end. 3. Update year mark in file header. Reported-by: Laszlo Ersek <lersek@redhat.com> Analyzed-by: Paolo Bonzini <pbonzini@redhat.com> Analyzed-by: Laszlo Ersek <lersek@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/LocalApicLib: Rename GetProcessorLocation()Jeff Fan2016-11-021-1/+1
| | | | | | | | | | | | | | | | GetProcessorLocation() is too generic and will conflict with the API defined in Galileo Board Software Package v1.0.0. This update is just to rename GetProcessorLocation() to one specific name GetProcessorLocationByApicId(). Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leo Duran <leo.duran@amd.com> Cc: Michael Kinney <Michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
* UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib libraryLeo Duran2016-11-011-120/+6
| | | | | | | | | | | | | 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. 2) Remove ExtractProcessorLocation() from MpInitLib library. 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Consume PcdAcpiS3Enable to control the codeStar Zeng2016-09-014-0/+37
| | | | | | | | | | | | | | if PcdAcpiS3Enable is disabled, then skip S3 related logic. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move S3 related code to CpuS3.cStar Zeng2016-09-013-341/+398
| | | | | | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Revert 7503cd70fb86Jeff Fan2016-08-191-2/+2
| | | | | | | | | Revert "UefiCpuPkg/PiSmmCpuDxeSmm: Add gEfiVariableArchProtocolGuid dependency" This reverts commit 7503cd70fb864a5663edb121c9b2488b4c69e7f5. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add gEfiVariableArchProtocolGuid dependencyJeff Fan2016-08-171-2/+2
| | | | | | | | | | | | | | | | | | | PiSmmCpuDxeSmm driver's entry point will get some PCDs supported dynamic type. In case those PCDs are set as DynamicHii type in platform DSC File, it implies that EFI Variable Arch protocol is required. This fix is to add gEfiVariableArchProtocolGuid dependency on PiSmmCpuDxeSmm driver to make sure those DynamicHii PCDs could be read correctly. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: SMM_CPU_DATA_BLOCK is not clearedJeff Fan2016-07-201-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 8b9311 changed the zeroing of mSmmMpSyncData of type SMM_DISPATCHER_MP_SYNC_DATA by the following patch. - ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize); + mSmmMpSyncData->SwitchBsp = FALSE; mSmmMpSyncDataSize not only includes SMM_DISPATCHER_MP_SYNC_DATA, but also includes the SMM_CPU_DATA_BLOCK array and one BOOLEAN variable array as shown here: mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) + (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; This patch restores the original ZeroMem() to clear all CPU Sync data. The commit 8b9311 may cause unexpected behavior. v2: Mentioned CandidateBsp array in comments to make it more accurate. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: remove superfluous ENDs from NASM sourceLaszlo Ersek2016-07-182-3/+0
| | | | | | | | | | | | | | | | | | | | Commits 28ee5816465b1 and 246cd9085f806 added these ENDs as part of the manual conversion from *.asm files. However, the ENDs makes no sense for NASM. Although they don't break the build, NASM complains about them: label alone on a line without a colon might be in error (This NASM warning category dates back to NASM 0.95, commit 6768eb71d8deb.) Remove the ENDs. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean up CheckFeatureSupported()Jeff Fan2016-07-143-60/+3
| | | | | | | | | | | | | Removed EFIAPI and parameter from CheckFeatureSupported() and removed CheckProcessorFeature() totally. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Check XD/BTS features in SMM relocationJeff Fan2016-07-142-7/+9
| | | | | | | | | | | | | | | | CheckProcessorFeature() invokes MpService->StartupAllAps() to detect XD/BTS features on normal boot path. It's not necessary and may cause performance impact, because INIT-SIPI-SIPI must be sent to APs if APs are in hlt-loop mode. XD/BTS feature detection is moved to SmmInitHandler() in SMM relocation during normal boot path. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add SMM S3 boot flagJeff Fan2016-07-141-0/+7
| | | | | | | | | | | | It will be set to TRUE during S3 resume. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add MemoryMapped in SetProcessorRegister()Jeff Fan2016-07-144-0/+27
| | | | | | | | | | | | | | | | | | REGISTER_TYPE in UefiCpuPkg/Include/AcpiCpuData.h defines a MemoryMapped enum value. However support for the MemoryMapped enum is missing from the implementation of SetProcessorRegister(). This patch adds support for MemoryMapped type SetProcessorRegister(). One spin lock is added to avoid potential conflict when multiple processor update the same memory space. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove duplicate aligned buffer on S3 pathJeff Fan2016-07-141-16/+25
| | | | | | | | | | | | | | | | | | | | InitializeMpSyncData() invokes InitializeSmmCpuSemaphores() to allocate an aligned buffer for all locks and semaphores. However, this function is invoked on S3 resume path again to reset mSmmMpSyncData. It causes an additional aligned buffer to be allocated. This update moves InitializeSmmCpuSemaphores() into InitializeMpServiceData() that is only invoked on normal boot. InitializeMpSyncData() is updated to reset the locks/semaphore in mSmmMpSyncData. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: fix ASSERT_EFI_ERROR() typosLaszlo Ersek2016-06-301-1/+1
| | | | | | | | | | | | | | | | | | | | A number of code locations use ASSERT_EFI_ERROR (BooleanExpression) instead of ASSERT (BooleanExpression) Fix them. Cc: Jeff Fan <jeff.fan@intel.com> Reported-by: Gerd Hoffmann <kraxel@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Add nasm source file into INF file.Liming Gao2016-06-281-26/+26
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmmInit.asm to NASMLiming Gao2016-06-281-0/+130
| | | | | | | Manually convert X64/SmmInit.asm to X64/SmmInit.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiException.asm to NASMLiming Gao2016-06-281-0/+412
| | | | | | | Manually convert X64/SmiException.asm to X64/SmiException.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiEntry.asm to NASMLiming Gao2016-06-281-0/+177
| | | | | | | Manually convert X64/SmiEntry.asm to X64/SmiEntry.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Update X64/MpFuncs.nasmLiming Gao2016-06-281-51/+43
| | | | | | | | | | | | | | | | | | | Use 16bit and 32bit assembly code to replace hard code db. In V2: add 0x67 prefixes to far jumps Without the a32 modifier under FLAT32_JUMP, and the a16 modifier under LONG_JUMP, nasm doesn't generate the 0x67 prefixes, and the far jumps don't work. (For the former, KVM returns an emulation failure. For the latter, KVM performs a triple fault (guest reboot).) By forcing the 0x67 prefixes we end up with the same machine code as the one open-coded in "MpFuncs.asm". This bug breaks S3 resume in the Ia32X64 + SMM_REQUIRE build of OVMF. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/MpFuncs.asm to NASMLiming Gao2016-06-281-0/+204
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert X64/MpFuncs.asm to X64/MpFuncs.nasm And, manually update it to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmmInit.asm to NASMLiming Gao2016-06-281-0/+88
| | | | | | | Manually convert Ia32/SmmInit.asm to Ia32/SmmInit.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiException.asm to NASMLiming Gao2016-06-281-0/+737
| | | | | | | Manually convert Ia32/SmiException.asm to Ia32/SmiException.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiEntry.asm to NASMLiming Gao2016-06-281-0/+163
| | | | | | | Manually convert Ia32/SmiEntry.asm to Ia32/SmiEntry.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Update Ia32/MpFuncs.nasmLiming Gao2016-06-281-26/+21
| | | | | | | | | | | | | | | | | | Use 16bit assembly code to replace hard code db. In V2: Add 0x67 prefix to far jump When we enter protected mode, with the far jump still in big real mode, the JMP instruction not only needs the 0x66 prefix (for 32-bit operand size), but also the 0x67 prefix (for 32-bit address size). Use the a32 nasm modifier to enforce this. This bug breaks S3 resume in the Ia32 + SMM_REQUIRE build of OVMF. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/MpFuncs.asm to NASMLiming Gao2016-06-281-0/+164
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/MpFuncs.asm to Ia32/MpFuncs.nasm. And, manually update it to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Using MSRs semaphores in aligned bufferJeff Fan2016-05-242-6/+30
| | | | | | | | | | | | | Update MSRs semaphores to the ones in allocated aligned semaphores buffer. If MSRs semaphores is not enough, allocate one page more. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for MSRs semaphoresJeff Fan2016-05-243-3/+20
| | | | | | | | | | | | | Allocate MSRs semaphores in allocated aligned semaphores buffer. And add it into semaphores structure. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Using CPU semaphores in aligned bufferJeff Fan2016-05-243-39/+49
| | | | | | | | | | | | | Update each CPU semaphores to the ones in allocated aligned semaphores buffer. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for each CPU semaphoresJeff Fan2016-05-242-1/+21
| | | | | | | | | | | | | Allocate each CPU semaphores in allocated aligned semaphores buffer. And add it into semaphores structure. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned bufferJeff Fan2016-05-245-45/+51
| | | | | | | | | | | | | Update all global semaphores to the ones in allocated aligned semaphores buffer. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move forward MP sync data initializationJeff Fan2016-05-241-9/+9
| | | | | | | | | | | | | | Move MP sync data initialization in front of the place that initialize page table, because the page fault spin lock is allocated in InitializeMpSyncData() while it is initialized in SmmInitPageTable(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for global semaphoresJeff Fan2016-05-242-0/+65
| | | | | | | | | | | | | Get semaphores alignment/size requirement and allocate aligned buffer for all global spin lock and semaphores. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Use public MSR_IA32_MISC_ENABLE definitionJeff Fan2016-05-164-21/+23
| | | | | | | | | | | | | | Use the MSR MSR_IA32_MISC_ENABLE definition defined in UefiCpuPkg/Include and remove the local definition. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Remove unnecessary BTS MSRsJeff Fan2016-05-162-6/+1
| | | | | | | | | | | | | | BTS used DS save area by IA32_DS_AREA MSR to get invoker IP instead of the Last Branch Record Stack. So, removed the unnecessary BTS MSRs. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Fix BTS support check bugJeff Fan2016-05-161-3/+2
| | | | | | | | | | | | | | | | | | | | | SmmProfile feature depends on BTS feature to get the invoker IP (in SMM) from last branch record. If this feature is not supported, SmmProfile cannot get the invoker IP (in SMM). Per IA-32 Architectures Software Developer's Manual, BTS feature is detected by IA32_MISC_ENABLE. If BIT11 of IA32_MISC_ENABLE is set, BTS is not supported. But current implementation check BIT11 opposite. Also, BTS feature does not depends on PEBS feature if supported or not. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Shifflett, Joseph <joseph.shifflett@hpe.com> Contributed-under: TianoCore Contribution Agreement 1.0 Reported-by: Shifflett, Joseph <joseph.shifflett@hpe.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shifflett, Joseph <joseph.shifflett@hpe.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: PiSmmCpuDxeSmm: remove set but unused variablesLaszlo Ersek2016-03-251-23/+11
| | | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Enable/Restore XD in SMMMichael Kinney2016-02-222-3/+16
| | | | | | | | | | | | | If XD is supported, then SMM enables it. The non-SMM execution environment can choose to enable or disable XD, so the state of XD must be detected in each SMI and be enabled/restored. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add EFIAPI to CheckFeatureSupported()Michael Kinney2016-02-222-6/+12
| | | | | | | | | | | | | | | The function CheckFeatureSupported() is used as an EFI_AP_PROCEDURE in the MP Services Protocol service StartAllAPs(). Any function used as an EFI_AP_PROCEDURE must use EFIAPI calling convention. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Initialize gSmst fields on S3 resumeMichael Kinney2015-12-241-0/+9
| | | | | | | | | | | | Update S3 resume path to initialize the fields of gSmst before the gSmst fields are used to complete initialization in S3 resume. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19504 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/PiSmmCpuDxeSmm: Correct CPUID leaf used to detect SMM modeMichael Kinney2015-12-241-1/+6
| | | | | | | | | | | | | Use Bit 29 of CPUID leaf CPUID_EXTENDED_CPU_SIG (0x80000001) to determine the SMM save state mode. The previous version of this code used CPUID leaf CPUID_VERSION_INFO (0x00000001). Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19503 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix failure when PcdCpuSmmDebug is TRUEMichael Kinney2015-12-241-4/+4
| | | | | | | | | | | | | | | | If PcdCpuSmmDebug is set to TRUE, then the first time the function CpuSmmDebugEntry () is called during the first normal SMI, the registers DR6 or DR7 may be set to invalid values due to gSmst not being fully initialized yet. Instead, use gSmmCpuPrivate that is fully initialized for the first SMI to look up CpuSaveState for the currently executing CPU. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19502 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Convert all .uni files to utf-8Jordan Justen2015-12-152-0/+0
| | | | | | | | | | | | | To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/PiSmmCpu: Always set WP in CR0Yao, Jiewen2015-11-304-4/+4
| | | | | | | | | | | | | | | | | | | | | | | So that we can use write-protection for code later. It is REPOST. It includes suggestion from Michael Kinney <michael.d.kinney@intel.com>: - "For IA32 assembly, can we combine into a single OR instruction that sets both page enable and WP?" - "For X64, does it make sense to use single OR instruction instead of 2 BTS instructions as well?" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Suggested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> Cc: "Paolo Bonzini" <pbonzini@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19068 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by defaultYao, Jiewen2015-11-307-26/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | So that we can use write-protection for code later. This is REPOST. It includes the bug fix from "Paolo Bonzini" <pbonzini@redhat.com>: Title: fix generation of 32-bit PAE page tables "Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table Entries (PDPTEs); see Table 4-8 in the SDM. With VMX extended page tables, the processor notices and fails the VM entry as soon as CR0.PG is set to 1." And thanks "Laszlo Ersek" <lersek@redhat.com> to validate the fix. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Signed-off-by: "Paolo Bonzini" <pbonzini@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> Cc: "Paolo Bonzini" <pbonzini@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/PiSmmCpu: Update function call for 2 new APIs.Yao, Jiewen2015-11-274-5/+59
| | | | | | | | | | | | | | | All page table allocation will use AllocatePageTableMemory(). Add SmmCpuFeaturesCompleteSmmReadyToLock() to PerformRemainingTasks() and PerformPreTasks(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18981 6f19259b-4bc3-4df7-8a09-765794883524
* Revert "Add 2 APIs in SmmCpuFeaturesLib."Laszlo Ersek2015-11-274-59/+5
| | | | | | | | | | | | | | This reverts SVN r18958 / git commit 9daa916dd1efe6443f9a66dfa882f3185d33ad28. The patch series had been fully reviewed on edk2-devel, but it got committed as a single squashed patch. Revert it for now. Link: http://thread.gmane.org/gmane.comp.bios.edk2.devel/4951 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18978 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-10 21:45:35 +0000