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* UefiCpuPkg/PiSmmCpuDxeSmm: Remove RestrictedMemoryAccess check for MM CPUJiaxin Wu2024-09-066-31/+46
| | | | | | | | | | | | | | The PcdCpuSmmRestrictedMemoryAccess is declared as either a dynamic or fixed PCD. It is not recommended for use in the MM CPU driver. Furthermore, IsRestrictedMemoryAccess() is only needed for SMM. Therefor, there is no need for MM to consume the PcdCpuSmmRestrictedMemoryAccess. So, this patch is to add the SMM specific file for its own functions, with the change, the dependency of the MM CPU driver on PcdCpuSmmRestrictedMemoryAccess can be removed. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean mCpuSmmRestrictedMemoryAccessJiaxin Wu2024-09-061-7/+4
| | | | | | | | | | Currently, mCpuSmmRestrictedMemoryAccess is only used by the IsRestrictedMemoryAccess(). And IsRestrictedMemoryAccess() can consume the PcdCpuSmmRestrictedMemoryAccess directly. Therefore, mCpuSmmRestrictedMemoryAccess can be cleaned to simply the code logic. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Update IfReadOnlyPageTableNeededJiaxin Wu2024-09-061-18/+1
| | | | | | | | | | After the 9f29fbd3, full mapping SMM page table is always created regardless the value of the PcdCpuSmmRestrictedMemoryAccess. If so, SMM PageTable Attributes can be set to ready-only since there is no need to update it. So, this patch is to remove restricted memory access check when setting the SMM PageTable attributes. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Correct SetPageTableAttributes func usageJiaxin Wu2024-09-062-12/+8
| | | | | | | | | | | SetPageTableAttributes() will use the IfReadOnlyPageTableNeeded() to determine whether it is necessary to set the page table itself to read-only. And IfReadOnlyPageTableNeeded() has already token into account the status of IsRestrictedMemoryAccess(). Therefore, there is no need for an additional call to IsRestrictedMemoryAccess() before calling the SetPageTableAttributes(). Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Deadloop if PFAddr is not supported by systemJiaxin Wu2024-09-061-1/+1
| | | | | | | Deadloop if PFAddr is not supported by system, no need check SMM CPU RestrictedMemory access enable or not. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Always save and restore CR2Jiaxin Wu2024-09-061-14/+4
| | | | | | | | | | | | | | | | | Following the commit 9f29fbd3, full mapping SMM page table is always created regardless the value of the PcdCpuSmmRestrictedMemoryAccess. Consequently, a page fault (#PF) that triggers an update to the page table occurs only when SmiProfile is enabled. Therefore, it is necessary to save and restore the CR2 register when SmiProfile is configured to be enabled. And the operation of saving and restoring CR2 is considered to be not heavy operation compared to the saving and restoring of CR3. As a result, the condition check for SmiProfile has been removed, and CR2 is now saved and restored unconditionally, without the need for additional condition checks. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix IsSmmCommBufferForbiddenAddress checkJiaxin Wu2024-09-062-1/+5
| | | | | | | | | | | | | | | | SmiPFHandler depends on the IsSmmCommBufferForbiddenAddress() to do the forbidden address check: For SMM, verifying whether an address is forbidden is necessary only when RestrictedMemoryAccess is enabled. For MM, all accessible address is recorded in the ResourceDescriptor HOB, so no need check the RestrictedMemoryAccess is enabled or not. This patch is to move RestrictedMemoryAccess check into SMM IsSmmCommBufferForbiddenAddress to align with above behavior. With the change, SmiPFHandler doesn't need to check the RestrictedMemoryAccess enable or not. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid to access MCA_CAP if CPU does not supportJiaxin Wu2024-09-061-5/+3
| | | | | | Do not access MCA_CAP MSR unless the CPU supports the SmmRegFeatureControl Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Simplify SMM Profile Size CalculationJiaxin Wu2024-08-283-10/+10
| | | | | | | | | | | | | | | | | | | | | | The motivation of this change is to simplify the logic in StandaloneMmIpl when allocating the memory for SMM profile data. IPL does not need to detect the CPU feature regarding MSR DS Area. That change requires the PCD value contains the MSR DS Area. So, the size of SmmProfileData will be simplified to the PcdCpuSmmProfileSize directly. mMsrDsAreaSize will be within the PcdCpuSmmProfileSize if mBtsSupported is TRUE. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid PcdCpuSmmProfileEnable check in MMJiaxin Wu2024-08-2812-17/+83
| | | | | | | | | | | | | | | | | | | | | | For MM, gMmProfileDataHobGuid Memory Allocation HOB is defined to indicate SMM profile feature enabled or not. If the HOB exist, SMM profile base address and size will be returned in the HOB, so no need to consume the PcdCpuSmmProfileEnable feature PCD to check enable or disable. To achieve above purpose, Add the IsSmmProfileEnabled () function. With this change, Both MM and SMM can use the new function for SMM profile feature check. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Cleanup SMM_CPU_SYNC_MODEJiaxin Wu2024-08-284-30/+24
| | | | | | | | | | | | | | | Use MM_CPU_SYNC_MODE instead of SMM_CPU_SYNC_MODE. Cleanup the duplicate definition. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Refine DxeSmm PageTable update logicJiaxin Wu2024-08-285-144/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to refine the updatePageTable logic for DxeSmm. For DxeSmm, PageTable will be updated in the first SMI when SMM ready to lock happen: IF SMM Profile is TRUE: 1. Mark mProtectionMemRange attribute: SmrrBase:Present, SMM profile base:Present&Nx, MMRAM ranges:Present, MMIO ranges: Present&Nx. 2. Mark the ranges not in mProtectionMemRange as RP (non-present). IF SMM Profile is FALSE: 1. Mark Non-MMRAM ranges as NX. 2. IF RestrictedMemoryAccess is TRUE: Forbidden Address mark as RP (IsUefiPageNotPresent is TRUE). Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add PiSmmCpuStandaloneMm.infJiaxin Wu2024-08-281-0/+136
| | | | | | | | | | | | | | | This patch is to add PiSmmCpuStandaloneMm.inf for MM CPU support. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Check logging PF address for MMJiaxin Wu2024-08-284-0/+70
| | | | | | | | | | | | | | | This patch is to make sure only logging PF address for MM can run into the SmmProfilePFHandler. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Start SMM Profile early for MMJiaxin Wu2024-08-284-5/+24
| | | | | | | | | | | | | | | | SMM Profile start can be started early in SMM CPU EntryPoint since page table for SMM profile is ready. No need wait smm ready to lock. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Differentiate PerformRemainingTasksJiaxin Wu2024-08-285-103/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | For MM: SMRAM & PageTable itself & SMM Paging State shall be configured once the gEdkiiPiMmMemoryAttributesTableGuid is installed by SMM core. It will happen after MmIpl.Entrypoint. PerformRemainingTasks will be called before MmIpl.Entrypoint exit. For SMM: SMRAM & PageTable itself & SMM Paging State are still configured in the first SMI when SMM ready to lock happen. So, this patch is to differentiate PerformRemainingTasks for MM and SMM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Enable CodeAccessCheck in MM Entry PointJiaxin Wu2024-08-284-23/+50
| | | | | | | | | | | | | | | | | | | | | | | For MM: CodeAccessCheck is designed to enable in the MM CPU Driver Entry Point. For SMM: CodeAccessCheck is still enabled in the first SMI when SMM ready to lock happen. This patch enables the CodeAccessCheck in MM CPU Driver Entry Point for MM support. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Refactor code to create default Page TableJiaxin Wu2024-08-287-74/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For MM: Since all accessible NON-MMRAM memory and attribute shall be in ResourceDescriptor HOBs for MM, the page table for MM can be finalized and created in the default Page. For SMM: There are still 2 steps for the finalized default Page: 1. Create default Page 2. update the page table in the first SMI when SMM ready to lock happen This patch to refactor the GenSmmPageTable() function to create the default Page Table for Both SMM and MM: 1. Create NonMmram MemoryRegion 2. Gen NonMmram MemoryRegion PageTable 3. Gen MMRAM Range PageTable 4. Consider PcdCpuSmmStackGuard & PcdNullPointerDetectionPropertyMask cases. Meanwhile, mXdSupported needs to be initialized before GenSmmPageTable since it's required by GenSmmPageTable function. So, move the mXdSupported init from CheckFeatureSupported to the common EntryPoint function. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add PiCpuStandaloneMmEntry for MMJiaxin Wu2024-08-281-0/+46
| | | | | | | | | | | | | | | | | | | | | This patch adds the PiCpuStandaloneMmEntry for MM, which is the module Entry Point of the CPU StandaloneMm driver. In the Entry Point: 1. Init the mIsStandaloneMm flag 2. Call PiSmmCpuEntryCommon 3. Init SmiCommandPort 4. Install the SMM Configuration Protocol. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add GetSupportedMaxLogicalProcessorNumberJiaxin Wu2024-08-284-11/+54
| | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdCpuMaxLogicalProcessorNumber), so move the PCD usage to DxeSmm. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl IsSmmCommBufferForbiddenAddress for MMJiaxin Wu2024-08-281-0/+28
| | | | | | | | | | | | | | | | Since all accessible NON-MMRAM memory shall be in ResourceDescriptor HOBs, check the ResourceDescriptor HOBs to return if the Address is forbidden or not for MM CPU. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Define mIsStandaloneMm to indicate SMM or MMJiaxin Wu2024-08-284-3/+41
| | | | | | | | | | | | | | | | | | | | Define the mIsStandaloneMm to indicate it's the MM_STANDALONE MM CPU driver or DXE_SMM_DRIVER SMM CPU driver execution. With mIsStandaloneMm, GetMpInformationFromMpServices() can be skipped for the MM CPU since it can not call the GetMpInformationFromMpServices() due to the NON-SMM MP Services usage for the MP Information. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetSmiCommandPort for MMJiaxin Wu2024-08-281-0/+13
| | | | | | | | | | | | | | | | MM CPU can not call EfiLocateFirstAcpiTable to get the system port address of the SMI Command Port. This patch just hard-code to 0xB2 for MM CPU. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl CreateExtendedProtectionRange for MMJiaxin Wu2024-08-282-2/+86
| | | | | | | | | | | | | | | | | According Standalone MM design, all accessible NON-MMRAM memory shall be in ResourceDescriptor HOBs. So, This patch consumes the Resource HOBs to create extended protection MemoryRegion and add them into protected memory ranges. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetSmmCpuSyncConfigData for MMJiaxin Wu2024-08-282-0/+46
| | | | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdCpuSmmSyncMode & PcdCpuSmmApSyncTimeout & PcdCpuSmmApSyncTimeout2), so, it consumes the gMmCpuSyncConfigHobGuid for RelaxedApMode & Timeout & Timeout2. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetAcpiS3EnableFlag for MMJiaxin Wu2024-08-282-0/+29
| | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdAcpiS3Enable), so, it consumes the gMmAcpiS3EnableHobGuid to get ACPI S3 enable flag. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetSmmProfileData for MMJiaxin Wu2024-08-282-0/+40
| | | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdCpuSmmProfileSize), so it consumes the gMmProfileDataHobGuid memory allocation hob for SmmProfile base address & size. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add empty .c for MM CPU specific implJiaxin Wu2024-08-282-0/+18
| | | | | | | | | | | | | | | | This patch adds the empty .c for MM CPU specific implementation： NonMmramMapStandaloneMm.c PiSmmCpuStandaloneMm.c Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move GetSmiCommandPort into DxeSmm CodeJiaxin Wu2024-08-285-29/+35
| | | | | | | | | | | | | | | | MM can not call the EfiLocateFirstAcpiTable(), so, move the function into DxeSmm Code. This will make InitSmmProfileCallBack() to be common function for both SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move GetUefiMemoryMap into DxeSmm codeJiaxin Wu2024-08-283-43/+44
| | | | | | | | | | | | | | | | | MM can not call GetUefiMemoryMap() function, so, move it into DxeSmm code. Define a SmmReadyToLockEventNotify to handler the logic. This will make PiSmmCpuEntryCommon to be common function for SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Create extended protection MemRegion in funcJiaxin Wu2024-08-283-95/+187
| | | | | | | | | | | | | | | | MM can not use the gDS service, so move the extended protection MemRegion creation into function. This can make InitProtectedMemRange() to be a common function for both SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Get SmmCpuSyncConfig data from funcJiaxin Wu2024-08-284-3/+58
| | | | | | | | | | | | | | | | MM can not use the dynamic PCD (PcdCpuSmmSyncMode & PcdCpuSmmApSyncTimeout & PcdCpuSmmApSyncTimeout2), so, move to DxeSmm code and implement in GetSmmCpuSyncConfigData function. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move GetAcpiS3EnableFlag into DxeSmm codeJiaxin Wu2024-08-283-12/+13
| | | | | | | | | | | | | | | | MM can not use the dynamic PCD, so, Move GetAcpiS3EnableFlag into DxeSmm code. This can make PiSmmCpuEntryCommon to be a function for SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move SMM profile data allocation into funcJiaxin Wu2024-08-283-29/+67
| | | | | | | | | | | | | | | | MM can not use the gBS service, so move SMM profile data allocation into function. This can make InitSmmProfileInternal() to a common function for both SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Use SMM Variable to set SmmProfileBaseJiaxin Wu2024-08-283-7/+18
| | | | | | | | | | | | | | | | MM can not use the gRT service, so use SMM Variable protocol to set SmmProfileBase instead of gRT->SetVariable for both SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Get SMRAM info from gEfiSmmSmramMemoryGuidJiaxin Wu2024-08-283-28/+16
| | | | | | | | | | | | | | | | MM can not use the SMM Access Protocol, so get SMRAM info from gEfiSmmSmramMemoryGuid instead of via SMM Access Protocol for both SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Centralize Non-Mmram Mem Management CodeJiaxin Wu2024-08-283-477/+489
| | | | | | | | | | | | | | | | | | Centralize the SMM Non-Mmram Memory Management related code into the NonMmramMapDxeSmm.c. The file SmmCpuMemoryManagement.c will be target to use for both SMM and MM in subsequent patches. No function impact. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move common code into PiSmmCpuCommon.cJiaxin Wu2024-08-284-1603/+1663
| | | | | | | | | | | | | | | | | | Move common code into PiSmmCpuCommon.c to facilitate common usage in both SMM and MM. The PiSmmCpuCommon.h will be utilized for both modes in subsequent patches. No function impact. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Rename PiSmmCpuDxeSmm.h to PiSmmCpuCommon.hJiaxin Wu2024-08-2818-20/+20
| | | | | | | | | | | | | | | | | | Rename the file PiSmmCpuDxeSmm.h to PiSmmCpuCommon.h to facilitate common usage in both SMM and MM. The renamed file PiSmmCpuCommon.h will be utilized for both modes in subsequent patches. No function impact. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Update gSmst to gMmstJiaxin Wu2024-08-287-28/+28
| | | | | | | | | | | | | | | | | This patch update the gSmst to gMmst for SMM and MM common usage. No function impact. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg: rename and simplify IsAddressValid functionDun Tan2024-08-053-34/+31
| | | | | | | | | | | | | | | In this commit, we rename IsAddressValid function to IsSmmProfilePFAddressAbove4GValid and remove unneeded code logic in it. Currently, IsAddressValid is only used in the function RestorePageTableAbove4G. It's used to identify if a SMM profile PF address above 4G is inside mProtectionMemRange or not. So we can remove the PcdCpuSmmProfileEnable FALSE condition related code logic in it. Also the function name is change to be more detailed and specific. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: remove unneeded code in SmmProfilePFHandlerDun Tan2024-08-051-8/+0
| | | | | | | | | | | | | | | | | | | | | | Remove unneeded calling of SmmProfileMapPFAddress () in SmmProfileMapPFAddress if SMM profile is not started. Previously, before SMM profile is started at ReadyToLock, SMM page table only covers [0, 4G]. The access to the range above 4G will cause PF. SmmProfileMapPFAddress is needed here to map the PF address before SMM profile is started. Now we always create full mapping SMM page table in the SmmInitPageTable(). When SMM profile is enabled, before SMM profile is started at ReadyToLock, SMM page table covers [0, MaxSupportedPhysicalAddress]. So the case that access to the range above 4G causes PF won't happen anymore. Then we can remove the calling of SmmProfileMapPFAddress before SMM profile is started. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: rename the SmiDefaultPFHandler functionDun Tan2024-08-057-166/+221
| | | | | | | | Rename SmiDefaultPFHandler to SmiProfileMapPFAddress and move the implementation to SmmProfileArch.c since it only will be used when SMM profile is enabled. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: Remove duplicate code in SmiPfHandlerDun Tan2024-08-052-12/+6
| | | | | | | | | | | | | | In this commit, we remove duplicate CpuDeadLoop in SmiPfHandler where mCpuSmmRestrictedMemoryAccess is TRUE. With last commit, we always call CpuDeadLoop if SMM profile is disabled. Then the CpuDeadLoop calling for the condition (mCpuSmmRestrictedMemoryAccess && IsSmmCommBufferForbiddenAddress (PFAddress)) is not needed anymore. We also modify the IA32 related code to be aligned with X64. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg:CpuDeadLoop in SmiPFHandler if SMM profile is disabledDun Tan2024-08-052-3/+4
| | | | | | | | | | | | | | | | | | | | Always call CpuDeadLoop() in SmiPFHandler if SMM profile is disabled. Previously, when PcdCpuSmmRestrictedMemoryAccess is FALSE, SMM page table only covers [0, 4g]. When code access to range above 4g happens, SmiPFHandler will map the accessed not-present range to present. After we always create full mapping page table, the dynamic page table creation logic is only needed when SMM profile is enabled. So we use CpuDeadLoop() in SmiPFHandler to cover the all the PF exception when SMM profile is disabled Considering that [0, 4g] is always mapped in SMM page table, we also modify the IA32 SmiPFHandler code to be aligned with X64 code. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: remove unnecessary manipulation for smm page tableDun Tan2024-08-051-17/+17
| | | | | | | | | | | | | | | | | | | In this commit, we only set some special bits in paging entry content when SMM profile is enabled. Previously, we set Pml4Entry sub-entries number and set the IA32_PG_PMNT bit for first 4 PdptEntry. It's to make sure that the paging structures cover [0, 4G] won't be reclaimed during dynamic page table creation. In last commit, we always create full mapping SMM page table regardless PcdCpuSmmRestrictedMemoryAccess. With this change, we only need to dynamic create SMM page table in smm PF handler when PcdCpuSmmProfileEnable is TRUE. So the sub-entries number and IA32_PG_PMNT bit in paging entry is only needed to set when PcdCpuSmmProfileEnable is TRUE. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: always create full mapping SMM page tableDun Tan2024-08-052-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this commit, we always create full mapping SMM page table in SmmInitPageTable regardless the value of the PcdCpuSmmRestrictedMemoryAccess. Previously, when PcdCpuSmmRestrictedMemoryAccess is false, only [0, 4G] is mapped in smm page table in SmmInitPageTable. If the range above 4G is accessed in SMM, SmiPFHandler will create new paging entry for the accessed range. To simplify the code logic, we also create full mapping SMM page table in SmmInitPageTable when PcdCpuSmmRestrictedMemoryAccess is false. Then we don't need to dynamic create paging entry for range above 4G except SMM profile is enabled. The comparison of SMM page table before and after the change under different configuration are listed here: 1.PcdCpuSmmRestrictedMemoryAccess is TRUE No change 2.PcdCpuSmmRestrictedMemoryAccess is FALSE and PcdCpuSmmProfileEnable is TRUE Before: the SMM page table when ReadyToLock covers 1. SMRAM range 2.SMM profile range 3. MMIO range below 4G After: the SMM page table when ReadyToLock covers 1. SMRAM range 2.SMM profile range 3. MMIO range below 4G and above 4G 3.PcdCpuSmmRestrictedMemoryAccess is FALSE and PcdCpuSmmProfileEnable is FALSE Before: the SMM page table when ReadyToLock covers [0, 4G] After: the SMM page table when ReadyToLock covers [0, MaxSupportPhysicalAddress] Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: Revert "UefiCpuPkg/PiSmmCpuDxeSmm: Fix system..."Dun Tan2024-08-051-30/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bef0d333dc "UefiCpuPkg/PiSmmCpuDxeSmm: Fix system hang when SmmProfile enable". The commit bef0d333dc was added to modify the code logic in InitPaging() to fix a code assert issue. Previously, the root cause of this issue is that we try to only set NX attribute for not-present MMIO range above 4G when SMM profile feature is enabled, which is not allowed by CpuPageTableLib. But after we always create full mapping initial SMM page table in the next commit, this code assert issue won't happen anymore since MMIO range above 4g will also be present in SMM page table before InitPaging(). Meanwhile another issue was introduced by commit bef0d333dc: In the entrypoint of PiSmmCpuDxe driver, we will set some pages in stack range as not-present in SMM page table if PcdCpuSmmStackGuard or PcdControlFlowEnforcementPropertyMask is TRUE. But in commit bef0d333dc, all SMRAM range are set to present in InitPaging() if SMM profile is enabled. Then the stack guard and shadow stack features do not work anymore. So let's revert the commit "UefiCpuPkg/PiSmmCpuDxeSmm: Fix system hang when SmmProfile enable" Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid use global variable in InitSmmS3Cr3Jiaxin Wu2024-08-026-20/+29
| | | | | | | This patch is to avoid use global variable in InitSmmS3Cr3. No function impact. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean redundant SmmS3Cr3 InitJiaxin Wu2024-08-023-8/+3
| | | | | | | | The SmmS3Cr3 is only used by S3Resume PEIM to switch CPU from 32bit to 64bit, it should be the CR3 for Non-SMM environment and init by InitSmmS3Cr3 function. No need set to SMM CR3. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 05:33:36 +0000