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* UefiCpuPkg: Remove PcdFrameworkCompatibilitySupport usageDandan Bi2019-05-091-2/+1
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1464 Currently Framework compatibility support is not needed and PcdFrameworkCompatibilitySupport will be removed from edk2. So remove the usage of this PCD firstly. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.Eric Dong2018-10-151-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V5: 1. Add ASSERT to indicate this assumption that environment is 32 bit mode. 2. Add description in INF about this driver's expected result in different environment. V4: Only disable paging when it is enabled. V3 changes: No need to change inf file. V2 changes: Only disable paging in 32 bit mode, no matter it is enable or not. V1 changes: PEI Stack Guard needs to enable paging. This might cause #GP if code trying to write CR3 register with PML4 page table while the processor is enabled with PAE paging. Simply disabling paging before updating CR3 can solve this conflict. It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60 BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232 Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Remove redundant library classes, Ppis and GUIDsshenglei2018-09-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some redundant library classes Ppis and GUIDs have been removed in inf, .c and .h files. v2: 1.Remove ReadOnlyVariable2.h in S3Resume.c which should be deleted in last version in which gEfiPeiReadOnlyVariable2PpiGuid was removed. 2.Remove the library class BaseLib in CpuPageTable.c which is included elsewhere. 3.Add library classes in SecCore.inf which are removed at last version. They are DebugAgentLib and CpuExceptionHandlerLib. 4.Add two Ppis in SecCore.inf which are removed at last version. They are gEfiSecPlatformInformationPpiGuid and gEfiSecPlatformInformation2PpiGuid. https://bugzilla.tianocore.org/show_bug.cgi?id=1043 https://bugzilla.tianocore.org/show_bug.cgi?id=1013 https://bugzilla.tianocore.org/show_bug.cgi?id=1032 https://bugzilla.tianocore.org/show_bug.cgi?id=1016 Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Remove X86 ASM and S filesLiming Gao2018-06-071-4/+0
| | | | | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules expect for the ones in ResetVector directory. The ones in ResetVector directory are included by Vtf0.nasmb. They are also nasm style. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg S3ResumePei: Signal S3SmmInitDoneStar Zeng2018-03-031-0/+3
| | | | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/S3Resume: Remove useless perf codeDandan Bi2018-02-121-2/+1
| | | | | | | | | | | | | | | | | | | V2: Just update the commit message to reference the hash value of new performance infrastructure. Our new performance infrastructure (edk2 trunk commit hash value: SHA-1: 73fef64f14d1b97ae9bd4705df3becc022391eba ~ SHA-1: 115eae650bfd2be2c2bc37360f4a755065e774c4)can support to dump performance date form ACPI table in OS. So we can remove the old perf code to write performance data to OS. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Rename SmmEndOfS3ResumeProtocolGuid to EndOfS3ResumeGuidStar Zeng2017-12-121-4/+2
| | | | | | | | | | | | | | | Rename SmmEndOfS3ResumeProtocolGuid to EndOfS3ResumeGuid as the GUID may be used to install PPI in future to notify PEI phase code. The references in UefiCpuPkg are also being updated. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/S3Resume2Pei: Send S3 resume finished event to SmmCore.Eric Dong2017-10-121-0/+4
| | | | | | | | | | | | | | | | | | | | | Driver will send S3 resume finished event to SmmCore through communicate buffer after it signals EndOfPei event. V2 Changes: 1. Change structures name to avoid they start with EFI_. 2. Base on DXE phase bits to provide communication buffer, current implement check both PEI and DXE phase. V3 Changes: 1. Change structure name for better understanding. 2. Enhance communication buffer calculate logic to more accurate. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD ↵Leo Duran2017-03-011-0/+2
| | | | | | | | | | | | | | | | | | | PcdPteMemoryEncryptionAddressOrMask This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables are created (S3Resume.c). CC: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg S3Resume2Pei: Add nasm source file into INF file.Liming Gao2016-06-281-2/+4
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: INF/DEC file updates to EDK II packagesGao, Liming2014-08-281-15/+22
| | | | | | | | | | | | 1. Usage information in INF file comment blocks are either incomplete or incorrect. This includes usage information for Protocols/PPIs/GUIDs/PCDs/HOBs/Events/BootModes. The syntax for usage information in comment blocks is defined in the EDK II Module Information (INF) Specification Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gao, Liming <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15933 6f19259b-4bc3-4df7-8a09-765794883524
* Correct INF file to make module pass ICC compiler.Liming Gao2013-12-111-2/+2
| | | | | | Signed-off-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14961 6f19259b-4bc3-4df7-8a09-765794883524
* Set correct DS/ES/FS/GS/SS segment selectors after GDT loaded.vanjeff2012-08-221-0/+8
| | | | | | | | | Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Rui Sun <rui.sun@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13667 6f19259b-4bc3-4df7-8a09-765794883524
* Remove Variable PPI dependency from S3Resume module, check return status of ↵lzeng142012-08-061-2/+2
| | | | | | | | | locating SmmAccess PPI in S3Resume S3ResumeExecuteBootScript(), and locate SmmAccess PPI and Open SMRAM region only when gEfiAcpiVariableGuid HOB is found in S3Resume S3RestoreConfig2(). Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13592 6f19259b-4bc3-4df7-8a09-765794883524
* Add PCD for 1G page tablejyao12011-09-211-0/+3
| | | | | | | signed off by: jyao1 reviewed by: jfan12 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12397 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Add S3Resume2Pei PEIMjljusten2011-08-291-0/+79
Signed-off-by: jljusten Reviewed-by: mdkinney Reviewed-by: rsun3 Reviewed-by: jyao1 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12227 6f19259b-4bc3-4df7-8a09-765794883524
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