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* UefiCpuPkg/PiSmmCpuDxeSmm: Clear some semaphores on S3 boot pathJeff Fan2016-12-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Some semaphores are not cleared on S3 boot path. For example, mSmmMpSyncData->CpuData[CpuIndex].Present. It may still keeps the value set at SMM runtime during S3 resume. It may causes BSP have the wrong judgement on SMM AP's present state. We have one related fix at e78a2a49ee6b0c0d7c6997c87ace31d7761cf636. But that is not completed. This fix is to clear Busy/Run/Present semaphores in InitializeMpSyncData(). Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 56e4a7d72660b229be333bbb5e1b5790d3c17890)
* UefiCpuPkg/SecCore: SecPlatformInformation(2) are optional PPIsJeff Fan2016-11-141-0/+2
| | | | | | | | | | | | | Currently, this is ASSERT() if neither SecPlatformInformation2 nor SecPlatformInformation PPIs are found. This is not correct. Per PI specification both of them are optional PPI. Platform may not install them. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> (cherry picked from commit 93638568c1c6bd6bace2cd27666796b7c87fc45c)
* UefiCpuPkg/SecCore: Fix comment typoJeff Fan2016-11-141-6/+6
| | | | | | | | | | | | Revert SecPlatformInformation2 and SecPlatformInformation in two comment blocks. And correct the words. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> (cherry picked from commit 030d2de7c7a8682837be168bbaf7f27739a8fff0)
* UefiCpuPkg/SecCore: Re-install SEC platform information(2) PPIJeff Fan2016-11-144-1/+146
| | | | | | | | | | | | | | In SecTemporaryRamDone(), we will build one privated GUIDed-HOB to save CPU BIST Data and re-install SEC platform information(2) PPI. Then other PEI drivers could get CPU BIST data from the private GUIDed-HOB by new installed PPI. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> (cherry picked from commit 8a5b8cef678711060cc9014e0fac1886839de943)
* UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()Jeff Fan2016-11-141-20/+61
| | | | | | | | | | | | | | Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke GetBistFromHob(). Add in/out for parameter in function header. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> (cherry picked from commit d157de8b5603fb24feed6ec7b46be8677083c25a)
* UefiCpuPkg/SecCore: Add SecBist.cJeff Fan2016-11-144-2/+152
| | | | | | | | | | | | | | Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and UefiCpuPkg.dsc accordinlgy to pass build. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> (cherry picked from commit 863c738c4af0d200c8789e4786e1722e07f407fa)
* UefiCpuPkg/PiSmmCpuDxeSmm: SMM_CPU_DATA_BLOCK is not clearedJeff Fan2016-07-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 8b9311 changed the zeroing of mSmmMpSyncData of type SMM_DISPATCHER_MP_SYNC_DATA by the following patch. - ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize); + mSmmMpSyncData->SwitchBsp = FALSE; mSmmMpSyncDataSize not only includes SMM_DISPATCHER_MP_SYNC_DATA, but also includes the SMM_CPU_DATA_BLOCK array and one BOOLEAN variable array as shown here: mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) + (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; This patch restores the original ZeroMem() to clear all CPU Sync data. The commit 8b9311 may cause unexpected behavior. v2: Mentioned CandidateBsp array in comments to make it more accurate. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> (cherry picked from commit e78a2a49ee6b0c0d7c6997c87ace31d7761cf636)
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove duplicate aligned buffer on S3 pathJeff Fan2016-07-211-16/+25
| | | | | | | | | | | | | | | | | | | | | InitializeMpSyncData() invokes InitializeSmmCpuSemaphores() to allocate an aligned buffer for all locks and semaphores. However, this function is invoked on S3 resume path again to reset mSmmMpSyncData. It causes an additional aligned buffer to be allocated. This update moves InitializeSmmCpuSemaphores() into InitializeMpServiceData() that is only invoked on normal boot. InitializeMpSyncData() is updated to reset the locks/semaphore in mSmmMpSyncData. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 8b9311b79557311e137d0ffdc7934fea3966b0d7)
* UefiCpuPkg/MtrrLib: Fixed bug if length is less than Fixed-MTRR rangeJeff Fan2016-07-151-23/+48
| | | | | | | | | | | | | | | | | | | Currently, if the memory length to be programmed is less than the remaining size of one Fixed-MTRR supported, RETURN_UNSUPPORTED returned. This is not correct. This is one regression at 07e889209034ba94bfac9e765b8a50ef344daef2 when we updated ProgramFixedMtrr() to remove the loop of calculating Fixed-MTRR Mask. This fix will calculate Right offset in Fixed-MTRR beside left offset. It supports small length (less than remaining size supported by Fixed-MTRR) to be programmed. Cc: Eric Dong <eric.dong@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit eecad34987c56317f69d4eee9d9c1df0c825a79e)
* UefiCpuPkg/MtrrLib: Remove the loop of calculating Fixed-MTRR MaskJeff Fan2016-07-151-16/+23
| | | | | | | | | | | | Introduce the 32bit mask seeds to calculate Fixed-MTRR or&and mask values. It could avoid the loop operation and 64bit shift operations. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 07e889209034ba94bfac9e765b8a50ef344daef2)
* UefiCpuPkg/MtrrLib: Remove the loop of calculating byte offset in MSRJeff Fan2016-07-151-11/+3
| | | | | | | | | | | Calculate byte offset in MSR directly and removing the loop. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit aaa1e579a5109a868863c8a3c7a51580f83b4c38)
* UefiCpuPkg/MtrrLib: Reduce the loop time to get fixed-MTRR MSR indexJeff Fan2016-07-151-6/+8
| | | | | | | | | | | | Add input fixed-MTRR MSR index to be start MSR index to avoid finding fixed-MTRR MSR index from 0 at each time. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 0f354122328755c7a1cb0f68a37748f166d412ae)
* UefiCpuPkg/CpuMpPei: Remove PmodeOffset and LmodeOffsetJeff Fan2016-07-148-25/+17
| | | | | | | | | | | | | Remove Pmode(Entry)Offset/Lmode(Entry)Offset and use unified Mode(Entry)Offset to clean up the definition of MP_ASSEMBLY_ADDRESS_MAP and MP_CPU_EXCHANGE_INFO. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit 01beffa7e9bb47adfeeb9868058311a478698b72)
* UefiCpuPkg/CpuMpPei: Remove un-used variables and functionsJeff Fan2016-07-148-156/+0
| | | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit 6d98a371593cbeee89001182a50f144f074893e2)
* UefiCpuPkg/CpuMpPei: Do not load new GDT tableJeff Fan2016-07-141-5/+1
| | | | | | | | | | | | | Do not load the new GDT table and just to use the exiting BSP's GDT table set up by SEC phase. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit 9c3d2f9a2985d97961b07ddc493b6e406ace8814)
* UefiCpuPkg/CpuMpPei/X64: Use CodeSegment and DataSegment fieldsJeff Fan2016-07-142-93/+71
| | | | | | | | | | | | | | Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode MACROs for x64 arch. Switch AP from real mode to long mode directly, so needn't the CS/DS of protected mode. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit d1471c011277829cf04a3078fa1931c104c22afa)
* UefiCpuPkg/CpuMpPei/X64: Remove hard code CPU BIST valueJeff Fan2016-07-141-4/+3
| | | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit 249ed12ea0c4bb0a9eefee6f48cecc330ff6af6a)
* UefiCpuPkg/CpuMpPei/Ia32: Use CodeSegment and DataSegment fieldsJeff Fan2016-07-142-34/+48
| | | | | | | | | | | | | Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode MACROs. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit aad5ee4899c43665a19ec8934e51dc6a34186389)
* UefiCpuPkg/CpuMpPei: Add CodeSegment and DataSegment fieldsJeff Fan2016-07-144-4/+12
| | | | | | | | | | | | | Added CodeSegment and DataSegment fields in MP_CPU_EXCHANGE_INFO. They are set to the values of current BSP's CS and DS. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit ed04bffe7517f42f94ec4eebcf9003cd6a9dd6fb)
* UefiCpuPkg/CpuMpPei: Consume CpuExceptionHandlerLibJeff Fan2016-07-143-4/+26
| | | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 9bedfb2f5b23c68c600770a9f853092d01eab6d4)
* UefiCpuPkg/ExceptionLib: Import PeiCpuExceptionHandlerLib moduleJeff Fan2016-07-145-0/+274
| | | | | | | | | | | | | This module could be linked by CpuMpPei driver to handle reserved vector list and provide spin lock for BSP/APs to prevent dump message corrupted. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit a81abf161666860d31359e40635f05fe4dc810fa)
* UefiCpuPkg/ExceptionLib: Move global variable locationJeff Fan2016-07-143-23/+22
| | | | | | | | | | | | | | Move some global variables location from PeiDxeSmmCpuException.c to DxeCpuException.c and SmmCpuException.c. And remove some un-used global vairables. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit d91225cfad507219502086d0b6b670ae126d489d)
* UefiCpuPkg/ExceptionLib: Add CommonExceptionHandlerWorker()Jeff Fan2016-07-144-26/+72
| | | | | | | | | | | | Add internal worker function RegisterCpuInterruptHandlerWorker(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 44ecbc28b69834ec1a4b1a8b99dae8839633b6b6)
* UefiCpuPkg/ExceptionLib: Update RegisterCpuInterruptHandlerWorker()Jeff Fan2016-07-144-17/+29
| | | | | | | | | | | | Add parameter CpuExceptionData for RegisterCpuInterruptHandlerWorker(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 670f13af6051dc7b8dcdaf9e1ec8014e122f41b7)
* UefiCpuPkg/ExceptionLib: Update UpdateIdtTable()Jeff Fan2016-07-143-24/+37
| | | | | | | | | | | | Add parameter CpuExceptionData for UpdateIdtTable(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 9db15f8148081688a0679b76a7258e9fc66107bc)
* UefiCpuPkg/ExceptionLib: Update InitializeCpuExceptionHandlersWorkerJeff Fan2016-07-144-9/+24
| | | | | | | | | | | | Add parameter CpuExceptionData for InitializeCpuExceptionHandlersWorker(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit ab95e54dc4ec949fd13e8bdda1c7423469e08c3d)
* UefiCpuPkg/ExceptionLib: Add EXCEPTION_HANDLER_DATA definitionJeff Fan2016-07-143-3/+12
| | | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 2c5873fede073ae1d83a4cb830ee1bad7bea1a62)
* UefiCpuPkg/ExceptionLib: Rename DxeSmmCpuException.cJeff Fan2016-07-143-6/+6
| | | | | | | | | | | | | Rename DxeSmmCpuException.c to PeiDxeSmmCpuException.c that will be used by PeiCpuExceptionHandlerLib. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 9b4aa7602e3ae93efc0b4956653b00c0062de07b)
* UefiCpuPkg: CpuMpPei: remove set but unused variablesLaszlo Ersek2016-07-141-2/+1
| | | | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 6c7f3f1d5921d0cd27f975af8cb723732b3ab158)
* UefiCpuPkg: PiSmmCpuDxeSmm: remove set but unused variablesLaszlo Ersek2016-07-141-23/+11
| | | | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit dc0a7143148508ef8eac2c8a5fb239d84561af14)
* UefiCpuPkg/CpuMpPei: Remove unnecessary variableJeff Fan2016-07-142-4/+0
| | | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit 30dc4a49b6e303d7a53ff27a8334269cfe3662e9)
* UefiCpuPkg/CpuMpPei: Dump message if microcode signature not matchedJeff Fan2016-07-144-25/+31
| | | | | | | | | | | | | | Verification microcode signature is one enhancement and not one requirement from IA32 SDM. This update is just to dump debug message instead of ASSERT() if the updated microcode signature does not match the loaded microcode signature. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit 719ff8cf3e8f3abc967de8a0a71319ce66ff2d9d)
* UefiCpuPkg/CpuMpPei: Skip microcode check/load if it has been loadedJeff Fan2016-07-141-0/+9
| | | | | | | | | | | | | | | Actually, there is only one microcode region in platform. If microcode has been loaded, its signature will not be zero and should be loaded successfully. We needn't to check microcode region and load microcode again. This update is to skip checking/loading microcode if current microcode signature is not zero. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> (cherry picked from commit 46fd118219fcce638f1eb9c861f4a037530b64b9)
* UefiCpuPkg S3Resume2Pei: Report status code when allocate memory is failedStar Zeng2016-07-071-3/+15
| | | | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 6f9760d88b11d3a848c2522286f3a5b5e5214fbd)
* UefiCpuPkg: fix ASSERT_EFI_ERROR() typosLaszlo Ersek2016-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | A number of code locations use ASSERT_EFI_ERROR (BooleanExpression) instead of ASSERT (BooleanExpression) Fix them. Cc: Jeff Fan <jeff.fan@intel.com> Reported-by: Gerd Hoffmann <kraxel@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> (cherry picked from commit ef3e20e3ca77204d69e741c720e0552d822ded0f)
* UefiCpuPkg/Cpuid.h: Display Intel SGX Resource Enumeration LeavesJeff Fan2016-07-071-0/+117
| | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> (cherry picked from commit f5a2d6f012fff6073017f814da6dd19530cc6046)
* UefiCpuPkg/Cpuid.h: Add CPUID defines and structures for Intel SGXJeff Fan2016-07-071-1/+280
| | | | | | | | | | | | | Add Intel SGX Resource Enumeration Leaves as described by Section 37.7 in Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D, December 2015. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> (cherry picked from commit c606a9a5b7611f54a4ae731827e7edd8a980dca3)
* UefiCpuPkg/PiSmmCpuDxeSmm: Using MSRs semaphores in aligned bufferJeff Fan2016-07-062-6/+30
| | | | | | | | | | | | | | Update MSRs semaphores to the ones in allocated aligned semaphores buffer. If MSRs semaphores is not enough, allocate one page more. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit dc99315b8732b6e3032d01319d3f534d440b43d0)
* UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for MSRs semaphoresJeff Fan2016-07-063-3/+20
| | | | | | | | | | | | | | Allocate MSRs semaphores in allocated aligned semaphores buffer. And add it into semaphores structure. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 695e62d1419cf3a8ab65a96c86c9cf58d4206d61)
* UefiCpuPkg/PiSmmCpuDxeSmm: Using CPU semaphores in aligned bufferJeff Fan2016-07-063-39/+49
| | | | | | | | | | | | | | Update each CPU semaphores to the ones in allocated aligned semaphores buffer. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit ed3d5ecb342dd6cca299ac72b30d4855a8b804a4)
* UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for each CPU semaphoresJeff Fan2016-07-062-1/+21
| | | | | | | | | | | | | | Allocate each CPU semaphores in allocated aligned semaphores buffer. And add it into semaphores structure. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 4e920581133766a31410f9d5b091446a3bc19d8c)
* UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned bufferJeff Fan2016-07-065-45/+51
| | | | | | | | | | | | | | Update all global semaphores to the ones in allocated aligned semaphores buffer. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit fe3a75bc41545125f76c28238016658f48833ba2)
* UefiCpuPkg/PiSmmCpuDxeSmm: Move forward MP sync data initializationJeff Fan2016-07-061-9/+9
| | | | | | | | | | | | | | | Move MP sync data initialization in front of the place that initialize page table, because the page fault spin lock is allocated in InitializeMpSyncData() while it is initialized in SmmInitPageTable(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit d67b73cc381219f16f5d120e733efb7ffaa814f0)
* UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for global semaphoresJeff Fan2016-07-062-0/+65
| | | | | | | | | | | | | | Get semaphores alignment/size requirement and allocate aligned buffer for all global spin lock and semaphores. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 1d64853193602f1100b835a4824da14c4258e5da)
* UefiCpuPkg/CpuMpPei: Fix potential AP mwait wakeup issueJeff Fan2016-07-061-7/+35
| | | | | | | | | | | | | | | | | | | | | | | If ApLoopMode is set to ApInMwaitLoop, AP will be placed into C-State by mwait instruction. BSP will wakeup AP by write start-up signal in monitor address. However, AP maybe waken by SMI/NMI/MCE and other condition. On this case, AP will check if BSP wants to wakeup itself really. If not, AP will continue to execute mwait to C-State. One potential issue: BSP may not recognize AP was wakeup from C-State by other event and BSP still writes start-up signal to wakeup AP. But AP does not aware it and still execute mwait instruction to C-State. So, AP cannot be wakeup on this case. This fix is let AP to clear start-up signal when it really is wakeup to execute AP function. And BSP will write start-up signal till AP clears it. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 4da1ebf3b3c22ec3e09cef3fe5d1da6f40895e6d)
* UefiCpuPkg/MtrrLib: remove unused but set variableArd Biesheuvel2016-06-291-2/+0
| | | | | | | | | | | | | | | | Remove variable TempQWord that is declared, assigned but never referenced. This fixes a warning emitted by GCC when -Wunused-but-set-variable is in effect. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 16e93125b506e30e53f63be4af0255a3afb0210b)
* UefiCpuPkg/Include: Add top level MSR include fileMichael Kinney2016-03-141-0/+48
| | | | | | | | | | | | | | | | | Add top level MSR include file that includes the Architecural MSR include file and all family specific MSR files from the Msr subdirectory Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR). Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 195c94360f726702b4a9a2290f02db2cd547d903)
* UefiCpuPkg/Include: Add Pentium MSR include fileMichael Kinney2016-03-141-0/+121
| | | | | | | | | | | | | | Add Pentium MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit a1e8e34d745cbf770db002e0596e714bd64e6056)
* UefiCpuPkg/Include: Add P6 MSR include fileMichael Kinney2016-03-141-0/+1608
| | | | | | | | | | | | | | Add P6 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 8e6bff887588c956f9b646e7ad78c173fa50fc0a)
* UefiCpuPkg/Include: Add Pentium M MSR include fileMichael Kinney2016-03-141-0/+643
| | | | | | | | | | | | | | Add Pentium M MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 83d4e58cb0a79eaa28f20d76814e27916edbc4a6)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 05:02:36 +0000