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* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-09285-1979/+289
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level pagingRay Ni2019-04-091-2/+5
| | | | | | | | Reserved6 is changed to Reserved7 because the bit width is changed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/LocalApicLib: Add GetProcessorLocation2ByApicId() APIRay Ni2019-04-083-3/+276
| | | | | | | | | | | GetProcessorLocation2ByApicId() extracts the package/die/tile/module/core/thread ID from the initial APIC ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
* UefiCpuPkg/Cpuid: Dump leaf 1FH information correctlyRay Ni2019-04-041-49/+23
| | | | | | | | | | | | | | | | | | Leaf 1FH is very similar to leaf 0BH. Both return the CPU topology information. Leaf 0BH returns 3-level (Package/Core/Thread) CPU topology info. Leaf 1FH returns 6-level (Package/Die/Tile/Module/Core/Thread) CPU topology info. The logic to enumerate the topology info is the same. But today's logic to handle 1FH is completely wrong. The patch combines them together to fix the 1FH issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
* UefiCpuPkg/Cpuid.h: Remove duplicated struct definition for leaf 1FHRay Ni2019-04-042-130/+20
| | | | | | | | | | | | | | | | Per SDM CPUID.0BH and CPUID.1FH outputs the same format of data in EAX/EBX/ECX/EDX except CPUID.1FH reports more level types such as module, tile, die. The patch removes the unnecessary duplicated structure definitions for CPUID.1FH because when the structure definitions for CPUID.0BH can be used for CPUID.1FH. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Correct comments.Eric Dong2019-04-041-2/+2
| | | | | | | | Cc: Ray Ni <Ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Simplify PcdCpuFeaturesSupport.Eric Dong2019-04-043-32/+22
| | | | | | | | | | | | | | | | PcdCpuFeaturesSupport used to specify the platform policy about what CPU features this platform supports. This PCD will be used in IsCpuFeatureSupported only. Now RegisterCpuFeaturesLib use this PCD as an template to Get the pcd size. Update the code logic to replace it with PcdCpuFeaturesSetting. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Optimize PCDEric Dong2019-04-045-72/+27
| | | | | | | | | | | | | | PcdCpuFeaturesUserConfiguration. Merge PcdCpuFeaturesUserConfiguration into PcdCpuFeaturesSetting. Use PcdCpuFeaturesSetting as input for the user input feature setting Use PcdCpuFeaturesSetting as output for the final CPU feature setting BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions.Eric Dong2019-04-042-86/+2
| | | | | | | | | | Remove useless APIs, simplify the code logic. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg\CpuSmm: Save & restore CR2 on-demand paging in SMMVanguput, Narendra K2019-04-044-3/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1593 For every SMI occurrence, save and restore CR2 register only when SMM on-demand paging support is enabled in 64 bit operation mode. This is not a bug but to have better improvement of code. Patch5 is updated with separate functions for Save and Restore of CR2 based on review feedback. Patch6 - Removed Global Cr2 instead used function parameter. Patch7 - Removed checking Cr2 with 0 as per feedback. Patch8 and 9 - Aligned with EDK2 Coding style. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vanguput Narendra K <narendra.k.vanguput@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Fix MemTest86 failure.Eric Dong2019-04-041-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V2 changes: Update the commit message and comments in the code. When waking vector buffer allocated by CpuDxe is tested by MemTest86 in MP mode, an error is reported because the same range of memory is modified by both CpuDxe driver and MemTest86. The waking vector buffer is not expected to be tested by MemTest86 if it is allocated out because MemTest86 only tests free memory. But current CpuDxe driver "borrows" buffer instead of allocate buffer for waking vector buffer (through allocate & free to get the buffer pointer, backup the buffer data before using it and restore it after using). With this implementation, if the buffer borrowed is not used by any other drivers, MemTest86 tool will treat it as free memory and test it. In order to fix the above issue, CpuDxe changes to allocate the buffer below 1M instead of borrowing it. But directly allocating memory below 1MB causes LegacyBios driver fails to start. LegacyBios driver allocates memory range from "0xA0000 - PcdEbdaReservedMemorySize" to 0xA0000 as Ebda Reserved Memory. The minimum value for "0xA0000 - PcdEbdaReservedMemorySize" is 0x88000. If LegacyBios driver allocate this range failed, it asserts. LegacyBios also reserves range from 0x60000 to "0x60000 + PcdOpromReservedMemorySize", it will be used as Oprom Reserve Memory. The maximum value for "0x60000 + PcdOpromReservedMemorySize" is 0x88000. LegacyBios driver tries to allocate these range page(4K size) by page. It just reports warning message if some pages are already allocated by others. Base on above investigation, one page in range 0x60000 ~ 0x88000 can be used as the waking vector buffer. LegacyBios driver only reports warning when page allocation in range [0x60000, 0x88000) fails. This library is consumed by CpuDxe driver to produce CPU Arch protocol. LagacyBios driver depends on CPU Arch protocol which guarantees below allocation runs earlier than LegacyBios driver. Cc: Ray Ni <ray.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib:Remove.S files for IA32 and X64 archShenglei Zhang2019-04-036-1109/+0
| | | | | | | | | | | | | .nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/BaseUefiCpuLib: Remove .S files for IA32 and X64 archShenglei Zhang2019-04-033-132/+0
| | | | | | | | | | | | | .nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Remove .S files for IA32 and X64 archShenglei Zhang2019-04-035-918/+0
| | | | | | | | | | | | | .nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/UefiCpuPkg.uni: Add the prompt and help informationShenglei Zhang2019-03-191-0/+4
| | | | | | | | | | | | | The prompt and help information are missing in UefiPkg.uni. https://bugzilla.tianocore.org/show_bug.cgi?id=1600 v3:The changes in v1 are duplicated. So update the info. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedlyStar Zeng2019-03-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621 According to Intel SDM as below, the BIT0 should be treated as lock bit, and BIT1 should be treated as disable(1)/enable(0) bit. "11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b" Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/Microcode.c: Add verification before calculate CheckSum32Chen A Chen2019-03-061-11/+20
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1020 Should make sure the TotalSize of Microcode is aligned with 4 bytes before calling CalculateSum32 function. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/Microcode: Fix InComplete CheckSum32 issueChen A Chen2019-03-011-18/+19
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1020 The Microcode region indicated by MicrocodePatchAddress PCD may contain more than one Microcode entry. We should save InCompleteCheckSum32 value for each payload. Move the logic for calculate InCompleteCheckSum32 from the outsize of the do-while loop to the inside. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: restore strict page attributes via #DB in nonstop mode onlyJian J Wang2019-03-013-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1576 The root cause of this issue is that non-stop mode of Heap Guard and NULL Detection set TF bit (single-step) in EFLAG unconditionally in the common handler in CpuExceptionLib. If PcdCpuSmmStaticPageTable is FALSE, the SMM will only create page table for memory below 4G. If SMM tries to access memory beyond 4G, a page fault exception will be triggered and the memory to access will be added to page table so that SMM code can continue the access. Because of above issue, the TF bit is set after the page fault is handled and then fall into another DEBUG exception. Since non-stop mode of Heap Guard and NULL Detection are not enabled, no special DEBUG exception handler is registered. The default handler just prints exception context and go into dead loop. Actually EFLAGS can be changed in any standard exception handler. There's no need to do single-step setup in assembly code. So the fix is to move the logic to C code part of page fault exception handler so that we can fully validate the configuration and prevent TF bit from being set unexpectedly. Fixes: dcc026217fdc363f55c217039fc43d344f69fed6 16b918bbaf51211a32ae04d9d8a5ba6ccca25a6a Test: - Pass special test of accessing memory beyond 4G in SMM mode - Boot to OS with Qemu emulator platform (Fedora27, Ubuntu18.04, Windows7, Windows10) Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.Jiewen Yao2019-02-2819-47/+807
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 We scan the SMM code with ROPgadget. http://shell-storm.org/project/ROPgadget/ https://github.com/JonathanSalwan/ROPgadget/tree/master This tool reports the gadget in SMM driver. This patch enabled CET ShadowStack for X86 SMM. If CET is supported, SMM will enable CET ShadowStack. SMM CET will save the OS CET context at SmmEntry and restore OS CET context at SmmExit. Test: 1) test Intel internal platform (x64 only, CET enabled/disabled) Boot test: CET supported or not supported CPU on CET supported platform CET enabled/disabled PcdCpuSmmCetEnable enabled/disabled Single core/Multiple core PcdCpuSmmStackGuard enabled/disabled PcdCpuSmmProfileEnable enabled/disabled PcdCpuSmmStaticPageTable enabled/disabled CET exception test: #CF generated with PcdCpuSmmStackGuard enabled/disabled. Other exception test: #PF for normal stack overflow #PF for NX protection #PF for RO protection CET env test: Launch SMM in CET enabled/disabled environment (DXE) - no impact to DXE The test case can be found at https://github.com/jyao1/SecurityEx/tree/master/ControlFlowPkg 2) test ovmf (both IA32 and X64 SMM, CET disabled only) test OvmfIa32/Ovmf3264, with -D SMM_REQUIRE. qemu-system-x86_64.exe -machine q35,smm=on -smp 4 -serial file:serial.log -drive if=pflash,format=raw,unit=0,file=OVMF_CODE.fd,readonly=on -drive if=pflash,format=raw,unit=1,file=OVMF_VARS.fd QEMU emulator version 3.1.0 (v3.1.0-11736-g7a30e7adb0-dirty) 3) not tested IA32 CET enabled platform Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/ExceptionLib: Add CET support.Jiewen Yao2019-02-284-8/+12
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 Add information dump for Control Protection exception. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Microcode: Fix incorrect checksum issue for extended tableChen A Chen2019-02-211-9/+73
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1020 The following Microcode payload format is define in SDM spec. Payload: |MicrocodeHeader|MicrocodeBinary|ExtendedHeader|ExtendedTable|. When we verify the CheckSum32 with ExtendedTable, we should use the fields of ExtendedTable to replace corresponding fields in MicrocodeHeader, and then calculate the CheckSum32 with MicrocodeHeader+MicrocodeBinary. This patch already verified on ICL platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Zhang Chao B <chao.b.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/SecCore: Wrong Debug Information for SecCoreChasel, Chiu2019-02-203-36/+54
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1533 When SecCore and PeiCore in different FV, current implementation still assuming SecCore and PeiCore are in the same FV. To fix this issue 2 FVs will be input parameters for FindAndReportEntryPoints () and SecCore and PeiCore will be found in each FV and correct debug information will be reported. Test: Booted with internal platform successfully. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MtrrLib: Fix a bug that may wrongly set memory <1MB to UCRuiyu Ni2019-02-191-41/+18
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1481 Today's MtrrLib contains a bug, for example: when the original cache setting is WB for [0xF_0000, 0xF_8000) and, a new request to set [0xF_0000, 0xF_4000) to WP, the cache setting for [0xF_4000, 0xF_8000) is reset to UC. The reason is when MtrrLibSetBelow1MBMemoryAttribute() is called the WorkingFixedSettings doesn't contain the actual MSR value stored in hardware, but when writing the fixed MTRRs, the code logic assumes WorkingFixedSettings contains the actual MSR value. The new fix is to change MtrrLibSetBelow1MBMemoryAttribute() to calculate the correct ClearMasks[] and OrMasks[], and use them directly when writing the fixed MTRRs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPIChasel, Chiu2019-02-151-4/+4
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524 Previous commit 373c2c5b888d029d7103206556bb85f33d980569, missed one comment change that should be fixed. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPIChasel, Chiu2019-02-153-8/+33
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524 EFI_PEI_CORE_FV_LOCATION_PPI may be passed by platform when PeiCore not in BFV so SecCore has to search PeiCore either from the FV location provided by EFI_PEI_CORE_FV_LOCATION_PPI or from BFV. Test: Verified on internal platform and booting successfully. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Replace AcquireSpinLock.Eric Dong2019-01-151-2/+7
| | | | | | | | | | | | | | | In AcquireSpinLock function, it may call GetPerformanceCounter which final calls PeiService table. This code may also been used by AP but AP should not calls PeiService. This patch update code to avoid use AcquireSpinLock function. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/S3Resume2Pei: check 64BIT_WAKE_F in FACS.OSPMFlags.Eric Dong2019-01-151-3/+3
| | | | | | | | | | | | | | | | | | | ((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) In above code, Facs->OspmFlags should be used instead. EFI_ACPI_4_0_OSPM_64BIT_WAKE__F is a bit in OSPM Enabled Firmware Control Structure Flags field, not in Firmware Control Structure Feature Flags. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1430 Cc: Aleksiy <oleksiyy@ami.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.Eric Dong2019-01-144-78/+99
| | | | | | | | | | | | | | | | | | | | | | | | | V3: Define union to specify the ppi or protocol. V2: 1. Initialize CpuFeaturesData->MpService in CpuInitDataInitialize and make this function been called at the begin of the initialization. 2. let all other functions use CpuFeaturesData->MpService install of locate the protocol itself. V1: GetProcessorIndex function calls GetMpPpi to get the MP Ppi. Ap will calls GetProcessorIndex function which final let AP calls PeiService. This patch avoid GetProcessorIndex call PeiService. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Enhance debug message.Eric Dong2019-01-141-6/+11
| | | | | | | | | | Enhance debug message format to let them easy to read. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Merge StuffRsb.inc files into one in UefiCpuPkg/IncludeHao Wu2019-01-0212-174/+10
| | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Previously, when compiling NASM source files, BaseTools did not support including files outside of the NASM source file directory. As a result, we duplicated multiple copies of "StuffRsb.inc" files in UefiCpuPkg. Those INC files contain the common logic to stuff the Return Stack Buffer and are identical. After the fix of BZ 1085: https://bugzilla.tianocore.org/show_bug.cgi?id=1085 The above support was introduced. Thus, this commit will merge all the StuffRsb.inc files in UefiCpuPkg into one file. The merged file will be named 'StuffRsbNasm.inc' and be placed under folder UefiCpuPkg/Include/. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Update to consume SpeculationBarrierHao Wu2018-12-251-3/+3
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1417 Since BaseLib API AsmLfence() is a x86 arch specific API and should be avoided using in generic codes, this commit replaces the usage of AsmLfence() with arch-generic API SpeculationBarrier(). Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: Fix spelling issueMike Maslenkin2018-12-215-5/+5
| | | | | | | | | | *Excpetion* should be *Exception* Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Mike Maslenkin <mike.maslenkin@gmail.com> CC: Eric Dong <eric.dong@intel.com> CC: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/Cpuid: Add code to support new definition.Eric Dong2018-12-101-5/+141
| | | | | | | | | | | Add code to support new definitions added in SDM 2018'11 version. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Cpuid.h: Sync CPUID definition to latest SDM.Eric Dong2018-12-101-23/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CPUID definition to follow SDM 2018'11 version, changes Include: 1. Add new fields to the existed data structure, impact CPUIDs include: 1. CPUID_THERMAL_POWER_MANAGEMENT 0x06 CPUID_THERMAL_POWER_MANAGEMENT_EAX 2. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX 3. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX 4. CPUID_EXTENDED_STATE 0x0D CPUID_EXTENDED_STATE_MAIN_LEAF_EAX CPUID_EXTENDED_STATE_SUB_LEAF_ECX 5. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX 6. CPUID_INTEL_SGX 0x12 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX 2. Add new data structures which not existed before, impact CPUID includes: 1. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX 3. Remove fields which defined before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX 4. Add new sub leaf which not existed before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03 5. Add new CPUIDs which not exist before, new CPUIDs include: 1. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 2. CPUID_V2_EXTENDED_TOPOLOGY_ENUMERATION 0x1F Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CommonFeature: Always set FEATURE_CONTROL.Lockedk2-stable201811Ruiyu Ni2018-11-141-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1305 The patch reverts commit 1ed6498c4a0210204bf4b95cc0c0cd6623ad6a0b * UefiCpuPkg/CommonFeature: Skip locking when the feature is disabled FEATURE_CONTROL.Lock bit is controlled by feature CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER. The commit 1ed649 fixes a bug that when the feature is disabled, the Lock bit is cleared. But it's a security hole if the bit is cleared when booting OS. We can argue that platform needs to make sure the value of PcdCpuFeaturesUserConfiguration should be set properly to make sure feature CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER is enabled. But it's better to guarantee this in the generic core code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Separate semaphore container.Eric Dong2018-11-111-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current implementation, core and package level sync uses same semaphores. Sharing the semaphore may cause wrong execution order. For example: 1. Feature A has CPU_FEATURE_CORE_BEFORE dependency with Feature B. 2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependency with Feature B. The expected feature initialization order is A B C: A ---- (Core Depends) ----> B ---- (Package Depends) ----> C For a CPU has 1 package, 2 cores and 4 threads. The feature initialization order may like below: Thread#1 Thread#2 Thread#3 Thread#4 [A.Init] [A.Init] [A.Init] Release(S1, S2) Release(S1, S2) Release(S3, S4) Wait(S1) * 2 Wait(S2) * 2 <------------------------------- Core sync [B.Init] [B.Init] Release (S1,S2,S3,S4) Wait (S1) * 4 <----------------------------------------------------- Package sync Wait(S4 * 2) <- Core sync [B.Init] In above case, for thread#4, when it syncs in core level, Wait(S4) * 2 isn't blocked and [B.Init] runs. But [A.Init] hasn't run in thread#3. It's wrong! Thread#4 should execute [B.Init] after thread#3 executes [A.Init] because B core level depends on A. The reason of the wrong execution order is that S4 is released in thread#1 by calling Release (S1, S2, S3, S4) and in thread #4 by calling Release (S3, S4). To fix this issue, core level sync and package level sync should use separate semaphores. In above example, the S4 released in Release (S1, S2, S3, S4) should not be the same semaphore as that in Release (S3, S4). Related BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1311 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Separate semaphore container.Eric Dong2018-11-112-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current implementation, core and package level sync uses same semaphores. Sharing the semaphore may cause wrong execution order. For example: 1. Feature A has CPU_FEATURE_CORE_BEFORE dependency with Feature B. 2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependency with Feature B. The expected feature initialization order is A B C: A ---- (Core Depends) ----> B ---- (Package Depends) ----> C For a CPU has 1 package, 2 cores and 4 threads. The feature initialization order may like below: Thread#1 Thread#2 Thread#3 Thread#4 [A.Init] [A.Init] [A.Init] Release(S1, S2) Release(S1, S2) Release(S3, S4) Wait(S1) * 2 Wait(S2) * 2 <------------------------------- Core sync [B.Init] [B.Init] Release (S1,S2,S3,S4) Wait (S1) * 4 <----------------------------------------------------- Package sync Wait(S4 * 2) <- Core sync [B.Init] In above case, for thread#4, when it syncs in core level, Wait(S4) * 2 isn't blocked and [B.Init] runs. But [A.Init] hasn't run in thread#3. It's wrong! Thread#4 should execute [B.Init] after thread#3 executes [A.Init] because B core level depends on A. The reason of the wrong execution order is that S4 is released in thread#1 by calling Release (S1, S2, S3, S4) and in thread #4 by calling Release (S3, S4). To fix this issue, core level sync and package level sync should use separate semaphores. In above example, the S4 released in Release (S1, S2, S3, S4) should not be the same semaphore as that in Release (S3, S4). Related BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1311 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Adjust Order.Eric Dong2018-11-113-20/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V2 changes: V1 change has regression which caused by change feature order. V2 changes logic to detect dependence not only for the neighborhood features. It need to check all features in the list. V1 Changes: In current code logic, only adjust feature position if current CPU feature position not follow the request order. Just like Feature A need to be executed before feature B, but current feature A registers after feature B. So code will adjust the position for feature A, move it to just before feature B. If the position already met the requirement, code will not adjust the position. This logic has issue when met all below cases: 1. feature A has core or package level dependence with feature B. 2. feature A is register before feature B. 3. Also exist other features exist between feature A and B. Root cause is driver ignores the dependence for this case, so threads may execute not follow the dependence order. Fix this issue by change code logic to adjust feature position for CPU features which has dependence relationship. Related BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1311 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
* UefiCpuPkg/SmmCpu: Block access-out only when static paging is usedJiewen Yao2018-11-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | When static paging is disabled, page table for below 4GB is created and page table for above 4GB is created dynamically in page fault handler. Today's implementation only allow SMM access-out to below types of memory address no matter static paging is enabled or not: 1. Reserved, run time and ACPI NVS type 2. MMIO But certain platform feature like RAS may need to access other types of memory from SMM. Today's code blocks these platforms. This patch simplifies the policy to only block when static paging is used so that the static paging can be disabled in these platforms to meet their SMM access-out need. Setting PcdCpuSmmStaticPageTable to FALSE can disable the static paging. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CommonFeature: Skip locking when the feature is disabledRuiyu Ni2018-11-071-1/+10
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1305 Today's code unconditionally sets the IA32_FEATURE_CONTROL.Lock to 1 no matter the feature is enabled or not. The patch fixes this issue by only setting the Lock bit to 1 when the feature is enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Rollback old change 2a5997f8.Dong, Eric2018-11-052-4/+7
| | | | | | | | | | | | | | | In some special cases, after BSP sends Init-sipi-sipi signal AP needs more time to start the Ap procedure. In this case BSP may think AP has finished its task but in fact AP hasn't began yet. Rollback former change to keep the status which only be used when AP really finished task. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix build failure.Eric Dong2018-10-311-1/+1
| | | | | | | | | | | | | | | | | | | | Build UefiCpuPkg with below configuration: Architecture(s) = IA32 Build target = NOOPT Toolchain = VS2015x86 Below error info shows up: DxeRegisterCpuFeaturesLib.lib(CpuFeaturesInitialize.obj) : error LNK2001: unresolved external symbol __allmul Valid mDependTypeStr type only have 5 items, use UINT32 type cast to fix this error. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix ASSERT for success.Marvin H?user2018-10-301-2/+1
| | | | | | | | | | | | | | | | | | | | | Index is initialized to MAX_UINT16 as default failure value, which is what the ASSERT is supposed to test for. The ASSERT condition however can never return FALSE for INT16 != int, as due to Integer Promotion[1], Index is converted to int, which can never result in -1. Furthermore, Index is used as a for loop index variable inbetween its initialization and the ASSERT, so the value is unconditionally overwritten too. Fix the ASSERT check to compare Index to its upper boundary, which it will be equal to if the loop was not broken out of on success. [1] ISO/IEC 9899:2011, 6.5.9.4 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Fix ASSERT for success.Marvin H?user2018-10-301-2/+1
| | | | | | | | | | | | | | | | | | | | | Index is initialized to MAX_UINT16 as default failure value, which is what the ASSERT is supposed to test for. The ASSERT condition however can never return FALSE for INT16 != int, as due to Integer Promotion[1], Index is converted to int, which can never result in -1. Furthermore, Index is used as a for loop index variable inbetween its initialization and the ASSERT, so the value is unconditionally overwritten too. Fix the ASSERT check to compare Index to its upper boundary, which it will be equal to if the loop was not broken out of on success. [1] ISO/IEC 9899:2011, 6.5.9.4 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix GCC build failure.Dong, Eric2018-10-272-2/+2
| | | | | | | Cc: Liming Gao <liming.gao@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Support combo CPU feature style.Eric Dong2018-10-263-67/+45
| | | | | | | | | | | | Current code assume only one dependence (before or after) for one feature. Enhance code logic to support feature has two dependence (before and after) type. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix build failure for VS2012 and GCC49.Eric Dong2018-10-261-0/+1
| | | | | | | | | | | | Code initialized in function can't be correctly detected by build tool. Add code to clearly initialize the local variable before use it. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean up useless code.Eric Dong2018-10-262-25/+1
| | | | | | | | | | | Remove useless code after change 93324390. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove white space at line end.Eric Dong2018-10-261-2/+2
| | | | | | | | | | | Remove extra white space at the end of line. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
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